JP2770786B2 - Multiplexed ATM / STM converter for structured data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to structured data for converting an ATM cell for transferring information for each channel of an STM signal having a plurality of channels time-divided in a frame period into an original STM signal. Multiplex ATM / STM conversion system.

[0002]

2. Description of the Related Art A fixed frame period (for example, 125 us)
ec or 500 usec)
U Recommendation I. The packet is transferred as an ATM cell in the ATM network by the AAL1 protocol of H.363. The target STM signal is represented by 64 kbps × n (n: any natural number).
A plurality of STM channels are given different VPs (virtual paths), and are transferred as ATM cells. In the conventional multiplexed ATM / STM conversion method for structured data, the ATM cells are stored in a buffer divided into VP units at a CDV (Transfer Delay Fluctuation) value or more that is generated in the ATM network, and the frame condition of the STM network is increased. Is read in conjunction with.
The buffer is initialized at the time of overflow and underflow, and C is generated in the ATM network again.
The reading is resumed after the value of DV is exceeded. In the conventional method, the buffer is fixedly divided according to the speed of the STM signal, or a plurality of STs are provided.
Efficient division operation utilizing regularity existing between M signals is achieved.

FIG. 7 is a block diagram of a main part of this type of ATM / STM conversion circuit. The ATM / STM conversion circuit includes an AAL1 (ATM application layer type 1) processing unit 71, a cell buffer 72, and a write control unit 7.
3, a read control unit 75, a CM unit (control memory unit) 76, and a buffer initialization unit 77. AAL
1 processing unit 71 complies with ITU Recommendation I. The ATM cell S101 in which the STM frame is converted into a cell according to the structured data transfer protocol 363 is received. Upon receiving the ATM cell S101, the AAL1 processing unit 71
The processing of the S layer is performed, and the frame position and VPI (VP identifier) of the STM frame are extracted as one of the results. Next, the AAL1 processing unit 71 sends the ATM cell S101 to the cell buffer 72, and
The write control unit 73 is notified of the arrival of the M cell and the VPI.
The cell buffer 72 is composed of a plurality of banks each having a fixed or a certain amount of efficient memory capacity, and is provided for each ATM cell VP, that is, one bank.
One bank is designated for one VP to store ATM cells. The write control unit 73 manages writing of the ATM cell into the cell buffer. That is, in response to the notification of the arrival of the ATM cell, the write address of the cell buffer 72 is controlled, and the address of the VP from which reading has been completed is held as a free cell address for the subsequent writing.
The CM unit 76 accumulates VP identifier information to be read in accordance with the frame on the STM network side.
The read control unit 75 is notified in accordance with the timing of the TM network, and the buffer initialization control unit 77 is notified that the notification has occurred. The read control unit 75 manages reading of a VP from the cell buffer 72. That is, at times other than the initialization, the VP is read in response to the output of the CM section 76 to generate a time division multiplexed STM frame. The read control unit 75 also stops reading the cell buffer 72 during the time from when the cell buffer 72 is reset during initialization to when the CDV value is exceeded. When a certain bank in the cell buffer overflows or underflows, the buffer initialization unit 77 instructs the write control unit 73 to stop writing to the bank and resets the bank to 0. The buffer initialization unit 77 further receives signals from the write control unit and the read control unit for notifying the occurrence of writing and reading, respectively, and monitors the amount of information stored in the cell buffer 72. A threshold corresponding to the CDV value is set based on the output of the unit 76, and when the amount of information stored in the bank reaches the threshold,
The reading control unit is instructed to read an instruction to end the initialization and restart reading. In this way, after the information amount corresponding to the CDV value is stored in the cell buffer 72, the reading is restarted.

[0004]

In the above conventional method, when accommodating a plurality of STM signals having completely different speeds, the size of the cell buffer corresponding to each VP is changed to the maximum speed STM signal. To make it the corresponding size,
The memory scale of the entire cell buffer becomes extremely large. In addition, the speed condition and frame format of a plurality of STM signals are restricted to some extent, and under these conditions, the regularity between the speeds of the STM signals is used to minimize the memory capacity of all cell buffers. Although a scheme was considered, it was not possible to accommodate a plurality of STM signals having completely different arbitrary speeds at a low memory cost. Either method has the problem that the circuit scale and power consumption increase as a result.

An object of the present invention is to make it possible to always keep the capacity of all cell buffers constant for a plurality of STM signals having completely arbitrary combinations of speeds, and to automatically perform reading to the STM side. The goal is to realize an architecture, and as a result, the capacity of the cell buffer itself is theoretically minimum in any situation, and the circuit size and power consumption are minimized.

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a multiplexed ATM / STM converter for structured data, which comprises a plurality of time-division multiplexed time periods multiplexed in a frame period. An ATM / STM conversion circuit for converting an ATM cell for transferring information of each channel of an STM signal having a channel on a cell basis into an original STM signal.
A TM cell is input, and the ATM cell is set to ITU Recommendation I.
SAR / 363 according to the structured data transfer protocol
The CS layer is processed, and one of the results is STM
An AAL1 processing unit 101 for extracting a frame portion and a virtual path identifier of a frame and outputting the ATM cell;
In order to absorb the cell transfer delay fluctuation of the TM cell,
Cell buffer means for storing TM cells for each virtual path, and when an area for storing each virtual path in the cell buffer means is a cell block, the ATM cell having the virtual path number extracted by the AAL1 processing unit is replaced with the cell. A write control unit for controlling a cell block address for writing to the buffer means, the channel arrangement of the virtual path of the ATM cell to the STM frame is accumulated, and the information specifying the virtual path to be read next from the cell buffer means is stored. , ST
A read control unit that manages a read address to a control memory unit and a cell buffer unit that is read according to a frame condition of the M network, and reads a virtual path specified by an output of the control memory unit from the cell buffer unit. A signal notifying the occurrence of writing and reading is input from the write control unit and the read control unit to monitor the amount of information accumulated in the cell buffer unit, and the information amount satisfies a predetermined condition. And a buffer initialization control unit for performing a buffer initialization process, wherein the cell buffer unit has a plurality of queues for storing the ATM cell payload received from the AAL1 processing unit for each virtual path, and The buffer size of the cell blocks that make up each queue is determined by the sum of the buffer sizes of the queues depending on the channel capacity. Under the condition that is equal to a predetermined value,
It is configured as a shared buffer that is set independently of each other.

[0007] buffer amount of each queue, the virtual path identifier of the virtual path to be stored in the queue and k, the frame length of the virtual path k and F _k, the cell delay variation T
When the ratio (T / T _f ) between the frame period and the frame period T _f is n,
It is set equal to 2nF _k. Further, when the cell transfer delay fluctuation of the ATM network is T, the sum of the buffer amounts is determined to be equal to 2T times the transmission path capacity. Preferably, the plurality of queues form a linked list.

[0008]

Now, assuming that the channel speed of the channel corresponding to the VP with the identifier k is R _k and the CDV value in the network is T, the STM frame output from the ATM network to the STM network matches the original STM frame. , The minimum cell buffer amount of each channel (each VP) required to absorb CDV is known to be 2 × R _k × T. Therefore, the total cell buffer amount _{= Σ (2xR K xT) =} 2TΣR k = 2TR all (1) where, sigma is the sum from k = 1 to k = N, N is the number of channels (the number of VP) . Regardless of the number of channels and the individual channel speeds, the maximum value of the total channel speed is determined by the transmission path capacity and is constant.
The VT value is also constant. Therefore, equation (1) holds true for any combination of the number of channels and the channel speed, and shows the minimum required cell buffer amount. In the decellularization method of the present invention, since a shared buffer type is used as the cell buffer, an arbitrary number of channels and an arbitrary channel speed can be accommodated by the cell buffer amount represented by the equation (1).

[0009] The cell buffer amount described above is expressed as _{2xR K xT = 2x (R K} T f) x (T / T f) = 2nF k (2).

The queue address of each channel in the cell buffer is pointed by the same address as the cell block address of the cell buffer instead of the address management FIFO for each channel.
It is managed by a pointer buffer, which is a shared buffer that performs the same operation as the IFO. Thereby, reduction of the total memory amount is realized. Address management FIF for each channel
When O is used, its size is expressed by equation (3) per channel C = N × log ₂ N (3) where C is the memory amount of the address management FIFO per channel and N Is the number of cell blocks in the cell buffer unit. Therefore, the total memory amount is given by the following equation (4).

C _all = C × L = L × N × log ₂ N (4) Here, C _all is the memory amount of the address management FIFO for all channels, and L is the number of channels. When a pointer buffer is used, its memory amount is expressed by the following equation (5).

C _ptr = N × log ₂ N (5) where C _ptr is the memory size of the pointer buffer,
N is the number of cell blocks in the cell buffer unit. The ratio between Equations (5) and (4) is 1 / L, and a significant reduction in the amount of memory is achieved. The effect increases as L of the total number of channels increases.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings. The multiplex ATM / STM conversion circuit of the present invention comprises:
ITU Recommendation I. This is a circuit for converting an ATM cell in which an STM frame is converted into a cell according to a structured data transfer protocol 363 into an original STM frame. FIG. 1 is a block diagram of one embodiment of a multiplexed ATM / STM conversion circuit. The multiplexed ATM / STM conversion circuit of this embodiment
LL1 processing unit 101, shared buffer 102, write control unit 103, free address FIFO unit 104, read control unit 105, CM unit 106, buffer initialization processing unit 1
07, a frame position detecting unit 108 and an ATM cell S
101 is input to the AAL1 processing unit 101.

The AAL1 processing unit 101 includes an ATM cell S1
When 01 is input, the SAR / CS layer is processed,
As one of the results, the frame position of the STM frame is extracted. The AAL1 processing unit 101 also includes a frame position indicating bit indicating whether or not the user data is a frame, a buffer initialization request bit from the buffer initialization control unit 107, and an ATM which is data stored in the cell block. A P format bit indicating whether the cell is in the P format or the Non-P format is added and transferred to the shared buffer unit 102. FIG. 5 shows a data format of the signal S102 input to the shared buffer unit 102. The AAL1 processing unit 101 also recognizes the VPI (virtual path identifier) of the input cell and notifies the write control unit 103 of the recognition.

The shared buffer unit 102 has a cell buffer unit as will be described later. The cell buffer unit has queues in VP units (channel units on the STM network side), and each queue block is an individual ATM. Stores the cell payload. Hereinafter, this block is referred to as a cell block. Each address in the cell buffer unit is pointed to by two types of addresses: a cell block address designating a cell block, and an offset address which is an offset in each cell block. Shared buffer unit 102
Receives an ATM cell having the format shown in FIG. 5 from the ALL1 processing unit 101 and adds the ATM cell to the cell block address notified from the write control unit 103 in VP units.
The cell is written. The shared buffer unit 102 also
The cell block address S104 for the next input cell is received from the write control unit 103 and held as data. The detailed configuration and operation of the shared buffer unit 102 will be described later with reference to FIG.

Upon receiving the notification of the arrival of a new cell and the VP number of the new cell from the AAL1 processing unit 101, the write control unit 103
The register value S103 of the corresponding VP is selected from the value of the tail register registered in the channel unit on the M network side), and the register value is notified to the shared buffer unit 102 as the cell block address of the VP. Also, the VP
, The cell block address S104 of the next ATM cell to be input from the empty cell block address FIFO unit 104, and the corresponding VP in the write control unit 103.
Update the value of the tail register. At the same time, the new buffer block address written to the tail register is also notified to the shared buffer unit. Further, it notifies the buffer initialization control unit 107 that the writing of the ATM cell has occurred.

The frame position detecting unit 108 monitors On / Off of the frame position indicating bit in the data S110 read from the shared buffer unit 102 (FIG. 5), and when it is On, notifies the reading control unit 105 of the fact. (S111). The CM unit 106 notifies the reading control unit 105 and the buffer initialization processing unit 107 of the VP to be read according to the timing on the STM network side.

The read control unit 105 reads the VP specified by the CM unit 106 in synchronization with the timing on the STM network side based on the frame position (S111) notified from the frame position detection unit 108. Also, the cell block address of the VP that has finished reading is notified to the empty cell address FIFO unit 104 and the buffer initialization processing unit 107 as an empty cell address. The detailed configuration and operation of the reading control unit 105 will be described later with reference to FIG.

The buffer initialization processing unit 107 includes the CM unit 1
06, the VP number S114 is received, and the write control unit 1
03, information indicating that writing has occurred in each VP unit is received as S103, and information indicating that reading has occurred in each VP unit is read from the reading control unit 105 as S103.
Received as 112, the length of the queue for each VP in the cell buffer unit is calculated by the method described later. From the calculation result, the queue is empty and the queue is 2n times the frame length (n: the CDV value in the network is 125 u
sec), the queue is n times the frame length, and the results are converted into buffer initialization control signals (S201, S203), which are then written to the write control unit 103 and read. The control unit 105 is notified. The detailed configuration and operation of the buffer initialization control circuit 107 will be described later with reference to FIG.

The empty cell address FIFO section stores the empty cell block address in the shared buffer
In response to a request from the write control unit 103, the vacant cell block address S104 stored at the head of the vacant cell address FIFO is notified, and the read control unit 105 controls the VP being read. Is completed, the cell block address S11
2 is stored at the end of the empty cell address FIFO as a new empty cell block address.

FIG. 2 is a block diagram showing the configuration of one embodiment of the shared buffer unit 102 of the present invention. The shared buffer unit 102 according to the present embodiment includes a cell buffer unit 202, a pointer buffer unit 201, a latch unit 204, and a counter unit 20.
3 is provided. The cell buffer unit 202 has a queue in VP units (channel units on the STM network side). Each block in the queue stores the payload of an individual ATM cell, and includes an address in cell blocks and an address in each cell block. It is pointed by two types of addresses, offset addresses. The pointer buffer unit 201 stores a pointer (cell block address) of a queue formed in a chained list structure in the cell buffer unit 202.
The latch unit 204 latches an address (cell block address) in cell block units. Counter unit 203
Is No if the input ATM cell is in P format.
A count of 46 or 47 is performed depending on whether the format is the n-P format.

The shared buffer of this embodiment functions as follows. The shared buffer unit 102 includes the AAL1 processing unit 101
5 and transfers the cell block address and the input cell to the cell buffer unit 202 in order to write the data to the cell block address notified from the write control unit. The counter unit 203
P of input data S102 shown in the format of FIG.
Upon receiving a notification from the format bit whether the input cell is in the P format or the Non-P format, count up from 0 to 46 or 47, respectively. The cell buffer unit 202 stores the cell block address S103 notified from the write control unit 103 and the counter unit 20.
3 is recognized as the storage address of the input cell, and the payload of the input cell is written to the internal memory. The latch unit 204 latches a cell block address in which an input cell is written. The pointer buffer unit 201 receives the cell block address S103 latched by the latch unit 204 as an internal memory address, receives the cell block address S104 for the next input cell of the corresponding VP from the write control unit 103, and receives the data as data. Write.

FIG. 6 shows the VP in the shared buffer unit 102.
3 shows a linked list management structure of a unit. Cell buffer unit 20
2 and the pointer buffer unit 201, the addresses specified by the same cell block address signal S103 include a chain list in which a pointer for specifying a position for storing the payload of the ATM cell and a position for storing the next ATM cell are stored. It is shown. In this chained list, the payload of the specified VP is stored at, for example, the position of the cell block address b in the cell buffer unit 202, and is stored next at the position of the same address b in the pointer buffer unit 201. A pointer c indicating the storage position of the ATM cell is stored as data.

FIG. 3 is a block diagram showing an embodiment of the reading control unit 105. The reading control unit 105 includes a head register unit 301 and a down-counting unit 302. The head register unit 301 includes the cell buffer unit 20
2 holds a cell block address S112 at the head of a queue in VP units (STM channel units) existing in each VP. The head register unit 301 also includes a VP
The offset value S113 in the cell block being read out in units (channel units on the STM network side) is also held. The down-counting unit 302 determines whether the cell block being read for each channel on the STM network side is in the P format or not.
A down-count is performed from the value of 46 or 47 to 0, respectively, depending on whether the format is the n-P format.

The reading control unit 105 notifies the CM unit 106 of the VP identifier to be output at the current time (S11).
4), if the cell block of the VP is being read, the offset value S1 of the cell block of the VP
13 is incremented by 1 to obtain an offset address S113 to be newly read. If the offset value of the cell block address during reading of the VP is the maximum (46 bytes if the cell block is in the P format, 47 bytes if the cell block is in the Non-P format), the reading of the cell block is not performed. Since the processing has been completed, the address S115 of the cell block next to the queue in the cell buffer unit 202 of the VP is received from the pointer buffer unit 201 and written into the head register unit 301. At the same time, P of the data (FIG. 5) read from the cell buffer unit 202
ATM cell in cell block newly read by format-bit is P format or Non-P
It is determined whether the format is a format, and an offset value of 46 or 47 is loaded into the down-counting unit 302, respectively.

FIG. 4 is a block diagram of one embodiment of the buffer initialization control unit. Buffer initialization control unit 1 of the present embodiment
07 includes a frame count unit 401, a queue length up / down counter unit 402, and a comparison unit 403. The frame counter unit 401 monitors the output of the CM unit 106 for each VP (for each channel on the STM side) for 125 seconds, measures the frame length, and multiplies the CDV value n of the network set by the system by VP (identifier k). Calculate the buffer threshold value Th _{1, k} for another (for each channel on the STM side) and further double it to obtain a threshold value for each VP (for each channel on the STM side)
Calculating a buffer length Th _{2, k.} The queue length up / down counter unit 402 receives a signal indicating that writing and reading have occurred for each VP from the writing control unit 103 and the reading control unit 105, and receives a signal for each VP in the cell buffer unit 202 (STM). The queue length for each side channel is calculated in cell block units. Comparison unit 403
Compares the queue length output from the queue length up / down counter unit with various outputs from the frame counter unit 401, and generates a buffer initialization signal and a buffer initialization processing end signal. The buffer initialization unit 107 operates as follows. The frame counter 401 decodes the VP identifier k (signal S114) input from the CM 106,
For each VP identifier, the number of occurrences of the VP identifier within a certain frame period is counted, and the frame length of each VP is measured. Each VP is 1: 1 with each channel on the STM network side.
There is a corresponding relationship. The frame length for each VP is multiplied by a CDV value (a value obtained by dividing the CDV value in the ATM network by 125 μs) n measured in units of the frame period to obtain the VP.
A first threshold value Th _{1, k} is generated for each (identifier k).
Further, a second threshold value Th _{2, k} is generated by multiplying the frame length of each VP by 2n. Th _{1, k} corresponds to the fluctuation of the average cell rate due to the transfer delay fluctuation of the ATM network.
Th _{2, k} is the minimum buffer amount necessary to absorb the transfer delay fluctuation, and limits the buffer length of the queue for storing the VP. The queue length up / down counter is
It has an up / down counter for each VP (for each channel on the STM network side), receives the number of times writing has occurred in each VP unit from the writing control unit 103 as a signal S103, and reads from the reading control unit 105 for each VP. The number of occurrences of the stocking is received as a signal S112, and the queue length is measured for each VP in the cell buffer unit 202. The comparison unit 403 receives the T from the frame counter unit 401 for each VP (identifier k) (for each channel).
h _{1, k} , Th _{2, k} and queue length up / down counter 4
From the queue lengths from 02, the queue is empty, the queue is 2n times the frame length (= Th _{2, k} ), and the queue is n times the frame length (= Th _{1, k} ). The comparison is performed, the result is converted into a buffer initialization request signal (S201, S203) for buffer initialization control, and the result is notified to the write control unit 103 and the read control unit 105.

The ATM / STM conversion circuit having the above configuration operates as follows as a whole. First, when the queue length of each VP (each channel of the STM signal) in the cell buffer unit 202 becomes 0, or when the queue length becomes Th2 _{, k} , initialization processing is performed on the queue. . In the initialization process, after resetting the queue length to 0, the frame length (T
This is a process of starting reading data to the STM network after accumulating input ATM cells for h _{1, k} ). For this purpose, the buffer initialization control unit 107 controls the buffer initialization request signal S2
01 is output to the write control unit 103. When writing the next input cell in the VP of the queue to the cell buffer unit 202, the write control unit 103 sets the buffer initialization request bit of the VP to On, and transfers the input ATM cell after the VP to the cell buffer unit 202. Stop writing. The read control unit 105 continues reading the VP from the queue, and when detecting the On of the buffer initialization request bit in the read data, the write control unit 1
03 is notified that the reading of the queue is completed and the queue is empty (S202). After receiving the notification, the write control unit 103 restarts writing the input ATM cell of the VP into the cell buffer unit 202. The buffer initialization control unit 107 monitors the queue length of the VP (k), and when the queue length exceeds Th _{1, k} , the reading restart instruction S203.
Is notified to the reading control unit 105. Read control unit 1
05 restarts reading the VP from the queue.

When the frame position detecting section 108 detects On of the frame position bit of the data read from the cell buffer section 202, the reading control section 1 reads that fact.
05 is notified (S111). The CM unit 106
CM information S11 for specifying the first time slot in the 8 kHz frame of each channel of the STM signal
4 is output with the first time slot bit of the CM information set to On. Read control unit 10
5 indicates that the first time slot bit of the CM information S114 from the CM unit 106 is ON when the frame position indication signal S111 is received from the frame position detection unit 108.
If not, reading from the cell buffer unit 202 to the STM channel is stopped, and reading is started when the first time slot bit of the CM information is turned on. Thereby, the phase of the frame stored in the cell buffer unit 202 and the phase of the frame read out to the STM network are synchronized for each VP.

[0029]

As described above, the present invention has the following effects. 1) By using a shared memory type buffer as a cell buffer, a plurality of structured (i.e., having frames) CBR (Continuous) with arbitrarily combined numbers of channels and channel speeds.
Continuous Bit Rate) VP can be input and converted to an STM signal. 2) The frame phase which is an integral multiple of 8 kHz between channels can be easily adjusted in 8 kHz units on the STM side. These processes are automatically performed only by external information from the control memory. 3) The cell buffer amount can be realized with the theoretically lowest memory cost.
4) Since the write side of the cell buffer is performed in units of cell blocks, the address management of the cell buffer is simplified. 5) Connection of the queue of each channel in the cell buffer is managed by a pointer buffer which is a shared buffer that is pointed to by the same address as the cell block address of the cell buffer and performs the same operation. FI that manages queues
Can be configured without the need for FO. 6) In summary,
Completely free ATM / STM conversion can be realized with near minimum hardware cost and power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall view of the architecture of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a shared memory unit according to the present invention.

FIG. 3 is a block diagram showing a configuration of a reading control unit according to the present invention.

FIG. 4 is a block diagram illustrating a configuration of a buffer initialization control unit according to the present invention.

FIG. 5 is a diagram showing a data format in the present invention.

FIG. 6 shows a management structure of a linked list in a shared buffer unit.

FIG. 7 is a block diagram showing an example of a conventional system.

[Explanation of symbols]

101 AAL1 processing unit 102 Shared buffer unit 103 Write control unit 104 Free address FIFO unit 105 Read control unit 106 CM unit 107 Buffer initialization control unit 108 Frame position detection unit 201 Pointer buffer unit 202 Cell buffer unit 203 Counter unit 204 Latch unit 301 Head register section 302 Down counter section 401 Frame counter section 402 Queue length up / down counter section 403 Comparison section S101 ATM cell signal S102 Internal data format (ATM input side) S103 Cell block address being written (VP unit) S104 Next ATM Cell block address (VP unit) for cell input S105 Offset address in cell block address being written S110 Internal data format Mat (STM output side) S111 Frame position indication signal S112 Cell block address being read (in VP) S113 Offset address (in VP) in cell block address being read S114 CM information S115 Cell block address to be read next (V
(P unit) S201 Buffer initialization request signal (VP unit) S202 Signal notifying that the queue is empty (V
(P unit) S203 Reading restart instruction signal from queue (VP unit)

Claims (7)

(57) [Claims] An arbitrary time-division multiplexed frame period
An ATM / STM conversion circuit for converting an ATM cell for transferring information for each channel of an STM signal transmitting an arbitrary number of channels having a transmission speed of each cell into an original STM signal, and a cell transfer delay of the ATM network. If the fluctuation is T
In this case, the ATM cell is input, and the ATM cell is input to ITU Recommendation I. 363 according to the structured data transfer protocol
AAL1 processing unit 101 that performs processing of the AR / CS layer, extracts the frame location of the STM frame and the virtual path identifier as one of the results, and outputs the ATM cell
Cell buffer means for storing the ATM cell for each virtual path in order to absorb the cell transfer delay fluctuation of the ATM cell; and, in the cell buffer means, an area for storing each virtual path as a cell block. A write control unit that outputs a cell block address for writing the ATM cell having the virtual path number extracted by the AAL1 processing unit to the cell buffer unit; and a channel arrangement of the virtual path of the ATM cell to the STM frame. A control memory unit in which information specifying a virtual path to be read next from the cell buffer means is read in accordance with the frame conditions of the STM network, and a read address to the cell buffer means is managed. Read the virtual path specified by the output of the section from the cell buffer means. A readout control unit, a signal for notifying the occurrence of writing and reading from the writing control unit and the reading control unit are input, and the amount of information stored in the cell buffer unit is monitored. Multiple ATM / ST having a buffer initialization control unit for performing a buffer initialization process when a condition is satisfied
In the M apparatus, the cell buffer unit stores the payload of the ATM cell received from the AAL1 processing unit for each virtual path .
Has a plurality of cell blocks constituting a queue,
The cell buffer means is equal to 2T times the transmission path capacity.
We have had total buffer quantity, of any speed any number channels
A shared bar that allows cells to use any cell block
Is configured as Ffa manages the address of a free cell blocks of the shared buffer,
An empty cell block address is requested by the write control unit.
Address to the write control unit and read the virtual path.
When reading is completed, the
The cell block in which the virtual path was stored
Store address as new free cell block address
The read control unit has an empty cell block address management unit for each time the reading of the virtual path is completed.
Empty the cell block address where the virtual path was stored.
A multiplexed ATM / STM converter for structured data, which notifies the cell block address management unit of the data. 2. The vacant cell block address management unit is an FI
Empty cell block of shared buffer with FO register
Addresses are managed on a first-in first-out basis and write control
At the beginning of the FIFO register in response to
Write control of the empty cell block address
To the virtual path, and the read control
When the reading of the cell block is completed,
Address as a new free cell block address,
2. The device according to claim 1, wherein the data is stored at the end of the O register . 3. Reading from the cell buffer means to the STM network.
Frame to detect the frame start position bit of the
Frame position detecting means, and the frame position detecting means
When the frame head position is detected, the head position indication signal
Is output to the reading control unit, and the reading control unit outputs the frame from the frame position detecting unit.
When a position indication signal is received,
The part specifies the first time slot of the STM frame
When the control memory information is not output
Is read from the cell buffer means to the STM network
Is stopped, and the control memory unit
Control memory information specifying the first time slot
2. The reading control is started when the information is output.
The described device. 4. The apparatus according to claim 1, wherein the plurality of queues form a linked list. 5. The shared buffer has a cell buffer unit, a pointer buffer unit, a latch unit, and a counter unit. The cell buffer unit has a queue for each virtual path, and each cell block of the queue is an individual cell block. The address of the information that stores the payload of the ATM cell and is stored in the cell block is:
The pointer buffer section is specified by two types of addresses, a cell block address specifying a cell block and an offset address specifying a storage position in each cell block. The pointer buffer section is configured by a chained list in the cell buffer section. A pointer for the queue is stored, the pointer specifies a cell block address of a cell block next to a cell block constituting the queue, and the latch unit
The cell block address is latched, and the counter unit counts 46 or 47 according to whether the input ATM cell is in the P format or the Non-P format, and specifies the offset address. An apparatus according to claim 4. 6. The read control unit has a head register unit and a down-count unit, and the head register unit stores a cell block address for performing reading for each virtual path, Generates an offset address for stocking, and checks whether the cell block read for each channel on the STM network side is in P format.
The apparatus according to claim 1, wherein the apparatus counts down from a value of 46 or 47 to 0, respectively, depending on whether it is in nP format. 7. The buffer initialization control unit includes a frame count unit, a queue length up / down counter unit, and a comparison unit. The frame counter unit monitors an output of the control memory unit for each virtual path (k) during a frame period. To calculate a frame length (F _k ), multiply the frame length by the ratio n, and obtain a first buffer threshold T for each virtual path.
h _{1 , k} is further calculated, and Th _{1 , k} is doubled to calculate a _second buffer threshold value Th _{2 , k} for each virtual path. A signal for notifying the occurrence of writing and reading is input from the control unit, and the queue length for each virtual path in the cell buffer unit is calculated for each cell block, and the comparison unit outputs the queue length up / down counter unit. The queue length is compared with the output of the frame counter unit. For each virtual path (k), the queue is reset when the queue length becomes 0 or Th _{2 , k,} and then the queue length becomes T.
Until h _{1 and k} , a buffer initialization signal for instructing the write control unit and the read control unit to execute the writing while stopping the reading of the queue is generated, and the queue length of the queue is set to Th _{1. , K} , the buffer initialization process end signal is generated to resume reading when the number reaches the threshold value.