JP2764988B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a microstructured bipolar semiconductor device.

[Prior Art] Conventionally, this type of bipolar type semiconductor device is called a planar type, in which impurities are selectively introduced from above a surface of an N-type epitaxial layer formed on a P-type substrate to form a P-type region, N ⁺
It has a structure in which a mold region is formed.

[Problems to be solved by the invention]

Since the above-described conventional semiconductor device is of a planar type (including its deformation), the area occupancy of the transistor on the semiconductor chip is high and the size of the active region is also increased by including the alignment margin in the lithography process. Therefore, there are obstacles to miniaturization and speeding up.

[Means for solving the problem]

In the semiconductor device of the present invention, the N-type semiconductor layer is formed by stacking an N-type semiconductor layer on a P-type semiconductor substrate.
A P-type base layer provided in contact with the side surface of the groove, a base extraction region reaching the surface of the semiconductor chip through an insulator in the groove, and the P-type base layer. An NPN transistor having an N-type emitter layer and an emitter extraction region reaching an upper surface of the semiconductor chip through an insulator in the trench.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention.

In this embodiment, an insulator (a silicon oxide film 5, a polycrystalline silicon layer 6, a silicon oxide film) of a semiconductor chip formed by laminating an N-type epitaxial layer 3 on a P-type silicon substrate 1 is used.
The P-type base layer provided in contact with the side surface of the above-described groove is provided in the N-type epitaxial layer 3 (element formation region) partitioned and insulated and separated by the groove filled with (14, 16) and the P-type buried layer 2. 9 and a base extraction region (P-type polysilicon layer 7,
15) and the N ⁺ -type emitter layer 12 provided on the P-type base layer 9
And an NPN transistor having an emitter extraction region (N-type polycrystalline silicon layer) reaching the surface of the semiconductor chip through the insulator in the above-described groove.

 Next, the manufacturing method of this embodiment will be described.

2 (a) to 2 (c) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of this embodiment.

First, as shown in FIG. 2 (a), 10 ¹⁴ to 10 ¹⁶ pieces / cm ³
The P-type silicon substrate 1 having an impurity concentration of a surface concentration of 10 ¹⁶ ~
Provide a P-type buried layer 2 with 10 ¹⁸ / cm ³ impurity and thickness
0.8Myuemu～7myuemu, grow N-type epitaxial layer 3 having an impurity concentration ^{1015 17} months / cm ^3. Thereafter, a groove 4 having a depth of 0.7 μm to 6.5 μm is formed until it contacts the P-type buried layer 2, and the surface thereof is oxidized to form a silicon oxide film 5 having a thickness of 0.2 μm to 0.5 μm. Next, as shown in FIG. 2 (b), after the groove is filled with a non-doped polycrystalline silicon layer 6 (a silica film may be used), the above-mentioned groove is filled with 0.5 μm.
The hole is opened again at a depth of ５5 μm. At this time, a groove (at 11) is also dug in the N-type epitaxial layer 3 in the element formation region. A P-type polycrystalline silicon layer 7 is buried in the opening,
Heat treatment is performed to form the P-type base layer 9 and simultaneously oxidize the P-type polycrystalline silicon layer 7 to a depth of 0.3 μm to 2 μm. Next, the silicon oxide layer 8 thus formed is deposited to a thickness of 0.1
The groove is opened again while leaving a thickness of 0.5 μm to 0.5 μm. N
Buried type polycrystalline silicon layers 10 and 11, heat treatment is performed N ⁺
The mold emitter layer 12 is formed.

When the N ⁺ -type emitter layer 12 is formed, an N ⁺ -type collector contact region is simultaneously formed by diffusion from the N-type polycrystalline silicon layer 11.

Thereafter, as shown in FIG. 2 (c), an opening is formed through the N-type polycrystalline silicon layer 10 and the silicon oxide layer 8 to provide a base lead region in the groove, and a silicon oxide layer 14 is formed on the side surface. The P-type polycrystalline silicon layer 15 is embedded.

Thereafter, as shown in FIG. 1, a P-type polysilicon layer
A groove having a width of 0.5 μm to 1 μm which reaches the non-doped polycrystalline silicon layer 6 is provided in the center of 15. Next, the silicon oxide layer 16 is formed by thermal oxidation to fill the groove.

Finally, the necessary contact holes are provided and the emitter electrodes E,
A base electrode B and a collector electrode C are provided.

Comparing this embodiment with a conventional isoplanar transistor, it was found that the area occupancy of the transistor having a collector current of 10 mA was reduced to about 1/2.

The dimensions of the emitter layer and the base layer in the depth direction are determined by the etching depth, and since there is no step of aligning the emitter layer and the base layer, the dimensional accuracy is improved as compared with the planar type.

〔The invention's effect〕

As described above, the present invention provides the emitter layer and the base layer in contact with the side surface of the insulating isolation groove,
Since an NPN transistor with a small area occupancy and a high accuracy can be realized, there is an effect that ultra-miniaturization and high speed operation of a large output transistor can be achieved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor chip showing one embodiment of the present invention,
2 (a) to 2 (c) are cross-sectional views of semiconductor chips arranged in the order of steps for explaining a manufacturing method according to an embodiment of the present invention. 1 ... P-type silicon substrate, 2 ... P-type buried layer, 3 ...
N-type epitaxial layer, 4 groove, 5 silicon oxide film, 5 polycrystalline silicon layer, 7 P-type polycrystalline silicon layer, 8 silicon oxide layer, 9 P-type base layer, 1
0,11 ... N-type polycrystalline silicon layer, 12 ... N ⁺ type emitter layer, 13 ... N ⁺ type collector contact region, 14 ... Silicon oxide layer, 15 ... P-type polycrystalline silicon layer, 16 ... ... a silicon oxide layer.

Claims (1)

(57) [Claims] 1. A semiconductor chip formed by laminating an N-type semiconductor layer on a P-type semiconductor substrate, a groove filled with an insulator, and the N-type semiconductor layer separated and separated by a P-type buried layer. A P-type base layer provided in contact with the side surface of the groove and a base extraction region reaching the surface of the semiconductor chip through an insulator in the groove; and an N-type base provided in the P-type base layer.
A semiconductor device comprising: an NPN transistor having a mold emitter layer and an emitter extraction region reaching an upper surface of a semiconductor chip through an insulator in the trench.