JP2757594B2 - Film carrier equipment - Google Patents
Film carrier equipmentInfo
- Publication number
- JP2757594B2 JP2757594B2 JP3176601A JP17660191A JP2757594B2 JP 2757594 B2 JP2757594 B2 JP 2757594B2 JP 3176601 A JP3176601 A JP 3176601A JP 17660191 A JP17660191 A JP 17660191A JP 2757594 B2 JP2757594 B2 JP 2757594B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- solder
- copper
- film carrier
- via hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910000679 solder Inorganic materials 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 19
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 238000005476 soldering Methods 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 229910052751 metal Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 67
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 32
- 229910052802 copper Inorganic materials 0.000 description 22
- 239000010949 copper Substances 0.000 description 22
- 239000011889 copper foil Substances 0.000 description 10
- 229920001721 polyimide Polymers 0.000 description 9
- 239000004642 Polyimide Substances 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 238000007733 ion plating Methods 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 5
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 239000012790 adhesive layer Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- OAKJQQAXSVQMHS-UHFFFAOYSA-N Hydrazine Chemical compound NN OAKJQQAXSVQMHS-UHFFFAOYSA-N 0.000 description 2
- 229910000978 Pb alloy Inorganic materials 0.000 description 2
- 229920001646 UPILEX Polymers 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 2
- 229920006332 epoxy adhesive Polymers 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910017755 Cu-Sn Inorganic materials 0.000 description 1
- 229910017927 Cu—Sn Inorganic materials 0.000 description 1
- 229910017985 Cu—Zr Inorganic materials 0.000 description 1
- 241000196324 Embryophyta Species 0.000 description 1
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000005266 casting Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000010891 electric arc Methods 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000010998 test method Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はバイアホールを有するフ
ィルムキャリア装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a film carrier device having a via hole.
【０００２】[0002]
【従来の技術】最近ＩＣの薄型高密度実装化に対応し
て、ＩＣチップをフィルムキャリアに取り付けて実装す
るＴＡＢ（テープキャリア方式）が用いられている。こ
のようなＴＡＢにおいては、例えばポリイミドフィルム
などの絶縁層の上面に信号層、下面に電源層を有してい
るが、下面の電源層から配線をとるためなどの目的でバ
イアホールが設けられる。2. Description of the Related Art In recent years, TAB (tape carrier type), in which an IC chip is mounted on a film carrier and mounted, has been used in response to the trend toward thinner and higher density mounting of ICs. In such a TAB, for example, a signal layer is provided on the upper surface of an insulating layer such as a polyimide film, and a power supply layer is provided on the lower surface. However, via holes are provided for the purpose of wiring from the power supply layer on the lower surface.
【０００３】フィルムキャリア装置に形成されたバイア
ホールを接続する手段として、従来例えば図５に示すよ
うにスパッタ法で銅をコートして銅膜層５を形成する方
法がある。すなわち例えば厚さ２５μｍの銅箔１、厚さ
７５μｍの絶縁層３に形成されたバイアホール４をスパ
ッタ法による厚さ４μｍの銅膜層５により接続してい
る。また、図６には例えば厚さ７５μｍのポリイミド絶
縁層３の両面に厚さ２５μｍの銅箔１、７をエポキシ系
接着剤２、６により張り合わせた後、径０．２〜０．６
ｍｍのスルーホール８を形成したものであるが、その接
続法として、銅の電気めっき法や無電解めっき法により
めっき層９を形成したものである。いずれの方法も、バ
イアホールを形成する壁面を介して電気的に接続するも
のである。As a means for connecting via holes formed in a film carrier device, there is a conventional method of forming a copper film layer 5 by coating copper by sputtering as shown in FIG. That is, for example, a copper foil 1 having a thickness of 25 μm and a via hole 4 formed in an insulating layer 3 having a thickness of 75 μm are connected by a copper film layer 5 having a thickness of 4 μm by sputtering. In FIG. 6, for example, copper foils 1 and 7 each having a thickness of 25 μm are attached to both surfaces of a polyimide insulating layer 3 having a thickness of 75 μm with epoxy adhesives 2 and 6, and then a diameter of 0.2 to 0.6.
The through-hole 8 is formed with a thickness of 8 mm, and as a connection method thereof, a plating layer 9 is formed by a copper electroplating method or an electroless plating method. In either method, electrical connection is made via a wall surface forming a via hole.
【０００４】前記スパッタ法による接続では、ポリイミ
ド絶縁層が発熱し、熱変形するうえ、用いるポリイミド
の種類（例えば商品名カプトンＨ、ユーピレックスＳ
等）によっては、形成される銅膜層の密着力が３０ｇ／
ｃｍ以下と弱く、密着力向上のためにはスパッタの後、
特殊なプラズマ処理が必要であった。まためっき法は、
一般に密着力が良いものの、やはり用いるポリイミドの
種類（例えば商品名カプトンＤ、ユーピレックスＳ等）
によってはめっきの密着性が悪く、熱ストレスに対する
信頼性に乏しいという問題がある。さらに銅の電気めっ
きでは５〜１０分、無電解めっきでは１〜２時間とめっ
きに時間がかかること、湿式で行なわれるためイオン性
物質がバイアホールや層間に残留して、マイグレーショ
ンや配線腐食原因となることなどの問題もある。[0004] In the connection by the sputtering method, the polyimide insulating layer generates heat and is thermally deformed. In addition, the kind of polyimide used (for example, Kapton H, Upilex S, trade name) is used.
And the like, the adhesion of the formed copper film layer is 30 g /
cm or less, and after sputtering to improve adhesion,
Special plasma treatment was required. The plating method is
In general, although the adhesive strength is good, the kind of polyimide to be used (for example, Kapton D, Upilex S, etc.)
In some cases, there is a problem that the adhesion of the plating is poor and the reliability against thermal stress is poor. In addition, electroplating of copper takes 5 to 10 minutes, and electroless plating takes 1 to 2 hours. It takes place in a wet process, and ionic substances remain between via holes and layers, causing migration and wiring corrosion. There are also problems such as becoming.
【０００５】[0005]
【発明が解決しようとする課題】フィルムキャリア装置
の絶縁層の両面に有する導電層間をバイアホールを介し
て電気的に接続する上記従来技術の課題に鑑み、信頼性
が高く、容易に接続できる方法が求められていた。本発
明は、このような要望に応えるものである。In view of the above-mentioned problem of the prior art in which conductive layers provided on both sides of an insulating layer of a film carrier device are electrically connected through via holes, a highly reliable and easily connectable method. Was required. The present invention addresses such a need.
【０００６】本発明は導電層間の電気的接続を半田ボー
ル等の溶融によるバイアホールの埋め込みを行なった
後、蒸着法、イオンプレーティングなどにより他の導電
層を形成することにより実現するものであり、加工作業
が極めて簡単で、バイアホールを介しての電気的接続の
信頼性の高いフィルムキャリア装置の製造方法を提供す
るものである。The present invention realizes electrical connection between conductive layers by filling via holes by melting solder balls or the like and then forming another conductive layer by vapor deposition, ion plating, or the like . Another object of the present invention is to provide a method of manufacturing a film carrier device which is extremely simple in processing operation and has high reliability in electrical connection via via holes.
【０００７】[0007]
【課題を解決するための手段】上記目的を達成するため
に本発明によれば、絶縁層の両面に第１および第２導電
層を有し、これらの導電層間がバイアホールを介して電
気的に接続されてなるフィルムキャリア装置の製造方法
であって、前記第１導電層の上面に形成されているバイ
アホールを半田ボールまたは半田線を挿入し加熱溶解し
てなる半田により実質的に充填した後、前記により充填
した半田の露出表面側から真空蒸着法またはイオンプレ
ーティング法を施すことにより、この半田表面に形成さ
れた蒸着層と一体の前記第２導電層を形成することを特
徴とするフィルムキャリア装置の製造方法が提供され
る。以下図面に基づき、本発明をさらに詳細説明する。According to the present invention, there is provided, in accordance with the present invention, first and second conductive layers on both surfaces of an insulating layer, and these conductive layers are electrically connected via via holes. a manufacturing method <br/> of connected comprising a film carrier device, a bi <br/> via holes formed on the upper surface of the first conductive layer by inserting a solder ball or solder wire was heated and dissolved
After substantially filled by a solder made of Te, filled by the
From the exposed surface side of the solder
By applying the soldering method, the solder
The method of manufacturing the film carrier and wherein is provided to form a vapor deposited layer and the second conductive layer of the integral that. Hereinafter, the present invention will be described in more detail with reference to the drawings.
【０００８】本発明において第１導電シート層としては
銅箔シート、銅合金（Ｃｕ−Ｚｒ，Ｃｕ−Ｓｎ合金）箔
シート、４２系合金（Ｆｅ−４２％Ｎｉ合金、Ｆｅ−４
２％Ｎｉ−３％Ｃｏ合金）箔シートなどが挙げられる。
第１導電シート層の厚さは通常４〜３５μｍである。ま
た、絶縁層３は商品名カプトンＤ、カプトンＨ、ユーピ
レックスＳなどで知られるポリイミドフィルム、ガラス
エポキシ、ＢＴレジンポリエステルフィルム等が挙げら
れるが、通常ポリイミドフィルムが好んで用いられる。
絶縁層の厚さは通常２５〜１５０μｍである。In the present invention, as the first conductive sheet layer, a copper foil sheet, a copper alloy (Cu-Zr, Cu-Sn alloy) foil sheet, a 42 alloy (Fe-42% Ni alloy, Fe-4)
2% Ni-3% Co alloy) foil sheet.
The thickness of the first conductive sheet layer is usually 4 to 35 μm. The insulating layer 3 may be a polyimide film known as Kapton D, Kapton H, Iupirex S, or the like, a glass epoxy, a BT resin polyester film, or the like. Usually, a polyimide film is preferably used.
The thickness of the insulating layer is usually 25 to 150 μm.
【０００９】バイアホールは、通常絶縁層にフォトレジ
スト層を形成し、それをマスクとしてヒドラジン等の液
中でフィルムシートの一部の領域をエッチングすること
により形成することができる。バイアホールの直径は通
常０．０５ｍｍから０．６ｍｍの範囲にあることが好ま
しい。その理由としては、多層配線でしかも配線ピッチ
が１４０μｍと狭くなる傾向にあるので０．６ｍｍを越
えるスペースを確保するのが困難である。また直径が
０．０５ｍｍよりも小さくなると本発明で使用する半田
ボールや半田線の挿入が実際上困難となる。[0009] The via hole can be usually formed by forming a photoresist layer on an insulating layer, and etching a part of the film sheet in a liquid such as hydrazine using the photoresist layer as a mask. Preferably, the diameter of the via hole is usually in the range of 0.05 mm to 0.6 mm. The reason is that it is difficult to secure a space exceeding 0.6 mm because the wiring pitch tends to be as narrow as 140 μm in the multilayer wiring. When the diameter is smaller than 0.05 mm, it becomes practically difficult to insert the solder balls and the solder wires used in the present invention.
【００１０】本発明におけるバイアホール内の埋め込み
は、例えば図１に示すように半田ボール若しくは半田線
を加熱溶融して絶縁層の上面高さ付近まで半田１０によ
り埋め込む。半田の埋め込み高さは絶縁層の上面高さに
なるべく合わせることが好ましい。半田の組成としては
Ｓｎが通常１００〜５％の範囲にあるものが好んで使用
される。半田ボールは常法により通常直径３５〜４００
μｍの半田線（ワイヤ）を加熱して製造する。半田線は
バイアホールに挿入し長さ５５〜７００μｍに切断す
る。In the embedding in the via hole in the present invention, for example, as shown in FIG. 1, a solder ball or a solder wire is heated and melted, and the solder ball or solder wire is buried near the upper surface of the insulating layer with the solder 10. It is preferable that the embedded height of the solder is adjusted to be as high as the upper surface of the insulating layer. As for the composition of the solder, one having Sn in the range of usually 100 to 5% is preferably used. Solder balls usually have a diameter of 35 to 400 by the usual method.
It is manufactured by heating a μm solder wire. The solder wire is inserted into the via hole and cut to a length of 55 to 700 μm.
【００１１】図７に半田ボールの埋め込み工程（装置）
の一例を示した。キャピラリー２２の孔に通した半田ワ
イヤ２３の先端を、ライン２６からのＡｒ＋１０％Ｈ2
等の雰囲気中でアーク放電により熔解し、ボール２４を
形成する。この時ボールの径はワイヤーの３倍の径迄作
ることができるのでバイアホールに１回の埋め込みで完
全に充填する事ができる。ボールのバイアホールへの接
合は超音波併用型の熱圧着法により行なうことができ
る。キャピラリーを垂直方向に移動させながら、クラン
パーを閉じボールの切断を行なう。この方法により、均
一な大きさのボールを再現性良く埋め込むことができ
る。FIG. 7 shows an embedding process (apparatus) of a solder ball.
An example was shown. The tip of the solder wire 23 passed through the hole of the capillary 22 is connected to Ar + 10% H2 from the line 26.
The ball 24 is formed by melting in an atmosphere such as the above by arc discharge. At this time, the diameter of the ball can be made up to three times the diameter of the wire, so that the via hole can be completely filled by one embedding. The bonding of the ball to the via hole can be performed by a thermocompression bonding method using ultrasonic waves. While moving the capillary vertically, the clamper is closed and the ball is cut. According to this method, a ball having a uniform size can be embedded with good reproducibility.
【００１２】第２の導電層１１は埋め込まれた半田層１
０と共に絶縁沿う３の上面に形成され、これによりバイ
アホールを介して電気的に接続される。第２導電層１１
は真空蒸着法、イオンプレーティングにより形成され
る。第２導電層に用いる金属としては銅、Ｎｉ下地銅で
あるが銅であることが好ましい。第２導電層１１が形成
されたあとは常法によりレジスト塗布、パターンニン
グ、導電層のエッチングを行い、微細配線の多層構造の
フィルムキャリア装置を得ることができる。The second conductive layer 11 is formed by the embedded solder layer 1.
Along with 0, it is formed on the upper surface of the insulation 3 and is thereby electrically connected via the via hole. Second conductive layer 11
Is formed by vacuum evaporation and ion plating.
You. The metal used for the second conductive layer may be copper or copper under Ni, but preferably copper. After the second conductive layer 11 is formed, resist coating, patterning, and etching of the conductive layer are performed by a conventional method to obtain a film carrier device having a multilayer structure of fine wiring.
【００１３】本発明の別の態様を図４に示す。図のよう
に、半田ボールあるいは半田線の熔解物１０と共に絶縁
層３の上面に銅層７を設けているが、その層にはバイア
ホールの径よりも小さい穴を開けている。こうすること
によって、半田の熔解の際に発生するガスの放出が容易
となり、更に半田１０が銅層７の上面に流出するのを防
止し、第１導電シート層をバイアホールを介して銅層７
と確実に接続される。Another embodiment of the present invention is shown in FIG. As shown in the figure, a copper layer 7 is provided on the upper surface of the insulating layer 3 together with the solder balls or the solder wire melt 10, and a hole smaller than the diameter of the via hole is formed in that layer. This facilitates the release of gas generated when the solder is melted, further prevents the solder 10 from flowing out to the upper surface of the copper layer 7, and connects the first conductive sheet layer to the copper layer via a via hole. 7
Is securely connected.
【００１４】[0014]
【実施例】以下、本発明を実施例に基づき具体的に説明
する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on embodiments.
【００１５】（実施例１）直径３００μｍのバイアホー
ルが形成された厚さ１００μｍの絶縁層（ポリイミド：
宇部興産社製、商品名ユーピレックスＳ）３にエポキシ
系接着剤２で厚さ２５μｍの銅箔シート１を貼り合わせ
た。次いで径が３００μｍの半田（８０％Ｓｎ−２０％
Ｐｂ合金）線を８０個のバイアホールに挿入切断後、約
２１０℃で加熱した。この段階の構造を図１に断面図と
して示す。次いでこの構造の絶縁層３および半田層１０
の上面に真空蒸着法で厚さ４μｍの銅層１１を形成し、
その後レジスト塗布、パターンニング、銅層のエッチン
グを行い、微細配線の２層構造のフィルムキャリア装置
を作成した。銅箔シート１と銅層１１が接続された構造
を図２に示す。比較のため、同じ構成のバイアホール
に、スパッタ法で厚さ４μｍの銅膜５を形成した（図５
参照）。(Example 1) An insulating layer (polyimide: 100 μm thick) in which a via hole having a diameter of 300 μm was formed.
A copper foil sheet 1 having a thickness of 25 μm was bonded to an Ube Industries product, trade name IUPIREX S) 3 with an epoxy adhesive 2. Next, a solder having a diameter of 300 μm (80% Sn-20%
(Pb alloy) wire was inserted and cut into 80 via holes, and then heated at about 210 ° C. The structure at this stage is shown as a sectional view in FIG. Next, the insulating layer 3 and the solder layer 10 of this structure
A copper layer 11 having a thickness of 4 μm is formed on the upper surface of the substrate by a vacuum evaporation method,
Thereafter, resist coating, patterning, and etching of the copper layer were performed to prepare a film carrier device having a two-layer structure of fine wiring. FIG. 2 shows a structure in which the copper foil sheet 1 and the copper layer 11 are connected. For comparison, a copper film 5 having a thickness of 4 μm was formed in a via hole having the same configuration by a sputtering method.
reference).
【００１６】両者の初期抵抗のばらつきを調べたとこ
ろ、実施例１では初期抵抗のばらつきは０．１〜０．２
Ω、比較例１のものは０．２〜１．０Ωであり、本発明
のものはばらつきも小さく安定していた。また、このフ
ィルムキャリア装置を−５０℃〜＋１５０℃の温度サイ
クル試験を実施しながら接続抵抗の推移を調べたとこ
ろ、比較例１のフィルムキャリア装置よりも導通不可
（バイアホールでの膜はがれによる断線）になる時間が
２０００時間と１０倍長く、熱ストレスに対する信頼性
が大幅に向上した。When the variation in the initial resistance was examined, the variation in the initial resistance was 0.1 to 0.2 in Example 1.
Ω, that of Comparative Example 1 was 0.2 to 1.0 Ω, and that of the present invention was stable with little variation. Further, when the transition of the connection resistance was examined while performing a temperature cycle test of −50 ° C. to + 150 ° C. on this film carrier device, conduction was not possible as compared with the film carrier device of Comparative Example 1 (disconnection due to film peeling at the via hole) ) Is 2000 hours, which is 10 times longer, and the reliability against thermal stress is greatly improved.
【００１７】（実施例２）厚さ２５μｍの銅箔シート１
にエポキシ系接着剤層２を介してポリイミド絶縁層（厚
さ７５μｍ、バイアホール径２００μｍで他面に銅箔キ
ャスティング材１２を有する）３を貼り合わせた。次い
で直径１８０μｍの半田（８０％Ｓｎ−２０％Ｐｂ合
金）線を８０個のバイアホールに挿入切断後、約２００
℃で加熱しバイアホールを充満させた。その上にイオン
プレーティングにより、厚さ５μｍの銅層１１を形成し
た（図３参照）。さらにレジスト塗布、パターンニング
を行い、銅層をエッチングし、２層微細配線構造のフィ
ルムキャリア装置を製作した。このフィルムキャリア装
置を−５０℃〜＋１５０℃の温度サイクル試験（３０分
保持）を実施しながら接続抵抗の推移を調べたところ、
従来のめっきによる銅箔シートとの接続をしたものと比
較して初期抵抗のばらつきも小さく導通不可（バイアホ
ールあるいはスルーホールでの銅の電気めっき膜のはが
れによる断線またはイオンプレーティングによる銅膜の
はがれによる）になる時間が２０００時間と５倍長く、
熱ストレスに対する信頼性が大幅に向上した。(Example 2) Copper foil sheet 1 having a thickness of 25 μm
A polyimide insulating layer (thickness: 75 μm, via hole diameter: 200 μm, having a copper foil casting material 12 on the other surface) 3 was bonded via an epoxy-based adhesive layer 2. Next, after inserting and cutting a solder (80% Sn-20% Pb alloy) wire having a diameter of 180 μm into 80 via holes, about 200 mm
C. to heat the via holes. A copper layer 11 having a thickness of 5 μm was formed thereon by ion plating (see FIG. 3). Further, resist coating and patterning were performed, and the copper layer was etched to produce a film carrier device having a two-layer fine wiring structure. When a change in connection resistance was examined while performing a temperature cycle test (holding for 30 minutes) of the film carrier device at −50 ° C. to + 150 ° C.,
Dispersion of the initial resistance is smaller than that of the connection with the copper foil sheet by the conventional plating, and the conduction is not possible. (Disconnection of the copper electroplating film in the via hole or through hole or disconnection of the copper film by ion plating. The time to become peeling) is 2000 hours, 5 times longer,
The reliability against thermal stress has been greatly improved.
【００１８】温度サイクル（熱ストレス）試験法：バイ
アホールを介して電気的に接続したフィルムキャリア装
置をＥＩＡＪ(Electronic Industries Association of
Japan:社団法人日本電子機械工業会）の規格に準拠し、
二葉科学製、冷熱サイクルの試験機を用い、−５０℃に
３０分間保った後、昇温速度１２０℃／分で１５０℃に
昇温し、３０分間保つ。次いで降温速度−３０℃／分で
−５０℃とする。このサイクルを繰り返し、導通が不可
になる時間を調べた。なお試験数４８個の平均値で求め
た。Temperature cycle (thermal stress) test method: A film carrier device electrically connected through a via hole is connected to an EIAJ (Electronic Industries Association of
Japan: Japan Electronics Association)
After maintaining the temperature at −50 ° C. for 30 minutes using a thermal cycle tester manufactured by Futaba Kagaku, the temperature is raised to 150 ° C. at a rate of 120 ° C./min and maintained for 30 minutes. Next, the temperature is lowered to -50 ° C at a temperature lowering rate of -30 ° C / min. This cycle was repeated to determine the time at which conduction was disabled. In addition, it calculated | required by the average value of 48 test numbers.
【００１９】[0019]
【発明の効果】本発明は以上説明したように構成されて
いるので、本発明の方法によって製造されるフィルムキ
ャリア装置は、半田ボール若しく半田線がバイアホール
に埋め込まれ、この半田の露出表面側から真空蒸着法ま
たはイオンプレーティング法を施すことにより、この半
田表面に形成された蒸着層と一体の第２導電層が形成さ
れ、それによってバイアホールを介して第１および第２
導電層の接続ができるため、熱ストレスに対する信頼性
が向上した。また、バイアホールが０．６ｍｍより小径
のもの程第１半田溶融層で確実にバイアホールを介して
の接続ができる。さらに本発明の方法によって製造され
るフィルムキャリア装置は効率の良い接続法によるもの
であり、工業的な量産性にも優れている。Since the present invention is configured as described above, the film carrier device manufactured by the method of the present invention has a solder ball or a solder wire embedded in a via hole, and the exposed surface of the solder is exposed. Vacuum evaporation from the side
Or by applying the ion plating method,
A second conductive layer integral with the vapor deposition layer formed on the rice field surface is formed.
Is it the first and second through via holes
Since the conductive layer can be connected, reliability against thermal stress has been improved. Further, as the diameter of the via hole is smaller than 0.6 mm, the connection through the via hole can be made more reliably in the first solder fusion layer. Further, the film carrier device manufactured by the method of the present invention is based on an efficient connection method and is excellent in industrial mass productivity.
【図１】本発明の実施例１の半田線を熔融した段階の構
造を示す断面図である。FIG. 1 is a cross-sectional view illustrating a structure at a stage where a solder wire according to a first embodiment of the present invention is melted.
【図２】本発明の実施例１の電気的接続を終えた段階の
構造を示す断面図である。FIG. 2 is a cross-sectional view illustrating a structure at a stage after the electrical connection according to the first embodiment of the present invention is completed.
【図３】本発明の実施例２の電気的接続を終えた段階の
構造を示す断面図である。FIG. 3 is a cross-sectional view illustrating a structure at a stage after an electrical connection according to a second embodiment of the present invention is completed.
【図４】本発明の装置の別の態様を示す断面図である。FIG. 4 is a sectional view showing another embodiment of the device of the present invention.
【図５】従来のスパッタ法により電気的に接続した構造
を示す断面図である。FIG. 5 is a cross-sectional view showing a structure electrically connected by a conventional sputtering method.
【図６】従来のめっき法により電気的に接続した構造を
示す断面図である。FIG. 6 is a cross-sectional view showing a structure electrically connected by a conventional plating method.
【図７】半田ボールの埋め込み工程（装置）の一例を示
す断面図である。FIG. 7 is a cross-sectional view illustrating an example of a step (apparatus) of embedding solder balls.
１ 銅箔シート（第１導電シート層） ２ 接着剤層 ３ 絶縁層 ４ バイアホール ５ 銅膜層 ６ 接着剤層 ７ 銅箔シート層 ８ スルーホール ９ めっき層 １０ 半田層 １１ 銅層（第２導電層） ２１ クランパー ２２ キャピラリーティップ ２３ 半田ワイヤー ２４ 埋め込み前の半田ボール ２５ 印加電極 ２６ 雰囲気ガス供給ライン DESCRIPTION OF SYMBOLS 1 Copper foil sheet (1st conductive sheet layer) 2 Adhesive layer 3 Insulating layer 4 Via hole 5 Copper film layer 6 Adhesive layer 7 Copper foil sheet layer 8 Through hole 9 Plating layer 10 Solder layer 11 Copper layer (2nd conductive layer) Layer) 21 Clamper 22 Capillary tip 23 Solder wire 24 Solder ball before embedding 25 Applied electrode 26 Atmospheric gas supply line
───────────────────────────────────────────────────── フロントページの続き (72)発明者 御 田 護 茨城県日立市助川町３丁目１番１号 日 立電線株式会社 電線工場内 (72)発明者 高 城 正 治 茨城県日立市助川町３丁目１番１号 日 立電線株式会社 電線工場内 (56)参考文献 特開 平３−11646（ＪＰ，Ａ) 特開 昭59−232491（ＪＰ，Ａ) 特開 昭62−36900（ＪＰ，Ａ) 特開 平５−21537（ＪＰ，Ａ) 特開 平２−180041（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 311──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor: Mamoru Mita 3-1-1, Sukekawa-cho, Hitachi-shi, Ibaraki Pref. Inside the cable plant at Hitachi Cable Co., Ltd. (72) Inventor: Masaharu Takagi, Sukegawa-cho, Hitachi-shi, Ibaraki JP-A-3-11646 (JP, A) JP-A-59-232491 (JP, A) JP-A-62-36900 (JP, A) A) JP-A-5-21537 (JP, A) JP-A-2-180041 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 311
Claims (1)
し、これらの導電層間がバイアホールを介して電気的に
接続されてなるフィルムキャリア装置の製造方法であっ
て、前記第１導電層が露呈した前記バイアホールに半田
ボールまたは半田線を挿入し加熱溶解して当該バイアホ
ールを半田により実質的に充填した後、前記により充填
した半田の露出表面側から真空蒸着法またはイオンプレ
ーティング法を施すことにより、この半田表面に形成さ
れた蒸着層と一体の前記第２導電層を形成することを特
徴とするフィルムキャリア装置の製造方法。 A first conductive layer on both sides of the insulating layer;
These conductive layers are electrically connected via holes.
A method for manufacturing a connected film carrier device.
And soldering the via hole where the first conductive layer is exposed.
Insert a ball or solder wire, melt by heating, and
After the metal is substantially filled with solder,
From the exposed surface side of the solder
By applying the soldering method, the solder
Forming the second conductive layer integral with the deposited layer.
A method for manufacturing a film carrier device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176601A JP2757594B2 (en) | 1991-07-17 | 1991-07-17 | Film carrier equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3176601A JP2757594B2 (en) | 1991-07-17 | 1991-07-17 | Film carrier equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0521538A JPH0521538A (en) | 1993-01-29 |
| JP2757594B2 true JP2757594B2 (en) | 1998-05-25 |
Family
ID=16016424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3176601A Expired - Lifetime JP2757594B2 (en) | 1991-07-17 | 1991-07-17 | Film carrier equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2757594B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6111306A (en) | 1993-12-06 | 2000-08-29 | Fujitsu Limited | Semiconductor device and method of producing the same and semiconductor device unit and method of producing the same |
| US5679978A (en) * | 1993-12-06 | 1997-10-21 | Fujitsu Limited | Semiconductor device having resin gate hole through substrate for resin encapsulation |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59232491A (en) * | 1983-06-15 | 1984-12-27 | 松下電工株式会社 | Method of producing multilayer printed circuit board |
| JPH0230199B2 (en) * | 1984-08-06 | 1990-07-04 | Ibiden Kk | FUKUGOPURINTOHAISENBANNOSEIZOHOHO |
| JP2823242B2 (en) * | 1989-06-08 | 1998-11-11 | 新光電気工業株式会社 | Film carrier |
-
1991
- 1991-07-17 JP JP3176601A patent/JP2757594B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521538A (en) | 1993-01-29 |
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