JP2752388B2 - Data demodulation circuit in RDS receiver - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a radio data system receiver (hereinafter referred to as RD).
S receiver).

2. Description of the Related Art At the time of program broadcasting of a general broadcasting station, broadcast time information such as information relating to the program content is received as data by multiplex modulation, and a desired program content is received on the receiving side based on the demodulated data. There is a radio data system (RDS) that allows the user to select a service and provide that service to radio listeners.

In this radio data system, 57 kHz, which is the third harmonic of the 19 KHz stereo pilot signal outside the frequency band of the FM modulation wave, is used as a subcarrier, and the subcarrier is filtered and biphase-coded. The radio data signal is amplitude-modulated by a data signal indicating information related to the broadcast such as the content, and the amplitude-modulated subcarrier is frequency-modulated to the main carrier for broadcasting.

As is clear from FIG. 4 showing the base bango coding structure of the radio data signal, 104 bits are 1 bit.
Multiplex transmission is performed repeatedly as a group. One group is composed of four blocks each having a 26-bit configuration, and each block is composed of a 16-bit information word and a 10-bit check word.

FIG. 5 shows an example of the configuration of an RDS receiver capable of receiving such RDS direction waves. In FIG. 1, an FM multiplex broadcast wave received by an antenna 1 is selected by a front end 2 and converted into an intermediate frequency (IF), and then supplied to an FM detector 4 via an IF amplifier 3. You. The detection output of FM detector 4 is
The signal is supplied to an MPX (multiplex) demodulation circuit 5, and in the case of a stereo broadcast, is separated into L (left) and R (right) channel audio signals to be reproduced audio output.

When the detection output of the FM detector 4 passes through the filter 6, a 57 KHz subcarrier amplitude-modulated by the biphase-coded data signal, that is, a radio data signal is extracted and demodulated by the PLL circuit 7. . This demodulated output is supplied to a digital (D) PLL circuit 8 and a decoder 9.
Supplied to In the D-PLL circuit 8, the PLL circuit 7 generates a clock for data demodulation based on the demodulated output. The generated clock is supplied to the decoder 9 and used as a clock for performing processing such as error correction on output data of the decoder 9. In the decoder 9,
The bi-phase coded data signal, which is the demodulated output of the PLL circuit 7, is decoded in synchronization with the clock generated by the D-PLL circuit 8.

The lock detection circuit 10 is for detecting a lock state and an unlock state of the D-PLL circuit 8, and includes, for example,
In the unlocked state, a high level unlock detection signal is output.
In the locked state, a low-level lock detection signal is output. As the lock detection circuit 10, for example,
The configuration described in JP-A-87836 can be used.
The detection output of the lock detection circuit 10 is supplied as a lock range switching signal for switching and controlling the lock ranges of the PLL circuit 7 and the D-PLL circuit 8. That is, the PLL circuit 7 and the DP
In the LL circuit 8, the cutoff frequency is variable by changing the constant or loop gain of the loop filter included in these circuits, and a high level unlock detection signal is supplied from the lock detection circuit 10. When the lock detection signal at a low level is supplied, the lock range is widened by increasing the cutoff frequency when the lockoff signal is supplied.

As described above, when the lock detection circuit 10 detects the lock state of the D-PLL circuit 8, the lock range of the PLL circuit 7 and the D-PLL circuit 8 is narrowed, so that the clock for data demodulation is affected by the outside. It can always be supplied as a stable clock without any problem.

As described above, in the conventional data demodulation circuit, in response to the detection output of the lock detection circuit 10, the PLL circuit 7 and the D
-The lock range of the PLL circuit 8 is switched. However, one group of the radio data signal repeatedly multiplex-transmitted in group units is composed of 104 bits (4th bit).
Therefore, if the lock range of the PLL circuit 7 and the D-PLL circuit 8 is immediately switched to a wider range when the lock state of the D-PLL circuit 8 is released, the jitter of the data demodulation clock increases. Therefore, processing such as error correction cannot be performed satisfactorily, and it takes time until accurate data is obtained.

SUMMARY OF THE INVENTION Accordingly, the present invention provides an RDS that can obtain accurate data continuously even when the PLL circuit is unlocked.
It is an object to provide a data demodulation circuit in a receiver.

A data demodulation circuit according to the present invention is an RDS receiver capable of receiving an RDS broadcast wave in which a radio data signal by a sub-carrier amplitude-modulated by a data signal is repeatedly multiplexed and transmitted in a group unit, and demodulates and modulates the radio data signal. PLL (phase and phase) for generating demodulation clock
A locked loop) circuit, and lock detecting means for detecting an unlocked state of the PLL circuit, wherein the lock state of the PLL circuit becomes wider than the locked state by detecting the unlocked state by the lock detecting means. A data demodulation circuit adapted to switch the lock range by detecting the unlocked state at a point in time when at least one group of the radio data signal has passed since the detection. It is characterized by having.

Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, the same parts as those in FIG. 5 are denoted by the same reference numerals, and the description thereof is omitted because they are duplicated. In the present embodiment, when the lock detection circuit 10 detects that the D-PLL circuit 8 is out of the locked state, the lock detection circuit 10 outputs a high-level unlock detection signal (a).
A signal (b) whose rise is delayed by a predetermined time T as shown in FIG. 2 is generated, and this signal (b) is controlled by the PLL circuit 7 and the D-PLL circuit 8 so as to widen their lock ranges. A delay circuit 11 for supplying a lock range switching signal is newly provided, and the rest is the same as the configuration in FIG. Delay time T of delay circuit 11
If the radio data signal is longer than the time corresponding to one group, that is, one group is 104 bits and the transmission rate of the radio data signal is 1187.5 bits / second, T ≧
Good results can be obtained by setting the time to 104 × (1 / 1187.5), preferably about 5 blocks in units of 4 blocks constituting one group, that is, T ≒ 130 × (1 / 1187.5). This has been confirmed by the applicant's experiments.

An example of a specific circuit configuration of the delay time 11 is shown in FIG. 3, and the delay circuit 11 uses the data demodulation clock from the D-PLL circuit 8 as a clock input and a lock detection circuit.
A counter 31 of 130 base (corresponding to 5 blocks) which is cleared at the rising edge of the unlock detection signal (FIG. 2 (a)) from 10 and an unlock detection signal (set by the count output of the counter 31) a) The flip-flop 32 is set at the falling edge of (a).
A lock range switching signal (b) delayed by a time T given by × (1 / 1187.5) is output. The delay time 11 is not limited to the circuit configuration shown in FIG. 3, but generates a lock range switching signal (b) whose rise is delayed by a time T with respect to the unlock detection signal (a). What is necessary is just a thing of the composition which can be performed.

As described above, when the unlocked state of the D-PLL circuit 8 is detected, the lock range of the PLL circuit 7 and the D-PLL circuit 8 is changed after a lapse of at least one group-corresponding time T of the radio data signal from the detection point. Is switched to a wider direction, so that one group of radio data signals is divided into four blocks, and the clock is stable even when several tens of bits of data are lost. The data of the block can be obtained as accurate data by performing processing such as error correction.

As described above, in the data demodulation circuit according to the present invention, switching of the lock range by detecting the unlock state of the PLL circuit that performs demodulation of the radio data signal and generation of the data demodulation clock is performed from the time of the detection. Since the operation is performed when the time corresponding to at least one group of the radio data signal has elapsed, a stable clock is continuously generated even when the lock state of the PLL circuit is released, and the data indicating the contents of the radio program, etc. Can be accurately demodulated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram of input / output signals of the delay circuit in FIG. 1, and FIG. 3 is a specific circuit configuration of the delay circuit in FIG. FIG. 4 is a block diagram showing an example of a radio data signal, and FIG. 5 is a block diagram showing a conventional example. Description of Signs of Main Part 2 Front End 4 FM Detector 5 Multiplex Demodulation Circuit 7 First PLL Circuit 8 Second PLL Circuit 10 Lock Detection Circuit 11 Delay circuit

Claims (2)

(57) [Claims] An RDS receiver capable of receiving an RDS broadcast wave in which a radio data signal of a subcarrier amplitude-modulated by a data signal is repeatedly multiplex-transmitted in group units,
A phase locked loop (PLL) circuit that demodulates the radio data signal and generates a data demodulation clock; and a lock detection unit that detects an unlock state of the PLL circuit. A data demodulation circuit adapted to switch a lock range of the PLL circuit to a direction wider than the lock state by detecting a lock state, wherein the switching of the lock range by the detection of the unlock state is performed by the radio from the time of detection. A data demodulation circuit comprising means for controlling the data signal to be executed when at least one group of data signals has elapsed. A first PLL circuit for demodulating the radio data signal; and a second PLL circuit for generating a data demodulation clock based on a demodulated output of the first PLL circuit.
An L circuit, wherein the lock detecting means includes the second PLL.
2. The data demodulation circuit according to claim 1, wherein an unlocked state of the circuit is detected.