JP2751673B2 - Bit error rate measurement equipment for digital communication systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit error rate measuring apparatus for a digital communication system, and more particularly to an apparatus for measuring a bit error rate by comparing a bit error rate with a pseudo random pattern.

[0002]

2. Description of the Related Art With the advent of the advanced information society in recent years, digitization has been promoted in the communication field. And
The quality of the data signal is evaluated by comparing transmitted information and received information (both digital signals) to determine whether data has been transmitted correctly. Among such quality evaluation methods, the bit error rate particularly indicates the ratio of the number of erroneously received bits to the number of transmission bits, and is an extremely effective evaluation method when discussing the quality of a transmission system globally. is there. That is, if n bits of the transmitted N-bit information are incorrect up to the receiving terminal, the bit error rate is n / N
Becomes Various methods for detecting such a bit error rate have been conventionally proposed, and FIG. 2 shows an example of such a bit error rate measuring device.

In FIG. 2, a pattern generator 1 of a transmitting section
The digital signal transmitted from 0 is transmitted to the receiving unit via the transmission system 12 of the measured system. The receiving unit is provided with a comparison pattern generator 14 having the same configuration as the transmitting unit.
15-stage shift registers SR1 to SR1 connected to W14a
SR15 is provided. The output terminal of the last-stage shift register SR15 and the immediately preceding shift register SR1
4 are both connected to the EX-OR gate 14b,
The configuration is output to the B contact in the figure. The input data from the B terminal of the comparison pattern generator 14 of the reception unit and the pattern generator 10 of the transmission unit are compared with the EX-OR gate 1 for comparison.
6 and an output thereof is connected to an error counting circuit 18.

[0004] The pseudo random pattern transmitted from the pattern generator 10 of the transmitting unit and the pseudo random pattern from the comparison pattern generator 14 are compared with the EX-EX for comparison.
The signals are compared by the OR gate 16 and counted by the error counting circuit 18. At this time, if there is no error for 30 consecutive bits, it is determined that the transmitting side and the receiving side have been synchronized.
The synchronization circuit 20 sends a control signal to the switching SW 14a to switch from the A contact to the B contact. Then, a pseudo random pattern is repeatedly output from the comparison pattern generation circuit 14 to one input terminal of the comparison EX-OR gate 16, and a pseudo random pattern is input from the pattern generator 10 of the transmission unit to the other input terminal. Will be compared. Also, after synchronization is achieved in this manner, the clock 1024
If an error of 1024 bits occurs in 0 bits, it is determined that the synchronization between the transmission unit and the reception unit has been lost again due to some influence (for example, mixing of noise), and the synchronization circuit 20 switches the control signal. The signal is sent to the SW 14a to switch from the B contact side to the A contact side again to resynchronize.

After the synchronization is established in this way, the input data from the transmission unit and the pseudo random pattern from the comparison pattern generator 14 are compared by the comparison EX-OR gate 16, and the number of mismatched bits is determined. The bit error rate is calculated by counting simultaneously with the clock by the error counting circuit 18. The bit error rate is calculated by the display circuit 2
4, the transmission quality of the transmission system 12 of the measured system is evaluated.

[0006]

As described above, in the conventional bit error rate measuring device for a digital telecommunications system, the input data and the data from the comparison pattern generator are compared after synchronization is obtained. When the synchronization is lost, it is necessary to start again with the acquisition of the pattern for comparison, so that the bit error rate cannot be measured during the acquisition of the pattern for comparison, so that the measurement takes time.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and has as its object to measure bit error rate for a digital communication system capable of immediately detecting synchronization and starting measurement even when synchronization is lost. It is to provide a device.

[0008]

In order to achieve the above object, the present invention comprises a comparison pattern generator for reading digital data sent from a transmission unit, and detects a synchronization with the transmission unit. In a bit error rate measuring device for a digital communication system for calculating a bit error rate by comparing digital data read into a comparison pattern generator with digital data from the transmitting unit, the digital data is connected in parallel with the transmitting unit. First and second comparison pattern generators, system switching means for switching the outputs of the first and second comparison pattern generators, and digital data from the transmission unit for the first or second comparison. Logic gate means for determining whether the digital data from the pattern generator matches, and data determined to be mismatched by the logic gate means The a counting means for counting, and synchronization detection means for controlling the switching by detecting the line switching means the presence or absence of synchronization based on the result of counting in the counting means,
When the out-of-synchronization is detected based on the counting result, the synchronization is detected using the digital data read into the remaining comparison pattern generators.

[0009]

As described above, in the bit error rate measuring device for a digital communication system according to the present invention, two comparison pattern generators are used. If the synchronization is lost during the measurement of the error, the synchronization detecting means switches the system switching means and uses the output of the remaining comparison pattern generator to eliminate unnecessary reading time.

That is, for example, when the digital data (pseudo-random pattern) read into the first comparison pattern generator is compared with the digital data from the transmission section to measure a data error, the counting means counts the data error. When the number of errors to be performed is large and the synchronization is lost, the synchronization detecting means controls the system switching means to switch the output from the first comparison pattern generator to the second pattern generator.

Since the second comparison pattern generator is connected to the transmission section in parallel with the first comparison pattern generator, the second comparison pattern generator always reads digital data from the transmission section. The synchronization can be immediately detected using the digital data read into the second comparison pattern generator without reading digital data from the section.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a bit error rate measuring device for a digital communication system according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the apparatus according to this embodiment. The comparison pattern generator in the present embodiment includes a first comparison pattern generator 30 and a second comparison pattern generator 32, and these first and second comparison pattern generators 30, 32 are provided. Have the same configuration as the comparison pattern generator 14 shown in FIG. That is, the first comparison pattern generator 3
0 is a first switching SW 30a having A and B contacts,
15-stage shift register S connected to switch SW30a
R1 to SR15, and EX-OR gates 30b to which outputs of SR14 and SR15 are input, and the second comparison pattern generator 32 is a switching second switch having C and D contacts.
SW32a, 15 connected to the second switch SW32a
The stage shift registers SR1 to SR15 are composed of EX-OR gates 32b to which outputs of SR14 and SR15 are input.

The first comparison pattern generator 30
A contact and the C contact of the second comparison pattern generator 32 are both connected to the transmission system 12 of the measured system.
When there is no input data, the first switching SW 30a and the second switching 32a are connected to the A contact side and the C contact side, respectively. Therefore, when data (pseudo random pattern) and a clock are inputted, the data is in the first state. Comparison pattern generator 3
0 and the second comparison pattern generator 32. And the read data is E
The signals are output to the E terminal and the F terminal as a pseudo random pattern via the X-OR gates 30b and 32b.

Here, the E terminal and the F terminal are system switching SWs.
34, and a pseudo-random pattern from the first comparison pattern generator 30 normally connected to the E-contact side by a control signal from the synchronization circuit 20 and the input data are used for comparison EX. -Comparison is made by the OR gate 16 Then, the comparison result is output to the error counting circuit 18, and the mismatch data is counted and sent to the synchronization circuit 20. The synchronization circuit 20 determines whether the number of coincident data has been counted continuously for 30 bits. If there is no error for 30 consecutive bits, the synchronization circuit 20 determines that synchronization between the transmitting side and the receiving side has been established, and performs the first switching. SW 30a is switched from the A contact side to the B contact side. Then, a pseudo-random pattern is repeatedly output (15 dot cycle) from the first comparison pattern generator 30 and compared with the input data.

During this time, the second switching SW 32a is fixed to the contact C side, so that the latest pseudo random pattern sent from the pattern generator 10 on the transmitting side is read into the second comparison pattern generator 32. But
Since the system switching SW 34 is connected to the E contact side, it is not used for error measurement.

In this manner, the first switch 30a is set to B
When switching to the contact side, the input data and the pseudo-random pattern from the first comparison pattern generator 30 are used for comparison E.
When the two data are input to the X-OR gate 16 and are different, a Hi signal is output to the error coefficient circuit 18 and the number of errors is counted. When an error of 1024 bits occurs in the clock 10240 bits, it is determined that the synchronization between the transmission unit and the reception unit has been lost, and the synchronization circuit 20 switches the first switching SW 30a to the A contact side and switches the system switching switch 34 Switch to F side. The second switch SW32
a is maintained at the C contact side. As described above, when the synchronization is lost, by switching the system switching SW 34 to the F contact side, the latest pseudo random pattern read into the second comparison pattern generator 32 is compared with the comparison EX-O.
The signal is output to the R gate 16, and the synchronization can be detected immediately. If there is no error for 30 consecutive bits, it is determined that synchronization between the transmitting side and the receiving side has been regained, and the second switch 32a is connected to the D side to continue the bit error rate measurement.

If it is determined that the synchronization has been lost again during the measurement, the system switching SW 34 is set to the E contact side to use the latest pseudo random pattern read into the first comparison pattern generator 30. Again to perform synchronization detection.

As described above, when the synchronization is lost, the data of either the first comparison pattern generator 30 or the second comparison pattern generator 32 is used alternately, so that even if the synchronization is lost, The synchronization detection can be immediately performed, and the bit error rate calculated by the error counting circuit 18 can be quickly displayed on the display circuit 22.

In this embodiment, the clock 102
It is determined that the transmission unit and the reception unit are out of synchronization when an error of 1024 bits out of 40 bits occurs, and that synchronization is established when there is no error for 30 consecutive bits. Can be appropriately set to a desired value according to the measurement conditions.

[0021]

As described above, according to the bit error rate measuring apparatus for a digital communication system according to the present invention, it is possible to eliminate the time required to read a pseudo random pattern for re-establishing synchronization when synchronization is lost. As a result, the unmeasurable time of the bit error rate can be removed, and the bit error rate can be quickly and accurately measured.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

FIG. 2 is a configuration block diagram of a conventional device.

[Explanation of symbols]

 Reference Signs List 16 EX-OR gate for comparison 18 Error coefficient circuit 20 Synchronous circuit 22 Display circuit 30 First pattern generator for comparison 32 Second pattern generator for comparison 34 System switching SW

Claims (1)

(57) [Claims] 1. A comparison pattern generator for reading digital data sent from a transmission unit, wherein after detecting synchronization with the transmission unit, the digital data read by the comparison pattern generator and the transmission unit A bit error rate measuring device for a digital communication system, which calculates a bit error rate by comparing digital data from a first and second pattern generators connected in parallel with the transmitting unit; System switching means for switching the outputs of the first and second comparison pattern generators; and determining whether the digital data from the transmission unit matches the digital data from the first or second comparison pattern generator. Logic gate means for counting, data counting means for counting the number of data determined to be inconsistent by the logic gate means, and counting by the counting means. Synchronization detection means for detecting the presence / absence of synchronization based on and switching control of the system switching means, and when the out-of-synchronization is detected by the counting result, the digital data read into the remaining comparison pattern generators A bit error rate measuring device for a digital communication system, wherein the bit error rate measuring device detects synchronization using the same.