JP2745993B2 - Signal transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission system, and in particular, a frequency synchronization is established between a transmitting clock signal for transmitting a data signal and a receiving clock signal for receiving the data signal. The present invention relates to an improved signal transmission method free from the influence of jitter or fluctuation (wonder) when the phase is not determined.

[0002]

2. Description of the Related Art Conventionally, in data transmission, a data transmitting side and a data receiving side operate with independent clocks,
In some cases, data transmission is performed under the condition that the clocks of the transmission and the reception are frequency-synchronized but the phase is uncertain. Under such conditions, the receiving side extracts the data on the transmitting side in accordance with the timing of the receiving clock and receives the data from the transmitting side in order to have a retiming phase margin in order to transfer the data as data synchronized with the receiving clock. It is necessary to divide the transmission clock by L. That is, L
It is necessary to double the data signal length by serially / parallel-converting the received data into two columns on the basis of at least the frequency-divided clock of 2.

Conventionally, a "clock signal transfer circuit" on the receiving side of this type of signal transmission system is shown in a block diagram of FIG. 3, and a timing chart of signals of respective parts is shown in FIG. FIG. 4 shows an example in which the phases of the transmitting clock C1 and the receiving clock C4 are different by 180 °. In the conventional example shown in FIG. 3, the transmission side clock C1 is phase-synchronized with the frame pulse FP1 of the data D1 to perform phase normal rotation and phase inversion.
And a frequency dividing circuit 5A for outputting clocks C2 and C3 divided by 2, and data D based on the divided clocks C2 and C3.
Two flip-flops 1, 11 for extracting 1 as two columns of data D2, D3, that is, a serial-parallel conversion circuit;
Flip-flop 2 for inverting data D2 by 180 °
And two columns of data D4 and D6 based on the clocks C5 and C6 which are synchronized with one of the receiving clock C4 and the receiving frame pulse, inverted in phase with each other, and frequency-divided by 2 by the frequency dividing circuit 7.
Flip-flops 12 and 13 for extracting the data D5 and D6 respectively from the data D3, a selection circuit 3A for alternately extracting the data D5 and D6 for parallel-to-serial conversion to obtain serial data D7, and finally a reception clock C4. And a flip-flop 4 that outputs data D8 that is phase-synchronized with the flip-flop 4.

[0004]

However, in the conventional signal transmission method, the data signal sequence becomes L times by performing the serial-parallel conversion, and the number of flip-flops required for retiming is greatly increased. There was a disadvantage of becoming. Further, in the prior art, when the clock phase difference including the frame pulse as a reference between transmission and reception is within L / 2 bits with respect to the division ratio L, the circuit operates normally. , There is a possibility that erroneous retiming may occur.

An object of the present invention is to provide a signal transmission system having a small circuit scale and configured with a minimum number of flip-flops without converting a data signal from serial to parallel.

[0006]

According to the signal transmission method of the present invention, frequency synchronization is established between a transmission side clock signal for transmitting a data signal and a reception side clock signal for receiving a data signal from the transmission side. However, in a signal transmission method in which the respective phases are not determined in advance, the transmission side clock signal and the transmission side non-inverted clock signal having the same phase as the transmission side clock signal are shifted by 180 degrees using the transmission side clock signal. Means for generating a phase-inverted transmission-side inverted clock signal; and a reception-side clock signal having the same phase as the reception-side clock signal using the reception-side clock signal and an N-multiple clock signal (N is a natural number of 3 or more) of the reception-side clock signal. The non-inverted clock signal also generates a window pulse of M clock width (M is a natural number closest to N / 4) based on the N-times clock signal and generates a window pulse. Means for generating a window signal such that the center of the pulse is in phase with the rising edge of the non-inverting clock signal on the receiving side, and a first flip-flop for retiming the data signal input from the transmitting side with the inverting clock signal on the transmitting side Flip-flop, a second flip-flop for retiming the output data signal of the first flip-flop with the non-inverting clock signal on the transmission side, and selecting the output data signals of the first and second flip-flops by an external selection signal Means for comparing the window signal with the transmission-side non-inverted clock signal and the transmission-side inverted clock signal, and outputting the output of the first flip-flop when the phase of the rising edge of the transmission-side non-inverted clock signal is within the window pulse The external selection signal is generated to select a data signal, and the phase of the rising edge of the inverted clock signal on the transmission side is generated. Means for generating the external selection signal so as to select the output data signal of the second flip-flop when present within the window pulse, and retiming the selected data signal with the receiving side non-inverting clock signal and outputting the selected data signal Means.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of one embodiment of the present invention. FIG.
When the transmission data signal D1 and the transmission side clock signal C1 sent from the transmission side via the transmission path are input, the reception side clock signal C4 provided on the reception side and the reception side 8 described below are used. 2 shows a "clock signal transfer circuit" that receives the double clock signal C5 and outputs the received data signal D5 changed in synchronization with the reception side clock signal.

Next, the configuration and operation of the embodiment shown in FIG. 1 will be described. The phase inverting circuit 5 receives the transmission-side clock signal C1 and inverts the transmission-side clock signal C1 by 180 degrees with respect to the transmission-side inverted clock signal C2 and the transmission-side clock signal C1.
To output a transmission-side normal clock signal C3 having the same phase.
The window signal generating circuit 6 receives the receiving-side clock signal C4 and the receiving-side octupled clock signal C5, which is the octupled clock signal of the receiving-side clock signal C4, and receives the receiving-side normal clock having the same phase as the receiving-side clock signal C4. A signal C6 and a window signal S1 having a window pulse corresponding to two clock widths of the receiving-side 8-multiplied clock signal C5 centering on the rising phase of the receiving-side clock signal C4 are output. The first-stage flip-flop 1 receives the transmission data signal D1 and the transmission-side inverted clock signal C2 from the phase inversion circuit 5, and re-times the transmission data signal D1 with the transmission-side inverted clock signal C2 to generate a 0.5-bit signal. It outputs the delayed data signal D2. 2
The stage flip-flop 2 is the first stage flip-flop 1
, And the transmission-side non-inverted clock signal C3 from the phase inversion circuit 5 are input.
The 5-bit delayed data signal D2 is retimed by the transmission side non-inverted clock signal C3 and output as a 1-bit delayed data signal D3. The selection circuit 3 receives the 0.5-bit delayed data signal D2 and the 1-bit delayed data signal D3,
Switching is performed by a selection signal S2 from the phase comparison circuit 7 described below, and a selection data signal D4 is output. The phase comparison circuit 7 outputs the transmission-side inverted clock signal C from the phase inversion circuit 5.
2, the transmission-side non-inverted clock signal C3 and the window signal S1 from the window signal generation circuit 6, and compares the transmission-side inverted clock signal C2 with the window signal S1, the transmission-side non-inverted clock signal C3, and the window signal S1, respectively. And the transmitting side inverted clock signal C
When the phase of the rising edge of 2 is within the window pulse of the window signal S1, the selection signal S2 is output so as to select the 1-bit delayed data signal D3 output from the second-stage flip-flop 2. Also, the transmission side non-inverted clock signal C3
Is present in the window pulse of the window signal S1, the selection signal S2 is output so as to select the 0.5-bit delayed data signal D2 output from the first-stage flip-flop 1. However, when neither the rising edge phase of the transmission side inverted clock signal C2 nor the phase of the rising edge of the transmission side normal clock signal C3 exists in the window pulse of the window signal S1, the selection signal S2 is not changed. The third-stage flip-flop 4 receives the selection data signal D4 selected by the selection circuit 3 and the reception-side non-inversion clock signal C6 from the window signal generation circuit 6, and converts the selection data signal D4 to the reception-side non-inversion clock signal C6. It is retimed and output as a received data signal D6.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. 2 and FIG. Here, it is assumed that the conversion point of the transmission data signal D1 is input with the same phase as the rising edge of the transmission side clock signal C1. The 0.5-bit delayed data signal D2 and the 1-bit delayed data signal D3 are retimed by the transmitting clock signal C2 and the transmitting non-inverting clock signal C3. If 0.5
Assuming that the bit-delayed data signal D2 is retimed by the receiving-side non-inverted clock signal C6 having the same phase as the receiving-side clock signal C4, even if a slight amount of jitter or wander occurs in the receiving-side clock signal C4, an error occurs at the time of retiming. May occur. Here, the window signal S1 absorbs this jitter or wander within this pulse width. That is, the receiving side clock signal C4 and the receiving side 8
When the window signal S1 generated from the multiplied clock signal C5 is compared with the transmission-side inverted clock signal C2 and the transmission-side non-inverted clock signal C3, the rising edge of the transmission-side inverted clock signal C2 exists in the window pulse of the window signal S1. In this case, the selection signal S2 is set to a low level. However, when the selection signal S2 is at the low level, the 1-bit delay data signal D3 is selected, and when the selection signal S2 is at the high level, the 0.5-bit delay data signal D2 is selected. The 1-bit delay data D3 selected in this manner is retimed by the reception-side non-inversion clock signal C6 having the same phase as the reception-side clock signal C4, and is output as the reception data signal D5. Even if some jitter or wander occurs, no error occurs at the time of retiming.

[0010]

As described above, according to the present invention, by providing a window signal generating circuit, a phase comparing circuit, and a selecting circuit, a transmitting clock signal for transmitting a data signal and a receiving clock signal for receiving the data signal are provided. Even if frequency synchronization is established for the receiving side clock signal but the respective phases are not determined in advance, the circuit does not perform serial-to-parallel conversion of the data signal using a large amount of flip-flops as in the conventional example. There is an effect that a small-scale signal transmission system can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of the present embodiment.

FIG. 3 is a block diagram of a conventional signal transmission system.

FIG. 4 is a timing chart illustrating the operation of the conventional example.

[Explanation of symbols]

 1, 2, 4 flip-flop 3 selection circuit 5 phase inversion circuit 6 window signal generation circuit 7 phase comparison circuit

Claims (1)

(57) [Claims] 1. A transmitting side clock signal for transmitting a data signal and a receiving side clock signal for receiving a data signal from the transmitting side have frequency synchronization established, but their phases are determined in advance. In the case of no signal transmission method, a transmission-side normal clock signal having the same phase as the transmission-side clock signal and a transmission-side inverted clock signal obtained by inverting the transmission-side clock signal by 180 degrees are generated using the transmission-side clock signal. Means, a receiving-side clock signal, and a receiving-side normal clock signal having the same phase as the receiving-side clock signal using the receiving-side clock signal and an N-times multiplied clock signal (N is a natural number of 3 or more). A window pulse having an M clock width (M is a natural number closest to N / 4) is generated based on the clock signal, and the center of the window pulse is set to the reception side non-inverted clock signal. Means for generating a window signal having the same phase as the rising edge of the signal, a first flip-flop for retiming the data signal input from the transmission with the inverted clock signal on the transmission side, and a first flip-flop. A second flip-flop for retiming the output data signal with the non-inverting clock signal on the transmission side, means for selecting output data signals of the first and second flip-flops by an external selection signal described later, Comparing the side normal clock signal and the transmission side inverted clock signal and selecting the output data signal of the first flip-flop when the phase of the rising edge of the transmission side normal clock signal is within the window pulse. An external selection signal is generated, and a second signal is generated when the phase of the rising edge of the inverted clock signal on the transmission side is within the window pulse. A signal comprising: means for generating the external selection signal so as to select an output data signal of a flip-flop; and means for retiming and outputting the selected data signal by a receiving-side non-inversion clock signal. Transmission method.