JP2626033B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2626033B2 JP2626033B2 JP6001589A JP6001589A JP2626033B2 JP 2626033 B2 JP2626033 B2 JP 2626033B2 JP 6001589 A JP6001589 A JP 6001589A JP 6001589 A JP6001589 A JP 6001589A JP 2626033 B2 JP2626033 B2 JP 2626033B2
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- tape
- conductive adhesive
- layer
- dicing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83193—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Die Bonding (AREA)
- Dicing (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体ウエハを個々の半導体チップ（ダイ）に分割す
るダイシング及び半導体チップをステージにろう付けす
るダイボンディング方法に関し， 背面に金属層のない半導体チップのダイボンディング
を可能にして，半導体装置製造の簡易化とコスト低減を
目的とし， 導電性接着剤，金属層,UVテープが順に積層された３
層フィルムの導電性接着剤面に半導体ウエハを貼り付け
る工程と，該３層フィルムを加熱して該導電性接着剤を
キュアする工程と，該UVテープを厚さ方向に全部切断し
ないで該ウエハ及び該金属層をダイシングし，背面に金
属層を被着した個々のチップに分割する工程と，該チッ
プをステージ上にボンディングする工程とを有するよう
に構成する。The present invention relates to a dicing method for dividing a semiconductor wafer into individual semiconductor chips (dies) and a die bonding method for brazing a semiconductor chip to a stage. In order to simplify and reduce the cost of semiconductor device manufacturing, conductive adhesive, metal layers, and UV tape were sequentially laminated.
A step of attaching a semiconductor wafer to the conductive adhesive surface of the layer film, a step of heating the three-layer film to cure the conductive adhesive, and a step of cutting the UV tape without cutting the entire UV tape in the thickness direction. And a step of dicing the metal layer to divide the chip into individual chips having a metal layer adhered to the back surface, and a step of bonding the chip to a stage.
本発明は半導体装置の製造方法に係り，特に半導体ウ
エハを個々の半導体チップ（ダイ）に分割するダイシン
グ及び半導体チップをステージにろう付けするダイボン
ディング方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a dicing method for dividing a semiconductor wafer into individual semiconductor chips (dies) and a die bonding method for brazing a semiconductor chip to a stage.
ダイシング及びダイボンディング工程は半導体装置の
組み立て工程の出発点であり，その合理化が望まれてい
る。The dicing and die bonding processes are starting points for the process of assembling the semiconductor device, and their rationalization is desired.
第４図は従来例によるタイシング及びダイボンディン
グ工程の流れ図である。FIG. 4 is a flow chart of a tiling and die bonding process according to a conventional example.
従来法は，まず背面に半田に対して濡れ性の良い金属
層を形成した半導体ウエハをUVテープ（紫外線照射によ
り接着力を失う性質を持つ接着剤を塗布した樹脂フィル
ム）に貼り付け，ダイシングソーによりダイシングし，
次に紫外線をUVテープに照射して，チップをダイコレッ
トでつかんでテープより剥離している。In the conventional method, first, a semiconductor wafer with a metal layer with good wettability to the solder formed on the back surface is attached to a UV tape (resin film coated with an adhesive that has the property of losing adhesive strength when irradiated with ultraviolet light), and a dicing saw is used. Dicing by
Next, UV light is applied to the UV tape, the chip is gripped by the die collet, and the chip is separated from the tape.
この後，半導体チップは,Agペーストを塗布したステ
ージ（表面に濡れ性の良い金属メッキ層を被着してい
る）上にダイボンディングされる。Thereafter, the semiconductor chip is die-bonded on a stage coated with an Ag paste (a metal plating layer having good wettability is applied to the surface).
第５図は従来のダイボンディング状態を説明する断面
図である。FIG. 5 is a sectional view for explaining a conventional die bonding state.
図において,1は半導体チップ,2はチップを搭載するス
テージ,3はチップ背面の金属層,4は半田,5はステージの
メッキ層である。In the figure, 1 is a semiconductor chip, 2 is a stage for mounting the chip, 3 is a metal layer on the back surface of the chip, 4 is solder, and 5 is a plating layer of the stage.
このように従来は，半導体チップを半田によってステ
ージに付けるために，蒸着又はスパッタ法により，半田
に対して濡れ性の良い金属層をチップ裏面に形成してい
る。As described above, conventionally, in order to attach a semiconductor chip to a stage by soldering, a metal layer having good wettability with respect to solder is formed on the back surface of the chip by vapor deposition or sputtering.
この金属層の形成には蒸着又はスパッタ等の工数と材
料費がかかり，コストの増加を招くので，簡便でコスト
の安い方法が望まれる。Since the formation of the metal layer requires man-hours and material costs such as vapor deposition or sputtering, and increases the cost, a simple and low-cost method is desired.
本発明は背面に金属層のない半導体チップのダイボン
ディングを可能にして，半導体装置製造の簡易化とコス
ト低減を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to enable die bonding of a semiconductor chip having no metal layer on the back surface, thereby simplifying semiconductor device manufacturing and reducing costs.
上記課題の解決は，導電性接着剤，金属層,UVテープ
が順に積層された３層フィルムの導電性接着剤面に半導
体ウエハを貼り付ける工程と，該３層フィルムを加熱し
て該導電性接着剤をキュアする工程と，該UVテープを厚
さ方向に全部切断しないで該ウエハ及び該金属層をダイ
シングし，背面に金属層を被着した個々のチップに分割
する工程と，該チップをステージ上にボンディングする
工程とを有する半導体装置の製造方法により達成され
る。In order to solve the above problems, a semiconductor wafer is attached to a conductive adhesive surface of a three-layer film in which a conductive adhesive, a metal layer, and a UV tape are sequentially laminated, and the conductive film is heated by heating the three-layer film. Curing the adhesive, dicing the wafer and the metal layer without cutting the UV tape in the thickness direction, and dividing the wafer and the metal layer into individual chips having a metal layer applied to the back surface; And a step of bonding on a stage.
第１図は本発明に使用する貼り付け用３層フィルムの
断面図である。FIG. 1 is a sectional view of a three-layer film for pasting used in the present invention.
本発明は，導電性接着剤6,金属層7,UVテープ８からな
る３層フィルムに背面に金属層のない半導体ウエハを貼
り付けて，導電性接着剤をキュアした後ダイシングする
ことにより，チップ背面に半田接合が可能な金属層を形
成することができ，この後従来とほぼ同じ工程でダイボ
ンディングができるようにしたものである。The present invention provides a three-layer film comprising a conductive adhesive 6, a metal layer 7, and a UV tape 8, a semiconductor wafer having no metal layer on the back surface, a curing of the conductive adhesive, and a dicing. A metal layer capable of being solder-bonded can be formed on the back surface, and thereafter, die bonding can be performed in substantially the same process as in the related art.
第２図は本発明によるダイシング及びダイボンディン
グ工程の流れ図である。FIG. 2 is a flowchart of a dicing and die bonding process according to the present invention.
従来例と相違する点は，ウエハに背面金属層のないも
のを使用したことと，貼り付けフィルムに３層フィルム
を用いたたことと,3層フィルムの導電性接着剤をキュア
する加熱工程を有することで，その他は従来工程と全く
同じである。The differences from the conventional example are that the wafer has no back metal layer, that a three-layer film is used for the attachment film, and that the heating process for curing the conductive adhesive of the three-layer film is different. Others are exactly the same as the conventional process.
ここで貼り付け用３層フィルムは次のものを用いる。 Here, the following three-layer film for sticking is used.
UVテープ８は厚さ70μｍの透明な樹脂フィルム上に紫
外線照射により接着力を失う性質を持つ接着剤を塗布し
た市販のものを用い，この上に厚さ25〜50μｍの金属層
７を貼り付け，その上に導電性接着剤６を厚さ25〜50μ
ｍ塗布する。The UV tape 8 is a commercially available UV tape 8 coated with an adhesive having a property of losing adhesive strength by irradiation with ultraviolet light on a 70 μm thick transparent resin film, and the metal layer 7 having a thickness of 25 to 50 μm is adhered thereon. , A conductive adhesive 6 having a thickness of 25 to 50 μm
m.
ここで，金属層７はAu（又はAg,Cu,Ni,Pd等）層を用
いる。Here, the metal layer 7 uses an Au (or Ag, Cu, Ni, Pd, etc.) layer.
導電性接着剤６として接着剤に導電性のフィラを含ん
だAgペーストを厚さ25〜50μｍ塗布する。接着剤はエポ
キシ系以外のもので良く，フィラ材料としてAu,Cu,Ni等
を用い，フィラの形状は無定形，球，繊維状のいずれで
もよい。An Ag paste containing a conductive filler is applied to the adhesive as the conductive adhesive 6 to a thickness of 25 to 50 μm. The adhesive may be other than epoxy, and Au, Cu, Ni, or the like may be used as the filler material, and the filler may be amorphous, spherical, or fibrous.
次に，第２図の流れ図に従って実施例の工程を説明す
る。Next, the steps of the embodiment will be described with reference to the flowchart of FIG.
第３図（ａ）〜（ｆ）は実施例の各工程を説明する断
面図である。3 (a) to 3 (f) are cross-sectional views illustrating each step of the embodiment.
第３図（ａ）において，背面に金属層を形成していな
い半導体ウエハ11を，貼り付け用３層フィルムの導電性
接着剤６上に貼り付ける（第２図の工程）。In FIG. 3 (a), a semiconductor wafer 11 having no metal layer formed on the back surface is adhered on the conductive adhesive 6 of the adhesive three-layer film (step in FIG. 2).
第３図（ｂ）において，ダイシングソー12を用いて，
ダイシングを行う。この際，最下層のUVテープ８の一部
に食い込むまで切断する（第２図の工程）。In FIG. 3 (b), using a dicing saw 12,
Perform dicing. At this time, cutting is performed until a part of the lowermost UV tape 8 is cut (step in FIG. 2).
ウエハ11は個々のチップ１に分割される。 The wafer 11 is divided into individual chips 1.
第３図（ｃ）において，所定の温度，例えば150℃で
導電性接着剤６をキュアし（第２図の工程），続いて
水銀ランプにより紫外線をウエハ背面より照射してUVテ
ープ８の接着剤をキュアし，金属層７をUVテープ８より
剥離し易くする（第２図の工程）。In FIG. 3 (c), the conductive adhesive 6 is cured at a predetermined temperature, for example, 150 ° C. (step of FIG. 2). The agent is cured so that the metal layer 7 is easily peeled off from the UV tape 8 (step of FIG. 2).
この後は従来と同じ工程でダイボンディングを行う
（第２図の工程）。Thereafter, die bonding is performed in the same step as the conventional method (step in FIG. 2).
第３図（ｄ）において,UVテープ８を伸長し，ダイコ
レット13により目的のチップ１を真空吸引し，ダイボン
ダに搬送する。In FIG. 3D, the UV tape 8 is extended, the target chip 1 is vacuum-sucked by the die collet 13, and is conveyed to the die bonder.
第３図（ｅ）において，ダイコレット13につかまれた
チップ１は図示されないヒータにより加熱されたステー
ジ２のメッキ層５上に半田４によりボンディングされ
る。In FIG. 3 (e), the chip 1 held by the die collet 13 is bonded by solder 4 onto the plating layer 5 of the stage 2 heated by a heater (not shown).
第３図（ｆ）はボンディング状態を示す断面図であ
る。FIG. 3 (f) is a sectional view showing a bonding state.
従来例の第５図と相違する点は，実施例ではチップ１
と金属層７との間に導電性接着剤６による半田層を介在
することである。The difference from the conventional example shown in FIG.
And a metal layer 7 between which a solder layer of conductive adhesive 6 is interposed.
以上説明したように本発明によれば，背面に金属層の
ない半導体チップのダイボンディングを可能にして，従
来と同じAgペーストによる場合も，実施例のように半田
による場合にも本発明を適用でき，半導体製造装置の簡
易化とコスト低減化がはかれる。As described above, according to the present invention, die bonding of a semiconductor chip having no metal layer on the back surface is enabled, and the present invention is applied to a case using the same Ag paste as in the past and a case using solder as in the embodiment. As a result, simplification and cost reduction of semiconductor manufacturing equipment can be achieved.
第１図は本発明に使用する貼り付け用３層フィルムの断
面図， 第２図は本発明によるダイシング及びダイボンディング
工程の流れ図， 第３図（ａ）〜（ｆ）は実施例の各工程を説明する断面
図， 第４図は従来例によるダイシング及びダイボンディング
工程の流れ図， 第５図は従来のダイボンディング状態を説明する断面図
である。 図において， １は半導体チップ， ２はステージ， ３はチップ背面の金属層， ４は半田， ５はステージのメッキ層， ６は導電性接着剤， ７は金属層， ８はUVテープ である。FIG. 1 is a cross-sectional view of a three-layer film for pasting used in the present invention, FIG. 2 is a flow chart of dicing and die bonding steps according to the present invention, and FIGS. FIG. 4 is a flow chart of a dicing and die bonding process according to a conventional example, and FIG. 5 is a cross-sectional view illustrating a conventional die bonding state. In the figure, 1 is a semiconductor chip, 2 is a stage, 3 is a metal layer on the back of the chip, 4 is solder, 5 is a plating layer of the stage, 6 is a conductive adhesive, 7 is a metal layer, and 8 is a UV tape.
Claims (1)
層された３層フィルムの導電性接着剤面に半導体ウエハ
を貼り付ける工程と， 該３層フィルムを加熱して該導電性接着剤をキュアする
工程と， 該UVテープを厚さ方向に全部切断しないで該ウエハ及び
該金属層をダイシングし，背面に金属層を被着した個々
のチップに分割する工程と， 該チップをステージ上にボンディングする工程 とを有することを特徴とする半導体装置の製造方法。A step of attaching a semiconductor wafer to a conductive adhesive surface of a three-layer film in which a conductive adhesive, a metal layer, and a UV tape are sequentially laminated; and heating the three-layer film to form the conductive adhesive. Curing the agent, dicing the wafer and the metal layer without cutting the UV tape in the thickness direction, and dividing the wafer and the metal layer into individual chips each having a metal layer applied to the back surface thereof; A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6001589A JP2626033B2 (en) | 1989-03-13 | 1989-03-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6001589A JP2626033B2 (en) | 1989-03-13 | 1989-03-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02238641A JPH02238641A (en) | 1990-09-20 |
| JP2626033B2 true JP2626033B2 (en) | 1997-07-02 |
Family
ID=13129817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6001589A Expired - Lifetime JP2626033B2 (en) | 1989-03-13 | 1989-03-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2626033B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008505486A (en) * | 2004-06-30 | 2008-02-21 | フリースケール セミコンダクター インコーポレイテッド | Ultra-thin die and manufacturing method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2866453B2 (en) * | 1990-07-04 | 1999-03-08 | ローム株式会社 | Expanding tape and chip component mounting method |
| JPH04247640A (en) * | 1991-02-04 | 1992-09-03 | Matsushita Electron Corp | Manufacture of semiconductor device |
| JPH05179211A (en) * | 1991-12-30 | 1993-07-20 | Nitto Denko Corp | Dicing die-bonded film |
-
1989
- 1989-03-13 JP JP6001589A patent/JP2626033B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008505486A (en) * | 2004-06-30 | 2008-02-21 | フリースケール セミコンダクター インコーポレイテッド | Ultra-thin die and manufacturing method thereof |
| US8198705B2 (en) | 2004-06-30 | 2012-06-12 | Freescale Semiconductor, Inc. | Ultra-thin die and method of fabricating same |
| JP2013084999A (en) * | 2004-06-30 | 2013-05-09 | Freescale Semiconductor Inc | Ultra-thin die and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02238641A (en) | 1990-09-20 |
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