JP2625390B2 - Liquid crystal display device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device used for a display, a projector, a television and the like, and a driving method thereof.

[0002]

2. Description of the Related Art For the multimedia age, various personal computers (hereinafter, referred to as PCs), workstations (hereinafter, referred to as WS), televisions, etc., having different video frequencies, pixel numbers, and scanning methods are supported. There is an increasing demand for possible liquid crystal displays.

In order to support various sources such as PCs, WSs, and televisions, it is necessary to perform various scanning methods such as a progressive scanning method, an interlaced drive, and a two-line simultaneous drive with one liquid crystal display device. . Further, there is a demand for a liquid crystal display device capable of freely enlarging and displaying an image having a smaller number of pixels than that of the liquid crystal display device. These are realized mainly by devising the configuration and driving method of the vertical drive circuit of the liquid crystal display device.

Further, when displaying an image having a smaller number of pixels than the number of pixels of the liquid crystal display device, a blanking period is set in order to make the remaining upper and lower or left and right pixels outside the liquid crystal display area black. During that time, it is necessary to perform black display writing for the pixel.

In recent years, in liquid crystal projectors, which have become widespread as large-screen displays and presentation displays, three liquid crystals corresponding to red, green, and blue are used due to the difference in the number of times light reflected and bent through the liquid crystal display device. For one panel of the display device, the image needs to be mirror-inverted. Further, there is a demand for a flexible liquid crystal display device that can handle front projection, rear projection, floor placement, and ceiling suspension with one liquid crystal projector device. For this reason, the scanning circuits constituting the vertical drive circuit and the horizontal drive circuit are both required to be capable of bidirectional scanning.

[0006] As described above, a liquid crystal display device capable of covering all of the scanning method, enlarged display, movement, black display writing, and bidirectional scanning is strongly desired as a liquid crystal display device in the coming multimedia age. Hereinafter, such a liquid crystal display device is referred to as a multi-sync liquid crystal display device.

On the other hand, with the aim of reducing the size and cost of the liquid crystal display device, the technology for integrating peripheral driving circuits on the same substrate as the liquid crystal display device has been developed. The peripheral drive circuit is
The vertical drive circuit scans the gates of the thin film transistors forming the active matrix array, and the horizontal drive circuit supplies image signals to pixels.

[0008] When displaying an image of a specific number of pixels by a specific scanning method, a shift register circuit is used as a scanning circuit used in a horizontal drive circuit. However, when a shift register circuit is used, the vertical and vertical speeds are limited due to the limitation of the circuit speed and the limitation of the writing frequency of the data signal.
During the horizontal blanking period, the upper and lower and left and right black display writing cannot be performed, respectively, and it is difficult to realize the above-described multi-sync liquid crystal display device.

At present, an address decoder is used in a scanning circuit for a horizontal drive circuit of a multi-sync liquid crystal display device. FIG. 12 shows the horizontal scanning circuit 1 of the horizontal driving circuit 103.
FIG. 4 is a diagram showing a configuration of a conventional liquid crystal display device using an address decoder in 04. As shown in the figure, the liquid crystal display device has an active matrix array 101 for displaying an image.
, A vertical drive circuit 102, and a horizontal drive circuit 103. A plurality of control signals for selecting the sample and hold switch 108 are input to the address decoder 105. The selected sample-and-hold switch writes the multi-phase expanded data signal to the data bus line for each block. Here, a case is shown in which video signals S1 to S16 developed in 16 phases are supplied. On the output side of the sample-and-hold switch 108, a sample-and-hold capacitor 109 for holding written data and writing the held data to the pixel electrode is usually provided.

FIG. 13 is a diagram showing an example of a conventional driving method of a liquid crystal display device using an address decoder in a horizontal driving circuit scanning circuit. Here, it is assumed that the vertical drive circuit is a circuit corresponding to a multi-sync liquid crystal display device. The number of signal lines is 1280. In this case, the number of control signals is A0, / A0 (/ represents inversion to a logic level), A1, / A1,..., A6, / A6.
It becomes 14 pieces. As shown in the figure, control signals A0, / A0, A1, / A1,.
A, A6, and / A6 receive a clock signal, and the clock cycle of A (i + 1) (i is an integer from 1 to 5) is twice the clock cycle of Ai. By inputting such a control signal, sampling pulse signals SP1, SP2,..., SP80 for sequentially scanning the control lines of the sample and hold switches can be obtained. As a result, at times t1, t2, t3,.
Video signals can be sampled in sequence at the timing of 80 and written to the data bus line.

If an address decoder is used, one or a plurality of control lines of an arbitrary sample-and-hold switch can be simultaneously selected according to a combination of logic levels of control signals. Therefore, in the upper and lower black writing periods during the vertical blanking period, all control lines of the sample and hold switch can be selected, and the time for upper and lower black display writing can be sufficiently long. Also, during the horizontal blanking period, the sample and hold switches corresponding to the left and right black display areas can be simultaneously selected,
The time for black writing on the left and right can be sufficiently long. For these reasons, an address decoder is used in a scanning circuit for a horizontal drive circuit of a multi-sync liquid crystal display device.

[0012]

As shown in FIG. 12, in a conventional multi-sync liquid crystal display device, an address decoder is used in a scanning circuit for a horizontal drive circuit. However, in the case of an address decoder, the number of control lines increases as the number of signal lines increases and the number of video signal developments decreases. Therefore, problems such as an increase in the size of a liquid crystal display module and an increase in cost arise. For example, when the number of signal lines is 1280 and a video signal developed in 16 phases is input, 14 control terminals are required. Further, even if the number of signal lines is the same as 1280, when an 8-phase expanded video signal is input, 16 control terminals are required.

Since the address decoder has a large number of control signals as described above and selects an address according to a combination of the logic levels of the control signals, noise is generated in the output signal due to noise between the control signals and a timing shift. There is also a problem that it is easy to do.

On the other hand, in a liquid crystal display device using a shift register for a horizontal drive circuit scanning circuit, the number of clock signal terminals and input signal terminals required for driving the shift register is independent of the number of scanning lines. Although a total of about three lines is sufficient, as described above, the shift register cannot cope with the multi-sync liquid crystal display device due to the limitation of the circuit speed and the limitation of the data signal writing frequency.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems by significantly reducing the number of control signal terminals for driving a scanning circuit for a horizontal drive circuit as compared with an address decoder, and to reduce noise in an output signal. It is an object of the present invention to provide a small-sized, low-cost multi-sync liquid crystal display device which does not cause the problem and a driving method thereof.

[0016]

According to a first aspect of the present invention, there is provided an active matrix array in which switching elements are arranged at intersections of a plurality of scanning lines and a plurality of signal lines, a vertical drive circuit for driving the scanning lines, In a liquid crystal display device comprising a horizontal drive circuit for driving the signal line, the horizontal drive circuit sequentially shifts a pulse signal by a half cycle of a clock signal and outputs the shifted signal (N is a positive integer). And M
The first control terminals are connected in common for every number (M is an integer of 2 or more), and the commonly connected control terminals are connected to the N output terminals of the scanning circuit, respectively, and (2 × M
-1) (N × M) first logic gate circuits, each of which is commonly connected to a second control terminal, and the first control terminal is connected to an output terminal of the first logic gate circuit. Connected (N × M) second logic gate circuits whose second control terminals are commonly connected, and control terminals are commonly connected every J (J is a positive integer). The input terminal is connected to the output terminal of the second logic gate circuit and the input terminal is (J-
1) It is characterized by comprising (N × M) sample hold switches commonly connected every other.

According to a second aspect of the invention, in the liquid crystal display device according to the first aspect, the first and second logic gate circuits are two-input NAND circuits.

According to a third aspect of the invention, in the liquid crystal display device according to the first aspect, the scanning circuit includes means for shifting a pulse signal bidirectionally.

According to a fourth aspect of the present invention, in the first, second or third driving method of the liquid crystal display device, when the sampling period of the video signal input to the liquid crystal display device is T, the period is (2 × M × T) is input to the scanning circuit, and the pulse width is larger than 0 ((M + 1) × T) or less, the pulse period is (2 × M × T), and the phase is sequentially shifted by T. 2 × M) pulse signals A1, A
2,..., A (2 × M) are replaced with the (N × M) first
Control terminals D1, D2, D3 of the logic gate circuit of
, D (2 × M) in order, and the output of the first logic gate circuit reflects the signal reflected on the output of the second logic gate circuit as the second logic It is characterized in that it is driven by being input to a second control terminal of the gate circuit.

According to a fifth aspect of the present invention, in the method of driving a liquid crystal display device according to the third aspect of the present invention, when the sampling period of a video signal input to the liquid crystal display device is T, the period is (2 × M ×
T) is input to the scanning circuit, and the pulse width is larger than 0 ((M + 1) × T) or less, the pulse period is (2 × M × T), and the phase is sequentially shifted by T. 2 × M) pulse signals A1, A2,..., A
(2 × M) is converted to the second control terminals D1, D2, D3,..., D (2) of the (N × M) first logic gate circuits.
× M) in the reverse order, and the output of the first logic gate circuit reflects the signal reflected on the output of the second logic gate circuit as the second signal of the second logic gate circuit.
Is driven by inputting to the control terminal of

According to a sixth aspect, in the driving method of the liquid crystal display device according to the first, second, or third aspect, the output of the second logic gate circuit is provided during a vertical blanking period.
A signal that is not reflected on the output of the first logic gate circuit is input to a second control terminal of the second logic gate circuit, and a signal level corresponding to black display is input to the J input terminals of the sample hold switch. It is characterized by inputting to a terminal.

According to a seventh aspect, in the driving method of the liquid crystal display device according to the first, second, or third aspect, the frequency of the clock signal input to the scanning circuit is changed during the horizontal blanking period during the video writing period. A pulse signal is transferred by modulating the signal to a higher frequency than that of the first logic gate circuit. During the transfer period, the output of the scanning circuit reflects a signal reflected on the output of the first logic gate circuit. And the output of the first logic gate circuit is
The signal reflected on the output of the second logic gate circuit is
Input to a second control terminal of the second logic gate circuit,
A signal level corresponding to black display is input to the J input terminals of the sample hold switch and driven.

According to an eighth aspect of the present invention, there is provided an active matrix array in which switching elements are arranged at intersections of a plurality of scanning lines and a plurality of signal lines, a vertical driving circuit for driving the scanning lines, and a driving of the signal lines. In a liquid crystal display device comprising a horizontal drive circuit, the horizontal drive circuit sequentially shifts a pulse signal by a half cycle of a clock signal and outputs the shifted signal, and M (M is a positive integer) scanning circuits; Is an integer of 2 or more), the first control terminals are commonly connected, and
The commonly connected control terminals are respectively connected to N output terminals of the scanning circuit, and every (2 × M−1) second control terminals are commonly connected (N × M). A second logic gate circuit, an output buffer circuit using the output signal of the logic gate circuit as an input signal, and a control terminal commonly connected every J (J is a positive integer) the control terminal of which is connected to the output terminal. It is characterized in that it is connected to the output terminal of the buffer circuit, and the input terminal is composed of (N × M) sample-and-hold switches commonly connected every (J−1).

According to a ninth aspect, in the eighth driving method of the liquid crystal display device, a clock signal of a predetermined cycle is input to the scanning circuit during a vertical blanking period, and the output of the scanning circuit is the logic signal. A signal reflected on the output of the gate circuit is input to the second control terminal of the logic gate circuit, and a signal level corresponding to black display is input to the J input terminals of the sample and hold switch for driving. It is characterized by:

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the liquid crystal display device and the driving method of the present invention will be described in detail.

FIG. 1 is a view showing a first embodiment of the liquid crystal display device of the present invention. The liquid crystal display device includes an active matrix array 101 having thin film transistors arranged at intersections of scanning lines and signal lines, a vertical driving circuit 102 for driving scanning lines, and a horizontal driving circuit 103 for driving signal lines.
It is composed of As shown in the figure, the horizontal driving circuit 103 includes a horizontal scanning circuit 104 and the horizontal scanning circuit 10.
4 as a control signal. At this time, the control terminals of the sample-and-hold switch 108 are commonly connected to every 16 terminals, while the input terminals thereof are commonly connected every 15 terminals. By inputting the video signals S1 to S16 developed in 16 phases to respective input terminals, 16 video signals are sequentially written by 16 through the 16 sample and hold switches sequentially selected. The sample hold capacitor 109 is a storage capacitor for holding the video signal written to the data bus line and writing the held voltage to the pixel.

This embodiment shows a case where the number of signal lines is set to 1280 and a video signal expanded to 16 phases is input. In this case, as shown in the figure, an 80-bit horizontal scanning circuit 104 is required.

The horizontal scanning circuit 1 of the liquid crystal display device of this embodiment
04 is a half-bit 40-stage scanning circuit 105-1 to 105-41 that sequentially shifts a pulse signal input from the input terminal a110 or the input terminal b111 in synchronization with a clock signal, as shown in FIG. Each output signal P of the half-bit configuration scanning circuits 105-1 to 105-41
, P2,..., P40 and control signals D1, D2, D
3 and D4 as input signals, input signals of the first NAND gate circuits 106-1 to 106-80, and a common enable signal EN from the input terminal 112. It comprises second NAND gates 107-1 to 107-80 that serve as signals. Two first NAND gate circuits are connected to each output of the half-bit configuration scanning circuits 105-1 to 105-41, and control signals of four adjacent NAND gate circuits are all different. Is the feature.

The scanning circuit 105 having a half bit configuration is used.
-1 to 105-41 have a configuration capable of bidirectional scanning. When scanning in one direction, a pulse signal is input from the input terminal a110, and when scanning in the reverse direction, a pulse signal is input from the input terminal b111.

Half-bit scanning circuit 105-1 to 105-1
05-41 uses a circuit driven by a two-phase clock signal. Therefore, the half-bit configuration scanning circuit 105
The number of drive signals required to drive -1 to 105-41 is four in total, including two clock signals and two input signals, including a pulse signal input to the input terminal 111 when scanning in the reverse direction. Become. Further, the first NAND gate circuit 10
In addition to the control signals D1 to D4 of 6-1 to 106-80 and the enable signal EN of the second NAND gate circuit, the total number of drive signals input to the horizontal scanning circuit 104 is nine. The number of drive signals is such that the number of signal lines is 12
It does not change even when the number exceeds 80 or when the number of phase expansions of the video signal is reduced.

On the other hand, when the conventionally used address decoder is applied to a horizontal scanning circuit, the number of control signals is 14 as described above. That is, in the liquid crystal display device of the present embodiment, the number of drive signal terminals of the horizontal scanning circuit is 9/14 of the conventional one. If the number of phase expansions of the video signal is 8, the number of control signals of the address decoder is 16 as described above, and the number of drive signal terminals of the horizontal scanning circuit of this embodiment is It becomes 9/16 of the conventional.

In this embodiment, the number of stages of the half-bit scanning circuit is set to 40, and each output is set to two first NANs.
Although the configuration is such that the data is input to the D gate circuit, the configuration may be such that the number of stages of the half-bit configuration scanning circuit is 20 and each output is input to the four first NAND gate circuits.

In this embodiment, NAND gate circuits are used as the first and second logic gate circuits.
Both may be replaced with a NOR gate circuit. In that case, the half-bit configuration scanning circuit 10 in the present embodiment is used.
A signal whose logic level is opposite to the output signals P1 to P40 of 5-1 to 105-41 is input to the first NOR gate circuit, and the enable signal EN and the enable signal EN input to the second NAND gate circuit in the present embodiment. Needs to input a signal having an opposite logic level to the second NOR gate circuit. Further, it is necessary to provide an output buffer circuit for inverting the output of the second NOR gate circuit.

FIG. 2 is a diagram showing a first embodiment of a method for driving a liquid crystal display device according to the present invention. This embodiment shows an example of a driving method for writing a video signal to a data bus line using the liquid crystal display device shown in FIG. Hereinafter, the driving method will be described with reference to FIG.

First, the half-bit configuration scanning circuit 105-
1 to 105-41, a clock signal CLK having a clock cycle of (4 × T) (T is a sampling cycle of the sample hold switch) and an input pulse signal VSTa having a pulse width of (4 × T) from the input terminal a110. Input is performed at the timing shown in FIG. 2, and the input pulse signal is sequentially shifted in synchronization with the clock signal. As a result, as shown in the figure, the output signals P1 to P40 of the half-bit configuration scanning circuits 105-1 to 105-40 have a pulse width of (4 × T) and a phase sequentially shifted by (2 × T). The output pulse signal is output. Since the scanning circuit is usually driven by a two-phase clock signal, a CL signal is used as the clock signal.
A clock signal having a phase opposite to that of K may be input from outside. On the other hand, the first NAND gate circuits 106-1 to 106-1
As the control signals 106 to 80, pulse signals having a pulse width of (3 × T), a pulse period of (4 × T), and a phase sequentially shifted by T are input at the timing shown in FIG. Also, the second NAND gate circuits 107-1 to 107-1
A signal having a high logic level is input as the enable signal EN of 107-80. As a result, the second NA
As the output signals SP1 to SP80 of the ND gate circuits, sampling pulse signals having a pulse width of (3 × T) and a phase sequentially shifted by T are obtained. As shown in the figure, the sample and hold switch selected by the sampling pulse signal has 16 points at the timings t1, t2, t3,..., T80 at which the sampling pulse falls.
The phase parallel data signals S1 to S16 are sampled, and a video signal is written to a data bus line.

As described above, the video signal can be written to the data bus line.

FIG. 3 is a diagram showing a second embodiment of the driving method of the liquid crystal display device according to the present invention. This embodiment shows an example of a driving method for writing a video signal to a data bus line, similarly to the first embodiment shown in FIG. 2, but the first method will be described below. The sampling accuracy can be improved as compared with the embodiment.

First, the half-bit scanning circuit 105-
1 to 105-41, (T) of which the clock cycle is (4 × T)
Is a sampling period of a sample-and-hold switch). A clock signal CLK and an input pulse signal VSTa having a pulse width of (4 × T) from an input terminal a110 are input at the timing shown in FIG. Synchronized and sequentially shifted. As a result, as shown in the figure, the output signals P1 to P40 of the half-bit configuration scanning circuits 105-1 to 105-40 have a pulse width of (4 × T) and a phase sequentially shifted by (2 × T). The output pulse signal is output. The driving method up to this point is exactly the same as in the first embodiment.

On the other hand, the first NAND gate circuit 106-
As the control signals D1 to D4 of 1 to 106-80, pulse signals having a pulse width of ((5/2) × T), a pulse period of (4 × T), and a phase sequentially shifted by T are shown in FIG. To enter. That is, the rising time of the control pulse signal D4 is input at a timing delayed by (T / 2) with respect to the falling time of the control pulse signal D1. Also, the second NAND gate circuits 107-1 to 107-1
A signal having a high logic level is input as the enable signal EN of 7-80. As a result, the second NAND
As the output signals SP1 to SP80 of the gate circuits, sampling pulse signals having a pulse width of ((5/2) × T) and a phase sequentially shifted by T are obtained. As shown in the figure, the sample-and-hold switch selected by the sampling pulse signal has 1 at the timings t1, t2, t3,..., T80 at which the sampling pulse falls.
The six-phase parallel data signals S1 to S16 are sampled, and the video signals are written to the data bus lines.

The difference from the first embodiment is that, in the first embodiment, as shown in FIG. 2, the timing at which the video signal is sampled coincides with the timing at which another sampling pulse signal rises. On the other hand, in the present embodiment, as shown in FIG. 3, at the timing when the video signal is sampled, the other sampling pulse signals are constant. Generally, at the rising time and the falling time of the sampling pulse signal, noise is easily generated in the input video signal. Therefore, when the sampling time coincides with the rising time of another sampling pulse signal as in the first embodiment, a video signal containing noise is sampled, and the sampling accuracy is poor. Become. On the other hand, as in the second embodiment, the sampling time and
When the rising time of the other sampling pulse signal is shifted, noise from the other sampling pulse signal is eliminated, so that the sampling accuracy can be improved as compared with the first embodiment.

As described above, the video signal can be written to the data bus line with higher accuracy than in the first embodiment shown in FIG.

FIG. 4 is a diagram showing a third embodiment of the method for driving a liquid crystal display device according to the present invention. This embodiment shows an example of a driving method for writing a video signal to a data bus line, as in the first and second embodiments shown in FIGS. 2 and 3, which will be described below. The sampling accuracy can be improved by the method as compared with the first and second embodiments.

First, the half-bit scanning circuit 105-
1 to 105-41, (T) of which the clock cycle is (4 × T)
Is the sampling period of the sampling and holding switch). A clock signal CLK and an input pulse signal VSTa having a pulse width of (4 × T) from the input terminal a110 are input at the timing shown in FIG. 4, and the input pulse signal is synchronized with the clock signal. And shift sequentially. As a result, as shown in the figure, the output signals P1 to P40 of the half-bit configuration scanning circuits 105-1 to 105-40 have a pulse width of (4 × T) and a phase sequentially shifted by (2 × T). The output pulse signal is output. The driving method so far is exactly the same as in the first and second embodiments.

On the other hand, the first NAND gate circuit 106-
As control signals D1 to D4 of 1 to 106-80, pulse signals having a pulse width of (T / 2), a pulse period of (4 × T), and a phase sequentially shifted by T are input at the timing shown in the figure. That is, the control pulse signal D1 is input at a timing delayed by ((3 × T) / 2) with respect to the output pulse signal P1 of the half-bit scanning circuit. Also, the enable signal E of the second NAND gate circuits 107-1 to 107-80
As N, a signal having a high logic level is input.
As a result, the output signal SP1 of the second NAND gate circuit
As SP80, a sampling pulse signal whose pulse width is (T / 2) and whose phase is sequentially shifted by T is obtained.
As shown in the figure, the sample and hold switch selected by the sampling pulse signal has timings t1, t2, t3,.
At time t80, the 16-phase parallel data signals S1 to S16 are sampled sequentially, and the video signal is written to the data bus line.

The difference from the first embodiment is that in the first embodiment, as shown in FIG. 2, the timing at which the video signal is sampled coincides with the timing at which another sampling pulse signal rises. On the other hand, in the present embodiment, as shown in FIG. 4, the other sampling pulse signal is constant at the timing when the video signal is sampled. Therefore, for the same reason as described in the description of the second embodiment,
The sampling accuracy can be improved as compared with the first embodiment.

The difference from the second embodiment is that in the second embodiment, three adjacent sampling pulse signals are shifted while overlapping, while in the present embodiment, the sampling pulse signals are shifted. The point is that signal overlap is completely eliminated. By driving in this manner, while the sample hold switch is in the ON state, noise from other sampling pulse signals can be completely removed, and sampling is performed with higher accuracy than in the second embodiment. be able to.

As described above, the video signal can be written to the data bus line with higher accuracy than the first and second embodiments. However, the driving method of the third embodiment is an effective driving method when the sampling frequency of the sample hold switch has a margin because the width of the sampling pulse is shorter than the sampling period T. .

In the third embodiment, the first N
Since the rising and falling timings of the output pulse signal of the half-bit scanning circuit input to the AND gate circuit and the control pulse signals D1 to D4 are shifted, noise caused by crosstalk and hazard is completely eliminated. Can be.

FIG. 5 is a diagram showing a fourth embodiment of the driving method of the liquid crystal display device according to the present invention. This embodiment shows an example of a driving method for writing a video signal to a data bus line using the liquid crystal display device shown in FIG. 1, as in the first embodiment of the driving method. The second embodiment differs from the first embodiment in that the active matrix array is scanned in the reverse direction. Hereinafter, the driving method will be described with reference to FIG.

First, the half-bit scanning circuit 105-
1 to 105-41, (T) of which the clock cycle is (4 × T)
Is a scanning line selection period) The clock signal CLK and the input pulse signal VSTb having a pulse width of (4 × T) from the input terminal b111 are input at the timing shown in FIG. 5, and the input pulse signal is synchronized with the clock signal. , In the order reverse to that of the first embodiment. As a result, as shown in the figure, the output signals P1 to P40 of the half-bit configuration scanning circuits 105-2 to 105-41 have the pulse width of (4 × T) and the opposite phases of (2 × T). The pulse signals sequentially shifted in sequence are output. Since the scanning circuit is normally driven by a two-phase clock signal, a clock signal having a phase opposite to that of CLK may be input from the outside. On the other hand, as the control signals D1 to D4 of the first NAND gate circuits 106-1 to 106-80, the pulse width is (3 × T), the pulse period is (4 × T),
Pulse signals sequentially shifted by T in the reverse order are input at the timing shown in the figure. Also, the second NA
As the enable signal EN of the ND gate circuits 107-1 to 107-80, a signal having a high logic level is input. As a result, as the output signals SP1 to SP80 of the second NAND gate circuit, sampling pulse signals whose pulse width is (3 × T) and whose phases are sequentially shifted by T in reverse order are obtained. The sample and hold switch selected by the sampling pulse signal is, as shown in the figure, at the timing t when the sampling pulse falls.
At 1, t2, t3,..., T80, the 16-phase parallel data signals S1 to S16 are sampled, and the video signals are written to the data bus lines.

As described above, the first embodiment 1
The video signal can be written to the data bus line in the opposite direction to the left and right. That is, it is possible to display an image by inverting left and right.

FIG. 6 is a diagram showing a fifth embodiment of the method for driving a liquid crystal display device according to the present invention. In the present embodiment, when displaying an image having a smaller number of pixels than the number of pixels of the liquid crystal display device using the liquid crystal display device shown in FIG. 1 shows an example of a driving method for writing black display. Here, a case in which black lines are written in 128 lines each for the upper and lower lines will be described. Hereinafter, the driving method will be described with reference to FIG.

First, during the vertical blanking period,
The clock signal CLK input to the half-bit configuration scanning circuits 105-1 to 105-41 and the input signal VSTa from the input terminal a110 are kept at a low level. At this time, it is assumed that the data of the pulse signal is not held in the half-bit configuration scanning circuits 105-1 to 105-41, and that all of them are swept out. As a result, the output signals P1-P of the half-bit configuration scanning circuits 105-1 through 105-40 are output.
Numeral 40 is a low-level fixed signal as shown in the figure. On the other hand, the first NAND gate circuits 106-1 to 106-1
As the 6-80 control signals D1 to D4, signals whose logic levels are constant at a low level are input. As shown in the figure, at time t1, the second NAND gate circuit 1
The logic level of the enable signal EN of 07-1 to 107-80 is switched from high level to low level. Thereafter, at time t4, the logic level of the enable signal EN is switched from low level to high level.
As a result, the output signal SP1 of the second NAND gate circuit
As SP80, a signal whose logic level is high is output during the period from t1 to t4. Thereby, t1
From t4 to t4, all the sample hold switches can be turned on.

On the other hand, during the period from t2 to t3, the gate pulse signals GP1 to GP1
The logic levels of GP128, GP899 to GP1024 are set to high level. In addition, a constant signal for displaying black is input as the video signals S1 to S16.

By driving in this manner, in the period from t2 to t3, 1280 sample-hold switches and all the pixel switches connected to the upper and lower 128 lines can be turned on. Video signal for black display,
Writing can be performed simultaneously on six lines. At this time, as the time from t2 to t3, in which the upper and lower black writing is performed, a long time for sufficiently writing the black display signal in the pixels for 256 lines is taken.

As described above, upper and lower black writing can be performed during the vertical blanking period.

FIGS. 7 and 8 (FIG. 9 shows the arrangement of FIGS. 7 and 8) show a sixth embodiment of the method of driving the liquid crystal display device of the present invention. In the present embodiment, when displaying an image having a smaller number of pixels than the number of pixels of the liquid crystal display device using the liquid crystal display device shown in FIG. 1 shows an example of a driving method for performing black writing. Here, left and right 12
A driving method when black writing is performed for every eight columns will be described. The driving method will be described below with reference to FIGS.

First, during the horizontal blanking period,
Half-bit configuration scanning circuits 105-1 to 105-41
A clock signal CLK having a clock cycle of (2 × T) (T is a sampling cycle of a sample hold switch in a video writing period) and an input pulse signal VSTa having a pulse width of (2 × T) from an input terminal a110 are Input is performed at the timing shown in FIG. 7, and the input pulse signal is sequentially shifted in synchronization with the clock signal. Thereby, the half-bit configuration scanning circuits 105-1 to 105-4
As shown in the figure, as output signals P1 to P4, pulse signals having a pulse width of (2 × T) and a phase sequentially shifted by T are output. Since the scanning circuit is usually driven by a two-phase clock signal, a clock signal CLK
A clock signal having a phase opposite to that of the clock signal may be input from the outside. On the other hand, the first NAND gate circuits 106-1 to 106-1
As the control signals D <b> 1 to D <b> 4 of 06-80, signals having a high logic level are input. Further, the second NA
As the enable signal EN of the ND gate circuits 107-1 to 107-80, a signal whose logic level is high is input. As a result, as the output signals SP1 to SP8 of the second NAND gate circuit, the pulse width is (2 × T),
A sampling pulse signal whose phase is sequentially shifted by T every other signal is obtained.

In this horizontal blanking period, the signal levels of black display are input as the video signals S1 to S16, so that the sampling pulse signals SP1 and SP
2, SP3 and SP4, SP5 and SP6, SP7 and SP8
Fall at the respective times t1, t2, t3, t4
, The black display signal is sampled, and the data bus lines DS1 to DS32, DS33 to DS64, DS6
5 to DS96 and DS97 to DS128. As described above, in the horizontal blanking period, black display writing for the left 128 columns can be performed.

In the video writing period following the horizontal blanking period, driving is performed in the same manner as the driving method of the first embodiment shown in FIG. First, the period of the clock signal CLK is modulated from (2 × T) to (4 × T). By performing such modulation, the half-bit configuration scanning circuit 10
As output signals of 5-5 to 105-36, pulse signals having a pulse width of (4 × T) and a phase sequentially shifted by (2 × T) are obtained. Although the pulse width of the pulse signal P6 is (5 × T), it does not affect the operation.
On the other hand, the first NAND gate circuits 106-1 to 106-
As the 80 control signals D1 to D4, the pulse width is (3 ×
T), a pulse signal whose pulse cycle is (4 × T) and whose phase is sequentially shifted by T is input at the timing shown in the figure.
Also, the second NAND gate circuits 107-1 to 107-
As the enable signal EN of 80, a signal having a high logic level is input. As a result, as the output signals SP9 to SP72 of the second NAND gate circuit, sampling pulse signals having a pulse width of (3 × T) and a phase sequentially shifted by T are obtained. The sample and hold switch selected by the sampling pulse signal samples the 16-phase parallel data signals S1 to S16 at the timing when the sampling pulse falls, and writes the video signals to the data bus lines DS129 to DS1152.

In the horizontal blanking period following the video writing period, black display writing of 128 columns on the right side is performed. First, the half-bit configuration scanning circuits 105-1 to 105-1
The period of the clock signal of 5-41 is changed from (4 × T) to (2 × T).
T). Thereby, each output signal P37-P of the half bit configuration scanning circuit 105-37-105-40 is output.
40, the pulse width is (2 × T) as shown in the figure.
Thus, a pulse signal whose phase is sequentially shifted by T is output. The pulse widths of the pulse signals P37 and P38 are (4 × T) and (3 × T), respectively, but do not affect the operation. On the other hand, the first NAND gate circuit 10
As the control signals D1 to D4 of 6-1 to 106-80, signals having a high logic level are input. Furthermore, the second
As an enable signal EN of the NAND gate circuit, a signal having a high logic level is input. As a result, the second NAND gate circuits 107-1 to 107-8
As an output signal of 0, a sampling pulse signal having a pulse width of (2 × T) and a phase sequentially shifted by T every other signal is obtained. However, the sampling pulse signal SP7
3 and SP74, and SP75 and SP76,
The pulse widths are (4 × T) and (3 × T), respectively. On the other hand, during this horizontal blanking period,
By inputting signal levels for black display as the video signals S1 to S16, sampling pulse signals SP73 and SP74, SP75 and SP76, SP77 and SP78,
Each time t at which SP79 and SP80 fall
At 5, t6, t7 and t8, the black display signal is sampled, and the data bus lines DS1153 to DS118 are sampled.
4, DS1185-DS1216, DS1217-DS
1248 and DS1249 to DS1280. As described above, in the horizontal blanking period, black display writing for the right 128 columns can be performed.

As described above, right and left black display writing can be performed using the liquid crystal display device shown in FIG.

FIG. 10 is a view showing a second embodiment of the liquid crystal display device of the present invention. The difference from the liquid crystal display device of the first embodiment shown in FIG. 1 is that the second NAND gate circuits 107-1 to 107-80 of FIG.
2-1 to 802-80. Other configurations are the same as those of the first embodiment. That is, as shown in the figure, the horizontal scanning circuit 104 of the liquid crystal display device of the present embodiment includes a half-bit 40-stage scanning circuit 105 that sequentially shifts a pulse signal input from an input terminal 110 in synchronization with a clock signal. -1 to 105-41, output signals P1, P2,..., P40 of the half-bit configuration scanning circuits 105-1 to 105-41, and control signals D1,
It comprises NAND gate circuits 801-1 to 801-80 using D 2, D 3, and D 4 as input signals, and inverting output buffer circuits 802-1 to 802-80 using respective output signals of the NAND gate circuits as input signals. Have been. Two NAND gate circuits are connected to each output of the half-bit configuration scanning circuits 105-1 to 105-41,
It is characterized in that the control signals of the four adjacent NAND gate circuits are all different.

The scanning circuit 105 having a half bit configuration
-1 to 105-41 have a configuration capable of bidirectional scanning. When scanning in the reverse direction, a pulse signal is input from the input terminal b111.

Half-bit configuration scanning circuits 105-1 to 105-1
05-41 uses a circuit driven by a two-phase clock signal. Therefore, the half-bit configuration scanning circuit 105
The number of drive signals required to drive -1 to 105-41 is four in total, including two clock signals and two input signals, including a pulse signal input when scanning in the reverse direction. Further, NAND gate circuits 801-1 to 801-
80 control signals D1 to D4 and the horizontal scanning circuit 10
The total number of drive signals input to 4 is eight.
This number of drive signals does not change even when the number of signal lines exceeds 1280 or when the number of phase expansions of the video signal is reduced. On the other hand, when the conventionally used address decoder is applied to the horizontal scanning circuit, as described above,
The number of control signals is 14. That is, in the liquid crystal display device of the present embodiment, the number of drive signal terminals of the horizontal scanning circuit is
It is 4/7 of the conventional one. If the number of phase expansions of the video signal is 8, the number of control signals of the address decoder is 16 as described above, and the number of drive signal terminals of the horizontal scanning circuit of this embodiment is It is half of the conventional one.

In the present embodiment, the number of stages of the half-bit scanning circuit is set to 40 and each output is input to two NAND gate circuits. The configuration may be such that each output is input to four NAND gate circuits.

In this embodiment, a NAND gate circuit is used as a logic gate circuit, but may be replaced with a NOR gate circuit. In this case, the half-bit configuration scanning circuits 105-1 to 105-4 in this embodiment are used.
It is necessary to input a signal having a logic level opposite to that of the output signals P1 to P40 to the NOR gate circuit, and to use the inverted output buffer circuit as a normal output buffer circuit.

FIG. 11 is a diagram showing a seventh embodiment of the driving method of the liquid crystal display device according to the present invention. In the present embodiment, FIG.
When displaying an image having a smaller number of pixels than the number of pixels of the liquid crystal display device by using the liquid crystal display device shown in (1), during the vertical blanking period, the driving method of writing the remaining upper and lower pixel regions in black. An example is shown. Here, a case in which black lines are written in 128 lines each for the upper and lower lines will be described. Hereinafter, the driving method will be described with reference to FIG.

First, the half-bit scanning circuit 105-
1 to 105-41, a clock signal CLK having a predetermined clock cycle TB and an input pulse signal VSTa having a pulse width of TB from the input terminal a110 are input at the timing shown in FIG. 11, and the input pulse signal is converted into a clock signal. Shift sequentially in synchronization. Thereby, each output signal P1 of the half-bit configuration scanning circuits 105-1 to 105-41 is output.
As shown in the figure, the pulse width is TB, and
A pulse signal whose phase is sequentially shifted by (TB / 2) is output. Since the scanning circuit is usually driven by a two-phase clock signal, a clock signal having a phase opposite to that of CLK may be input from the outside as a clock signal. On the other hand, as the control signals D1 to D4 of the NAND gate circuits 801-1 to 801-80, signals having a high logic level are input. As a result, the output buffer circuit 802-1
As the output signals SP1 to SP80 of .about.802-80, sampling pulse signals in which the pulse width is TB and the phase is shifted sequentially by (TB / 2) every other signal are obtained.

In this vertical blanking period, the signal levels of black display are input as the video signals S1 to S16, so that the sampling pulse signals SP1 and SP
2, SP3 and SP4, SP5 and SP6, ..., SP7
9 and SP80 fall, each time t1, t
, T3,..., T40, the black display signal is sampled and the data bus lines DS1 to DS32, D
S33 to DS64, DS65 to DS96, ..., DS
1249 to DS1280. At this time,
Gate pulse signal GP for the line for writing the upper and lower black display
The logic levels of 1 to GP128 and GP899 to GP1024 are set to high level. As a result, the black display signal written to the data bus line can be written to the pixels of the upper and lower 128 lines.

As described above, using the liquid crystal display device shown in FIG. 10, upper and lower black display writing can be performed during the vertical blanking period.

In this embodiment, the pulse width of the pulse signal input to the half-bit scanning circuits 105-1 to 105-41 is TB, but (L × TB) and (L is an integer of 2 or more) are used. May be. In that case, the pulse width of the sampling pulse signal output from the output buffer circuit is
(L × TB), and the period for writing the black display signal to the data bus line can be extended.

Further, the driving method of the present embodiment can be applied to the liquid crystal display device shown in FIG. In that case, a signal having a high logic level may be input as an enable signal of the second NAND gate circuit.

The liquid crystal display device of this embodiment is one in which polycrystalline silicon thin film transistors are integrated on a glass substrate. The vertical drive circuit and the horizontal drive circuit are CM
Although it is configured by the OS static circuit, it can be configured by a CMOS dynamic circuit. Although a polycrystalline silicon thin film transistor is used in this embodiment, the thin film transistor may be formed of another thin film transistor using amorphous silicon, cadmium selenium, or the like for the semiconductor layer. It is also possible to use a single-crystal silicon MOS transistor.

[0075]

As described above, when the liquid crystal display device of the present invention and the method of driving the same are applied, the number of control elements input to the horizontal drive circuit of the multi-sync liquid crystal display device is 9/9.
Since it can be reduced from 14 to about half, it is extremely effective in reducing the size and cost of the multi-sync liquid crystal display device. This effect becomes remarkable as the number of pixels of the liquid crystal display device increases and the number of phase expansions of the input video signal decreases.

Further, since no noise is generated due to the crosstalk of the control signal, the liquid crystal display device can be operated stably.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a liquid crystal display device of the present invention.

FIG. 2 is a diagram showing a first embodiment of a method for driving a liquid crystal display device according to the present invention.

FIG. 3 is a diagram showing a second embodiment of the driving method of the liquid crystal display device of the present invention.

FIG. 4 is a diagram showing a third embodiment of the driving method of the liquid crystal display device of the present invention.

FIG. 5 is a diagram showing a fourth embodiment of the driving method of the liquid crystal display device of the present invention.

FIG. 6 is a diagram showing a fifth embodiment of the driving method of the liquid crystal display device of the present invention.

FIG. 7 is a view showing a sixth embodiment of the driving method of the liquid crystal display device of the present invention.

FIG. 8 is a diagram showing a sixth embodiment of the driving method of the liquid crystal display device of the present invention.

FIG. 9 is a diagram showing the arrangement of FIGS. 7 and 8;

FIG. 10 is a view showing a second embodiment of the liquid crystal display device of the present invention.

FIG. 11 is a diagram showing a seventh embodiment of the method for driving the liquid crystal display device of the present invention.

FIG. 12 is a diagram showing a conventional liquid crystal display device.

FIG. 13 is a diagram illustrating an example of a driving method of a conventional liquid crystal display device.

[Explanation of symbols]

 Reference Signs List 101 active matrix array 102 vertical drive circuit 103 horizontal drive circuit 104 horizontal scan circuit 105-1 to 105-41 half-bit scan circuit 106-1 to 106-80 first NAND gate circuit 107-1 to 107-80 second NAND gate circuit 108 Sample hold switch 109 Sample hold capacitor 110 Input terminal a 111 Input terminal b 112 Enable signal 801 NAND gate circuit 802 Output buffer circuit

Claims (7)

(57) [Claims] An active matrix array having switching elements disposed at intersections of a plurality of scanning lines and a plurality of signal lines; a vertical driving circuit for driving the scanning lines; and a horizontal driving circuit for driving the signal lines. A horizontal drive circuit comprising: an N-stage (N is a positive integer) scanning circuit for sequentially shifting and outputting a pulse signal by a half cycle of a clock signal; and M (M is 2 or more) For each (integer), the first control terminals are commonly connected, and the commonly connected control terminals are respectively connected to the N output terminals of the scanning circuit, and (2 ×
(N × M) first logic gate circuits, each of which has a common connection with every other M-1) second control terminals; and a first control terminal is an output terminal of the first logic gate circuit. , And the second control terminal is commonly connected (N ×
M) second logic gate circuits, a control terminal is commonly connected for every J pieces (J is a positive integer), a control terminal thereof is connected to an output terminal of the second logic gate circuit, and an input terminal (N × M) sample hold switches commonly connected every (J−1) pixels. 2. A method for driving a liquid crystal display device according to claim 1, wherein a clock signal having a period of (2 × M × T) is provided when a sampling period of a video signal input to the liquid crystal display device is T. When the pulse width is larger than 0 ((M + 1) × T) and the pulse cycle is (2 × M ×
T), phase shifted sequentially by T, different (2 × M)
.., A (2 × M)
.., D (2 × M) are sequentially input to the second control terminals D1, D2, D3,..., D (2 × M) of the (N × M) first logic gate circuits, respectively. A signal output from a circuit reflected on an output of the second logic gate circuit is input to a second control terminal of the second logic gate circuit to drive the liquid crystal display device. Method. 3. A method of driving a liquid crystal display device according to claim 1, wherein, when a sampling period of a video signal input to the liquid crystal display device is T, a clock signal having a period of (2 × M × T) is used. When the pulse width is larger than 0 ((M + 1) × T) and the pulse cycle is (2 × M ×
T), phase shifted sequentially by T, different (2 × M)
.., A (2 × M)
.., D (2 × M) of the (N × M) first logic gate circuits, respectively, in the reverse order. A liquid crystal display device, wherein a signal whose output from a logic gate circuit is reflected on the output of the second logic gate circuit is input to a second control terminal of the second logic gate circuit and driven. Drive method. 4. The method for driving a liquid crystal display device according to claim 1, wherein during a vertical blanking period, an output of said first logic gate circuit is a signal which is not reflected on an output of said second logic gate circuit. A second control terminal of the second logic gate circuit, and a signal level corresponding to black display is input to J input terminals of the sample and hold switch. Method. 5. The method of driving a liquid crystal display device according to claim 1, wherein a frequency of a clock signal input to the scanning circuit is modulated to a higher frequency during a horizontal blanking period than during a video writing period. A pulse signal is transferred, and during the transfer period, a signal in which the output of the scanning circuit is reflected on the output of the first logic gate circuit is input to a second control terminal of the first logic gate circuit. And a signal in which the output of the first logic gate circuit is reflected on the output of the second logic gate circuit is input to a second control terminal of the second logic gate circuit, which corresponds to black display. A method for driving a liquid crystal display device, wherein a signal level is input to J input terminals of the sample and hold switch to drive the sample and hold switch. 6. An active matrix array in which switching elements are arranged at intersections of a plurality of scanning lines and a plurality of signal lines, a vertical driving circuit for driving the scanning lines, and a horizontal driving circuit for driving the signal lines. A horizontal drive circuit comprising: an N-stage (N is a positive integer) scanning circuit for sequentially shifting and outputting a pulse signal by a half cycle of a clock signal; and M (M is 2 or more) For each (integer), the first control terminals are commonly connected, and the commonly connected control terminals are respectively connected to the N output terminals of the scanning circuit, and (2 ×
(N × M) logic gate circuits each having a second common control terminal commonly connected to every M-1) logic circuits, an output buffer circuit having an output signal of the logic gate circuit as an input signal, and a control terminal Are connected in common every J (J is a positive integer), the control terminal is connected to the output terminal of the output buffer circuit, and the input terminal is connected in common every (J−1) (N
× M) sample and hold switches. 7. The method for driving a liquid crystal display device according to claim 6, wherein a clock signal having a predetermined period is input to the scanning circuit during a vertical blanking period, and the output of the scanning circuit is the logic gate. A signal reflected on an output of the circuit is input to a second control terminal of the logic gate circuit, and a signal level corresponding to black display is input to the J input terminals of the sample and hold switch to drive. A method for driving a liquid crystal display device, comprising: