JP2621681B2 - Stacked varistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated varistor functioning as a voltage non-linear resistor, and more particularly, to obtaining a voltage non-linear characteristic by utilizing a Schottky barrier generated at an interface between an internal electrode and a semiconductor ceramic layer. The present invention relates to a structure in which leakage current can be improved without deteriorating characteristics such as surge withstand voltage and limiting voltage in the case of (1).

[0002]

2. Description of the Related Art In recent years, in the field of electronic equipment such as communication equipment, miniaturization and integration of electronic parts have been rapidly progressing, and accordingly, demands have also been made for varistors to be reduced in size or reduced in voltage. Is growing. In order to meet such a demand, there has conventionally been a laminated varistor instead of a disk type (for example, Japanese Patent Application No. 1-302496). The laminated varistor is configured such that a semiconductor ceramic layer and an internal electrode are alternately stacked to form a laminated body, and one end face of each of the internal electrodes is alternately led out to both end faces of the laminated body. An external electrode connected to one end surface of the internal electrode is formed. A non-connection internal electrode that is not connected to the external electrode is provided in the ceramic layer between the internal electrodes, and the non-connection internal electrode is sealed in the laminate. In such a multilayer varistor, a voltage non-linearity characteristic is obtained by a Schottky barrier formed at the interface between the internal electrode and the non-connection internal electrode and the semiconductor ceramic layer. Since the Schottky barrier is determined by the materials and materials of the internal electrodes and the ceramic layer, the varistor voltage is controlled by the number of stacked ceramic layers.

[0003]

By the way, in the above-mentioned laminated varistor, it is effective to increase the number of laminated internal electrodes or to increase the electrode area in order to further improve the capacitance, surge withstand voltage or limiting voltage. It is. However, the above-mentioned conventional multilayer varistor has a problem that when the number of stacked internal electrodes is increased or the electrode area is increased, the leakage current increases and the power consumption increases. On the other hand, when the area of the internal electrode is reduced, the leakage current can be suppressed, but on the contrary, the surge withstand capability is reduced and the limit voltage is increased.

The present invention has been made in view of the above-mentioned conventional circumstances, and has as its object to provide a multilayer varistor capable of reducing leakage current without deteriorating characteristics of surge withstand voltage and limiting voltage.

[0005]

Means for Solving the Problems The present inventors examined the cause of the leakage current, and found that when an electric field was applied to the pore existing at the interface between the internal electrode and the semiconductor ceramic layer, a discharge was generated. Was found to be increasing. It has been found that it is effective to fill the pores with a metal oxide in order to reduce the leakage current due to such discharge. The reason why the metal oxide is selected as a material for filling the pores is that oxygen needs to be supplied into the semiconductor ceramic layer during the firing process of the laminate. Therefore, the present inventors selected Mn ₃ O ₄ , Co ₂ CO ₃ , and Pr ₆ O ₁₁ from several kinds of metal oxides, added these to the internal electrode, and performed an experiment.
When Co ₂ CO ₃ and Pr ₆ O ₁₁ were added alone, Co and Pr diffused into the semiconductor ceramic layer after firing, and as a result, the pores could not be filled. On the other hand, even when the same metal oxide was added with Mn ₃ O ₄ , it was confirmed that Mn was present near the interface between the internal electrode and the semiconductor ceramic layer and filled the pores without being diffused during firing. . As a result, the present inventors have conceived that, by adding Mn, the leakage current can be reduced while satisfying the characteristics such as surge withstand voltage and limiting voltage with the same internal electrode area, and made the present invention.

Therefore, the present invention provides a multilayer varistor in which a semiconductor ceramic layer and internal electrodes are alternately stacked to form a laminate, and external electrodes are formed on both end surfaces of the laminate. A voltage non-linear characteristic is given by a Schottky barrier formed at the interface between the ceramic layer and the internal electrode, and manganese exists near the interface between the semiconductor ceramic layer and the internal electrode, and this manganese is present at the interface. It is characterized by filling the pores that occur in The invention of claim 2, in claim 1, is characterized by being composed of a metallic material the internal electrode contains 0.01 to 20.0 wt% of manganese in terms of Mn ₃ O _4. Here, the reason for limiting the amount of Mn ₃ O ₄ added is that if this amount is less than 0.01% by weight, the effect of improving the leakage current is hardly obtained, and if it exceeds 20.0% by weight, the sintering of the semiconductor ceramic layer is not achieved. This is because the varistor voltage tends to be insufficient, and as a result, the varistor voltage becomes extremely large. Note that the laminated varistor of the present invention also includes one in which a non-connected internal electrode that is not connected to an external electrode is disposed between the internal electrodes in the ceramic layer, and is formed at the interface between the semiconductor ceramic layer and the electrode. The present invention can be applied to any device that obtains a voltage non-linear characteristic by a Schottky barrier.

[0007]

According to the multilayer varistor according to the present invention, manganese is present near the interface between the semiconductor ceramic layer and the internal electrode where the voltage nonlinearity is given by the Schottky characteristic, and pores generated at the interface by the manganese are reduced. Because it is filled, leakage current due to discharge can be reduced,
Power consumption can be reduced. In addition, since the leakage current can be reduced with the same electrode area, each characteristic such as surge withstand voltage and limiting voltage does not deteriorate. In addition, since the manganese is present near the interface, the impurity concentration can be increased, and the Schottky barrier can be improved accordingly.

[0008]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 and 2 are views for explaining a multilayer varistor according to an embodiment of the present invention. In the drawing, reference numeral 1 denotes a laminated varistor of the present embodiment. The varistor 1 has a rectangular parallelepiped shape, and alternately laminates a semiconductor ceramic layer 2 containing ZnO as a main component and an internal electrode 3 made of Pt, and fires the sintered body 4 integrally and left and right end faces thereof. External electrodes 5 made of Ag / Pd are formed on 4a and 4b. Further, one end faces 3a of the internal electrodes 3 are alternately led to left and right end faces 4a, 4b of the sintered body 4, and the end faces 3a are electrically connected to the external electrodes 5. Further, the other parts of the internal electrodes 3 are located inside the ceramic layer 2 and sealed in the sintered body 4.

In the semiconductor ceramic layer 2 between the internal electrodes 3, a pair of unconnected internal electrodes 6, 6 are provided. The peripheral end surface of each of the non-connected internal electrodes 6 is located inside the ceramic layer 2 and is sealed in the sintered body 4, whereby the external electrodes 5 are provided between the internal electrodes 3 and 3.
A non-connected internal electrode 6 that is not electrically connected to the internal electrode is interposed. A ceramic layer 7 as a dummy is provided on the upper and lower surfaces of the sintered body 4.

Manganese is added to the internal electrodes 3 and the non-connected internal electrodes 6, and the added amount of manganese is in the range of 0.01 to 20.0% by weight in terms of Mn ₃ O _4. I have. As a result, the manganese exists near the interface between the internal electrode 3 and the non-connection internal electrode 6 and the semiconductor ceramic layer 2 and fills the pores.

Next, a method of manufacturing the multilayer varistor 1 of the present embodiment will be described. First, ZnO (97.9 mol%), Co
CO ₃ (1.0 mol%), MnCO ₃ (0.5 mol%), Sb ₂ O
₃ (2.0 mol%) and Bi ₂ O ₃ (0.5 mol%) in the above-mentioned respective molar ratios are mixed with B ₂ O ₃ , Si
A glass powder composed of O ₂ , PbO and ZnO is added at 0.1% by weight to prepare a raw material. Further, an organic binder is mixed with the raw material to form a green sheet having a thickness of 10 μm by a reverse roller method, and the green sheet is cut into a rectangular shape to form a large number of ceramic sheets 2.
a is formed.

[0012] Next, by mixing the organic vehicle to the metal powder consisting of Pt to form a paste, Mn ₃ to the paste
With the addition 0.01～20.0Wt% of O _4, Co ₂ C
O _3, and Pr ₆ and O ₁₁ were added respectively 0.001 ~30.0wt% create an electrode paste.

Then, the internal electrode 3 is formed by printing the electrode paste on the upper surface of the ceramic sheet 2a. In this case, one end face 3a of the internal electrode 3 is formed to extend to the edge of the ceramic sheet 2a, and the other end face is formed inside the ceramic sheet 2a. The electrode paste is also printed on the upper surface of another ceramic sheet 2a to form the non-connection internal electrodes 6. All the end faces of the non-connection internal electrode 6 have the ceramic sheet 2
It is formed so as to be located inside the periphery of a.

Next, as shown in FIG.
The semiconductor ceramic layer 2 is formed by laminating two ceramic sheets 2a on which the non-connection internal electrodes 6 are formed on the ceramic sheet 2a on which the ceramic layers 2 are formed.
Are sequentially laminated. In this case, the ceramic layers 2 and the internal electrodes 3 are arranged so as to alternately overlap with each other, and only one end face 3a of the internal electrode 3 is alternately exposed to the left and right end faces of the ceramic layer 2. Further, a ceramic layer 7 made up of ten ceramic sheets 2a on which no electrode paste is printed is laminated on the upper and lower surfaces thereof. Next, a pressure of ² t / cm ² is applied in the laminating direction to press and compress to form a laminated body, which is cut into a predetermined size. Thus, as shown in FIG. 1, a structure in which a pair of non-connection internal electrodes 6 are arranged in the ceramic layer 2 between the internal electrodes 3 is obtained.

[0015] Then, the above-mentioned laminate is subjected to
It is heated and fired at a temperature of 1150 ° C. for 3 hours to obtain a sintered body 4. During this firing, manganese precipitates near the interface between the internal electrode 3 and the non-connection internal electrode 6 and the semiconductor ceramic layer 2 and fills pores generated at the interface, that is, pores. Finally, on the left and right end faces 4a and 4b of the sintered body 4 where one end face 3a of the internal electrode 3 is exposed, Ag:
After applying a conductive paste having a weight ratio of Pd = 7: 3, the external electrode 5 is formed by baking. As a result, the multilayer varistor 1 of this embodiment is manufactured.

As described above, according to the present embodiment, Mn ₃ O ₄ is applied to the internal electrodes 3 and the non-connected internal electrodes 6 in an amount of 0.01 to 2%.
0.0% by weight was added so that the Mn filled pores formed at the interfaces between the electrodes 3 and 6 and the semiconductor ceramic layer 2 and existed near the interfaces. As a result, it is possible to reduce only the leakage current with the same electrode area without deteriorating characteristics such as surge withstand voltage and limiting voltage, and to suppress power consumption.

[0017]

[Table 1]

Table 1 shows the results of tests performed to confirm the effects of the multilayer varistor 1 of this embodiment. In this test, a multilayer varistor was prepared by changing the amount of Mn ₃ O ₄ added in the range of 0.001 to 30 wt% by the manufacturing method of the above example. The varistor voltage _V1mA , the limiting voltage ratio _V2A / _V1mA , the capacitance PF, and the
The surge resistance A when a triangular current wave of μsec was applied and the resistance MΩ when a voltage of 2 V was applied for 30 seconds were measured. For comparison, the same measurement was performed on a conventional multilayer varistor to which Mn was not added. As is clear from the table, all of the samples of the present embodiment, the comparative sample, and the conventional sample have the limiting voltage ratio V _{2 A} / V _{1 mA} of 1.5 to 1.7 and the surge withstand capability of 50 A, which are satisfactory characteristics. The resistance values of the conventional sample and the comparative sample with Mn of 0.001 wt% are low at 0.19 MΩ and 0.91 MΩ, respectively, and the leakage current is large. On the other hand, high values of 1.82 to 20.0 MΩ were obtained in the example samples and comparative samples having Mn of 0.01 wt% or more. However, when the addition amount exceeds 20 wt%, V _{1 mA} is increased and the capacitance is also decreased. This added amount of Mn ₃ O ₄ from it can be seen that it is desirable in the range of 0.01~20.0wt%.

In the above embodiment, the case where the non-connection internal electrode 6 is disposed in the semiconductor ceramic layer 2 between the internal electrodes 3 has been described as an example. However, the present invention has a structure in which the non-connection internal electrode is not disposed. Of course, the same effect can be obtained in this case.

[0020]

As described above, according to the multilayer varistor according to the present invention, since manganese filling the pores is present at the interface between the semiconductor ceramic layer on which the Schottky barrier is formed and the internal electrode, the surge withstand capability can be obtained. Without deteriorating each characteristic such as the limiting voltage and the like, the leakage current due to the discharge can be reduced, the power consumption can be suppressed, and the Schottky barrier can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a laminated varistor according to an embodiment of the present invention.

FIG. 2 is an exploded perspective view for explaining a method of manufacturing the multilayer varistor of the embodiment.

[Explanation of symbols]

 Reference Signs List 1 laminated varistor 2 semiconductor ceramic layer 3 internal electrode 4 sintered body (laminated body) 4a, 4b end face of sintered body 5 external electrode

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yasunobu Yoneda 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Co., Ltd. Inside Murata Manufacturing Co., Ltd. (72) Inventor Yukio Sakabe 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Co., Ltd. (56) References JP-A-2-73604 (JP, A) JP-A-51-73256 (JP, A)

Claims (2)

(57) [Claims] 1. A a semiconductor ceramic layers and the internal electrodes overlapped alternately to form a laminate, the laminate type varistor obtained by forming external electrodes on both end faces of the laminate, the semiconductor
A shot formed at the interface between the ceramic layer and the internal electrode
Voltage nonlinearity is given by the Tokey barrier,
Near the interface between the semiconductor ceramic layer and the internal electrode
Manganese is present at the interface
Varistors characterized by filling in pores . 2. The method according to claim 1, wherein the internal electrode is Mn.
A multilayer varistor comprising a metal material containing 0.01 to 20.0% by weight of manganese in terms of ₃ O ₄ .