JP2620650B2 - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JP2620650B2 JP2620650B2 JP2201220A JP20122090A JP2620650B2 JP 2620650 B2 JP2620650 B2 JP 2620650B2 JP 2201220 A JP2201220 A JP 2201220A JP 20122090 A JP20122090 A JP 20122090A JP 2620650 B2 JP2620650 B2 JP 2620650B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- substrate
- conductive path
- microcomputer
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/14—Structural association of two or more printed circuits
- H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/225—Correcting or repairing of printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/44—Manufacturing insulated metal core circuits or other insulated electrically conductive core circuits
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Combinations Of Printed Boards (AREA)
Description
【発明の詳細な説明】 （イ）産業上の利用分野 本発明は混成集積回路装置に関し、特にメモリおよび
マイクロコンピュータを搭載した混成集積回路装置の配
線接続構造に関する。The present invention relates to a hybrid integrated circuit device, and more particularly to a wiring connection structure of a hybrid integrated circuit device equipped with a memory and a microcomputer.
（ロ）従来の技術 第４図を参照して従来の混成集積回路装置を説明す
る。(B) Conventional technology A conventional hybrid integrated circuit device will be described with reference to FIG.
第４図は混成集積回路装置の平面図を示し、混成集積
回路装置は絶縁金属基板（70）と、導電路（72）と、中
継パッド（74）と、外部リード用パッド（76）と、ボン
ディングワイア（78）と、第１のゲートアレイ（80）、
マイクロコンピュータ（82）、メモリ（84）、第２のゲ
ートアレイ（86）、その他の周辺集積回路（88）等の複
数の集積回路素子と、チップ抵抗（90）等で構成されて
いる。FIG. 4 shows a plan view of the hybrid integrated circuit device. The hybrid integrated circuit device has an insulating metal substrate (70), a conductive path (72), a relay pad (74), an external lead pad (76), A bonding wire (78), a first gate array (80),
It comprises a plurality of integrated circuit elements such as a microcomputer (82), a memory (84), a second gate array (86), and other peripheral integrated circuits (88), and a chip resistor (90).
絶縁金属基板（70）は絶縁処理されたアルミニウム基
板が主として用いられ、この絶縁金属基板（70）に貼着
した銅箔をホトエッチングする等して所定形状に配線パ
ターンが形成され、後述する集積回路素子を固着するた
めのパッド、その電極を接続するためのパッド、中継パ
ッド（74）等の導電路（72）および外部リード用パッド
（76）等が形成されている。As the insulating metal substrate (70), an insulated aluminum substrate is mainly used, and a wiring pattern is formed in a predetermined shape by, for example, photo-etching a copper foil adhered to the insulating metal substrate (70). Pads for fixing circuit elements, pads for connecting electrodes thereof, conductive paths (72) such as relay pads (74), and pads for external leads (76) are formed.
上記した導電路（72）の所定位置には、第１および第
２のゲートアレイ（80）（86）、マイクロコンピュータ
（82）、メモリ（84）および周辺集積回路（88）を形成
するチップ状の素子がAgペーストにより固着され、チッ
プコンデンサ、チップ抵抗素子等の電子部品が接続強
度、コンタクト抵抗を考慮して半田固着されている。At predetermined positions of the above-mentioned conductive path (72), chip-like parts forming the first and second gate arrays (80) and (86), the microcomputer (82), the memory (84) and the peripheral integrated circuit (88) are formed. Are fixed by an Ag paste, and electronic components such as a chip capacitor and a chip resistor are fixed by soldering in consideration of connection strength and contact resistance.
斯る大規模な混成集積回路装置は多種の電気機器に使
用され、近年ではプリンタコントローラとしても使用さ
れる。Such large-scale hybrid integrated circuit devices are used for various types of electric equipment, and in recent years, are also used as printer controllers.
一般的なプリンタコントローラを混成集積回路装置と
して実現する場合につき簡単に説明すると、例えば第１
のゲートアレイ（80）はセントロニクス仕様のパラレル
・データ、センサ入力およびプリンタのフロントパネル
・スイッチ信号等を入力してマイクロコンピュータ（8
2）に入力する入力インターフェースとして機能し、第
２のゲートアレイ（86）はマイクロコンピュータ（82）
の命令に基づいて文字フォントを印字ヘッドに出力し、
またキャリッジリターンあるいはフィードフォワード信
号等の制御信号等を出力する出力インターフェースとし
て機能する。また、マイクロコンピュータ（82）には例
えば16ビットの入出力ポートと20ビットのアドレス空間
を有する80ピンのマイクロコンピュータが使用され、メ
モリ（84）には例えば256Kビット、28ピンのメモリが使
用される。The case where a general printer controller is realized as a hybrid integrated circuit device will be briefly described as follows.
The gate array (80) of the microcomputer (8) inputs parallel data of the Centronics specification, sensor inputs, printer front panel switch signals, etc.
The second gate array (86) functions as an input interface for input to 2), and the microcomputer (82)
The character font is output to the print head based on the instruction of
Also, it functions as an output interface for outputting a control signal such as a carriage return or a feed forward signal. The microcomputer (82) is, for example, an 80-pin microcomputer having a 16-bit input / output port and a 20-bit address space, and the memory (84) is, for example, a 256-Kbit, 28-pin memory. You.
上記構造の混成集積回路装置はプリンタコントローラ
に要求される小型化の要求に一応、応えることができ、
また絶縁金属基板を使用するため機器の放熱の問題も解
決されている。The hybrid integrated circuit device having the above structure can respond to the demand for miniaturization required for the printer controller,
In addition, the use of an insulated metal substrate solves the problem of heat radiation of equipment.
（ハ）発明が解決しようとする課題 しかしながら、16ビットのデータバスと20ビットもの
アドレス空間を有し、しかも大規模構成されるディジタ
ル回路の配線パターンは極めて複雑なものとなり、デー
タバス、アドレスバス等の導電路は基板上の処所で、ジ
ャンピングワイア接続と称される技術を用いて相互に接
続しなければならなかった。(C) Problems to be Solved by the Invention However, the wiring pattern of a large-scale digital circuit having a 16-bit data bus and a 20-bit address space becomes extremely complicated, and the data bus and the address bus Such conductive paths had to be interconnected at a location on the substrate using a technique called jumping wire connection.
斯るジャンピングワイア接続技術を用いることによ
り、比較的離間する導電路間の接続が行えるものの、極
めて多数のデータバス、アドレスバスを必要とするマイ
クロコンピュータ、メモリ等を搭載する混成集積回路装
置においては、第４図に示す如く、極めて多数のジャン
ピングワイアを必要としていた。By using such a jumping wire connection technique, connection between conductive paths that are relatively separated from each other can be performed, but in a hybrid integrated circuit device equipped with a microcomputer, a memory, and the like that require an extremely large number of data buses and address buses. As shown in FIG. 4, an extremely large number of jumping wires were required.
その結果、ジャンピングワイアを固着するためのパッ
ド数の増加による基板実装有効面積の低下および装置の
小型化の点で限界があり、大容量かつ超小型の混成集積
回路装置の実現が困難であった。As a result, there is a limit in terms of a reduction in the effective area for mounting the substrate due to an increase in the number of pads for fixing the jumping wires and a reduction in the size of the device, and it has been difficult to realize a large-capacity and ultra-compact hybrid integrated circuit device. .
（ニ）課題を解決するための手段 本発明は上記課題に鑑みてなされたものであって、メ
モリおよびマイクロコンピュータ等の素子の周辺にアド
レスバス、データバス等の配線パターンを形成した多層
基板を接着樹脂含浸シートを介して絶縁配置し、この多
層基板を介してマイクロコンピュータとその周辺回路素
子間のアドレスバス、データバス等の接続、並びにマイ
クロコンピュータおよびその周辺回路素子と所定の導電
路との接続を行うことによって、ワイヤボンディングの
数を著しく削減し高信頼並びに高密度かつ小型の混成集
積回路装置を提供するものである。(D) Means for Solving the Problems The present invention has been made in view of the above problems, and has been made in consideration of a multilayer substrate in which wiring patterns such as an address bus and a data bus are formed around elements such as a memory and a microcomputer. Insulated and arranged via an adhesive resin impregnated sheet, connection of an address bus, a data bus, etc. between the microcomputer and its peripheral circuit elements via this multilayer substrate, and connection of the microcomputer and its peripheral circuit elements with predetermined conductive paths. It is an object of the present invention to provide a highly reliable, high-density, and small-sized hybrid integrated circuit device by remarkably reducing the number of wire bondings by performing connection.
（ホ）作 用 多層基板に形成された導電路を介してアドレスバス、
データバス等の接続が行われるため長スパンの接続が可
能になり、マイクロコンピュータとその周辺回路素子間
の接続、並びにマイクロコンピュータおよびその周辺回
路素子と所定の導電路との接続において、従来の如き、
ジャンピングワイア接続を不要とすることができる。(E) Operation The address bus, via the conductive path formed on the multilayer substrate,
The connection of the data bus and the like is made possible, so that a long-span connection can be made, and the connection between the microcomputer and its peripheral circuit elements and the connection between the microcomputer and its peripheral circuit elements and a predetermined conductive path are the same as those in the related art. ,
Jumping wire connection can be eliminated.
また、接着樹脂含浸シートを用いて多層基板を絶縁固
着するため多層基板の接着工程が簡素化されると共に絶
縁金属基板と多層基板間の絶縁性能が向上する。Further, since the multilayer substrate is insulated and fixed by using the adhesive resin impregnated sheet, the bonding process of the multilayer substrate is simplified, and the insulation performance between the insulating metal substrate and the multilayer substrate is improved.
（ヘ）実 施 例 以下、本発明をプリンタコントローラ用の混成集積回
路装置に適用した実施例を第１図乃至第３図を参照して
説明する。(F) Embodiment Hereinafter, an embodiment in which the present invention is applied to a hybrid integrated circuit device for a printer controller will be described with reference to FIGS.
第１図は実施例の平面図であり、混成集積回路装置は
絶縁金属基板（12）（但し、同平面図には当該金属基板
上に形成された絶縁樹脂層が現れているにすぎないの
で、後述の断面構造の説明に際しては絶縁金属基板（1
2）に使用する参照番号を絶縁樹脂層にも使用する）、
この絶縁金属基板（12）上に所定のパターンに形成され
た導電路（14）、外部リード用パッド（18）、第１のゲ
ートアレイ（24）、マイクロコンピュータ（26）、メモ
リ（28）、第２のゲートアレイ（30）、その他の周辺集
積回路（32）、チップ抵抗（34）および本発明に特徴的
な多層基板（40）等で示されている。なお、多層基板
（40）下の絶縁金属基板（12）上にも導電路（14）が形
成されている。FIG. 1 is a plan view of an embodiment, in which a hybrid integrated circuit device is an insulated metal substrate (12) (however, in the plan view, only an insulating resin layer formed on the metal substrate appears. In the description of the cross-sectional structure described below, the insulating metal substrate (1
The reference number used in 2) is also used for the insulating resin layer),
A conductive path (14) formed in a predetermined pattern on the insulating metal substrate (12), an external lead pad (18), a first gate array (24), a microcomputer (26), a memory (28), This is shown by a second gate array (30), other peripheral integrated circuits (32), chip resistors (34), and a multilayer substrate (40) characteristic of the present invention. The conductive path (14) is also formed on the insulating metal substrate (12) below the multilayer substrate (40).
絶縁金属基板（12）にはアルミニウムが使用され、陽
極酸化により表面がアルマイト処理され、その一主面に
エポキシ樹脂あるいはポリイミド樹脂等の接着性を有す
る絶縁樹脂が被覆される。Aluminum is used for the insulating metal substrate (12), the surface of which is anodized by anodic oxidation, and one main surface of which is coated with an insulating resin having adhesive properties such as an epoxy resin or a polyimide resin.
導電路（14）、外部リード用パッド（18）は前記絶縁
金属基板（12）に予め貼着した銅箔をホトエッチングす
る等して所定のパターンに形成され、特にバス（16）と
して示す導電路（14）により分断される一部の導電路
（14）はアルミワイア（22）によりジャンピング接続さ
れる。また、接地電位の導電路（14）は基板金属（20）
に接続される。The conductive path (14) and the external lead pad (18) are formed in a predetermined pattern by, for example, photo-etching a copper foil previously adhered to the insulating metal substrate (12). A part of the conductive path (14) divided by the path (14) is jump connected by an aluminum wire (22). In addition, the ground potential conductive path (14) is a substrate metal (20)
Connected to.
第１および第２のゲートアレイ（24）（30）、マイク
ロコンピュータ（26）、メモリ（28）、その他の周辺集
積回路（32）にはチップ素子が使用され、それらは所定
の導電路（14）上にAgペーストにより固着される。ま
た、チップ抵抗（34）およびチップコンデンサは所定の
導電路（14）に半田固着される。なお、集積回路素子の
機能は従来例の項で説明したので省略する。Chip elements are used for the first and second gate arrays (24) and (30), the microcomputer (26), the memory (28), and other peripheral integrated circuits (32), and they are provided in predetermined conductive paths (14). ) Is fixed on top with Ag paste. Further, the chip resistor (34) and the chip capacitor are fixed to the predetermined conductive path (14) by soldering. The function of the integrated circuit device has been described in the section of the conventional example, and thus the description thereof is omitted.
次に、第２図を参照して本発明に特徴的な多層基板
（40）を説明する。Next, a multilayer substrate (40) characteristic of the present invention will be described with reference to FIG.
多層基板（40）は厚さ0.6mm〜1.0mmのガラスエポキ
シ、紙エポキシ、紙フェノール、ポリイミド等の樹脂に
より形成され、図示するように、第１および第２のゲー
トアレイ（24）（30）、マイクロコンピュータ（26）お
よびメモリ（28）のチップを露出させる孔（42）および
切り欠き（42）が形成されている。なお、以下の説明に
より明かとなるが、この孔（42）はマイクロコンピュー
タ（26）等の集積回路素子の周辺にボンディングパッド
を多層に配列するために形成されるものであって、実質
的にその目的が達成される形状であれば孔に限定される
ものではない。The multilayer substrate (40) is formed of a resin such as glass epoxy, paper epoxy, paper phenol, or polyimide having a thickness of 0.6 mm to 1.0 mm. As shown in the drawing, the first and second gate arrays (24) and (30) A hole (42) and a notch (42) for exposing chips of the microcomputer (26) and the memory (28) are formed. As will be apparent from the following description, this hole (42) is formed for arranging bonding pads in multiple layers around an integrated circuit element such as a microcomputer (26), and is substantially formed. The shape is not limited to the hole as long as the object is achieved.
また、この多層基板（40）の両面には周知の方法によ
り、その一部を図示するように、アドレスバス、データ
バス等の導電路（44）が形成され、適宜の位置でスルー
ホール（46）により接続されている。As shown in the drawing, conductive paths (44) such as an address bus and a data bus are formed on both sides of the multilayer substrate (40) by a known method, and through holes (46) are formed at appropriate positions. ).
所定の導電路（44）の一部は多層基板（40）の周端部
に延在形成されて、絶縁金属基板（12）上に形成された
パッドとボンディング接続されるパッド（48）が形成さ
れ、他の所定の導電路（44）の一部は孔（42）の周囲に
延在形成されて、第１および第２のゲートアレイ（24）
（30）、マイクロコンピュータ（26）およびメモリ（2
8）の電極とボンディング接続されるパッド（50）が形
成されている。前記パッド（48）およびそのワイヤボン
ディング工程は、多層基板（40）の裏面の所定位置に半
田バンプを形成し、絶縁金属基板（12）上に形成された
対応するパッドとバンプ接続を行うようにすることによ
り省略することができる。A part of the predetermined conductive path (44) is formed to extend at the peripheral end of the multilayer substrate (40) to form a pad (48) to be bonded to a pad formed on the insulating metal substrate (12). A part of another predetermined conductive path (44) is formed so as to extend around the hole (42), and the first and second gate arrays (24) are formed.
(30), microcomputer (26) and memory (2
A pad (50) to be bonded to the electrode of (8) is formed. The pad (48) and its wire bonding step are performed such that solder bumps are formed at predetermined positions on the back surface of the multilayer substrate (40) and bump connections are made with the corresponding pads formed on the insulating metal substrate (12). By doing so, it can be omitted.
第３図を参照して本発明をさらに詳細に説明する。 The present invention will be described in more detail with reference to FIG.
同図は理解を容易にするため一部側面図で示した第１
図のＩ−Ｉ線断面図であり、本発明の混成集積回路装置
は金属基板（10）、絶縁樹脂層（12）、この絶縁樹脂層
（12）上に形成した導電路（14）および外部リード用パ
ッド（18）、Agペースト層（15）を介して導電路（14）
上に固着した第１および第２のゲートアレイ（24）（3
0）、マイクロコンピュータ（26）、メモリ（28）から
なる主基板と、前記集積回路チップのための孔（42）
（側面図で示されている）を形成した多層基板（40）
と、この多層基板（40）を主基板に絶縁接着する接着樹
脂含浸シート（60）で示されている。FIG. 1 is a first side view partially shown for easy understanding.
FIG. 2 is a cross-sectional view taken along the line II of FIG. 1. The hybrid integrated circuit device of the present invention includes a metal substrate (10), an insulating resin layer (12), a conductive path (14) formed on the insulating resin layer (12), and an external circuit. Conductive path (14) through lead pad (18), Ag paste layer (15)
The first and second gate arrays (24) (3
0), a main substrate including a microcomputer (26) and a memory (28), and a hole (42) for the integrated circuit chip.
Multilayer substrate (40) formed (shown in side view)
And an adhesive resin impregnated sheet (60) for insulatingly bonding the multilayer substrate (40) to the main substrate.
接着樹脂含浸シート（60）は厚さ0.5mm程度の和紙に
接着性を有する例えばエポキシ系の樹脂を含浸させ、多
層基板（40）と略同形に形成したものである。この接着
樹脂含浸シート（60）は常温では接着性がなく、押圧下
で125℃程度に加熱することによりその含浸樹脂が溶融
し、さらに熱硬化して多層基板（40）と主基板とを接着
する。従って、通常の接着剤を使用する場合に比較し
て、良好な絶縁が得られるばかりか接着剤の調整、塗布
の工程を省くことができ、多層基板（40）接着工程が簡
素化される。また、この接着樹脂含浸シート（60）の厚
さは多層基板（40）の上面の高さが前記集積回路素子の
上面の高さと略等しくなるように設計され、ワイヤボン
ディングを容易にするよう配慮される。The adhesive resin-impregnated sheet (60) is formed by impregnating a Japanese paper having a thickness of about 0.5 mm with an adhesive resin, for example, an epoxy-based resin, and forming the same shape as the multilayer substrate (40). This adhesive resin impregnated sheet (60) has no adhesiveness at room temperature, and when heated to about 125 ° C under pressure, the impregnated resin is melted and heat-cured to bond the multilayer board (40) to the main board. I do. Therefore, as compared with the case where a normal adhesive is used, not only good insulation can be obtained, but also the step of adjusting and applying the adhesive can be omitted, and the bonding step of the multilayer substrate (40) is simplified. The thickness of the adhesive resin-impregnated sheet (60) is designed so that the height of the upper surface of the multilayer substrate (40) is substantially equal to the height of the upper surface of the integrated circuit element, and consideration is given to facilitating wire bonding. Is done.
この接着樹脂含浸シート（60）および前記多層基板
（40）は主基板に形成したガイドポスト（図示しない）
に係合させる等して主基板上に積層配置された後、押圧
下で所定の温度条件が付与されて、接着樹脂含浸シート
（60）の含浸樹脂が溶融され、さらに熱硬化される。そ
して、多層基板（40）の孔（42）により露出される領域
にスタンプ法によりAgペースト層（15）が形成され、そ
のAgペースト層（15）の上に第１および第２のゲートア
レイ（24）（30）、マイクロコンピュータ（26）、メモ
リ（28）等の集積回路素子が配置される。The adhesive resin-impregnated sheet (60) and the multilayer board (40) are formed by guide posts (not shown) formed on the main board.
After being stacked on the main substrate by being engaged with, for example, a predetermined temperature condition is applied under pressure, the impregnated resin of the adhesive resin impregnated sheet (60) is melted, and further thermoset. Then, an Ag paste layer (15) is formed in a region exposed by the hole (42) of the multilayer substrate (40) by a stamp method, and the first and second gate arrays (15) are formed on the Ag paste layer (15). 24) (30), integrated circuit elements such as a microcomputer (26) and a memory (28) are arranged.
そこで、主基板を加熱してAgペースト層（15）を溶融
させ、前記集積回路素子を導電路（14）上に固着する
と、第１図に図示するように、第１および第２のゲート
アレイ（24）（30）、マイクロコンピュータ（26）、メ
モリ（28）の周辺にはそれら集積回路素子の電極と接続
すべきパッドが２層に配列され、最短距離で絶縁金属基
板（12）上の導電路（14）あるいは多層基板（40）上の
導電路（44）の何れかにワイヤボンディングすることが
可能になる。それら集積回路素子の電極と導電路（14）
を接続するボンディングワイヤを参照番号（36）、集積
回路素子の電極と多層基板（40）のパッド（50）を接続
するボンディングワイヤを参照番号（52）、さらに多層
基板（40）のパッド（48）と導電路（14）を接続するボ
ンディングワイヤを参照番号（54）で示す。Then, when the main substrate is heated to melt the Ag paste layer (15) and the integrated circuit element is fixed on the conductive path (14), the first and second gate arrays are formed as shown in FIG. (24) (30), a microcomputer (26), and a memory (28) are arranged in two layers with pads to be connected to the electrodes of the integrated circuit element on the periphery of the insulating metal substrate (12) at the shortest distance. Wire bonding can be performed to either the conductive path (14) or the conductive path (44) on the multilayer substrate (40). Electrodes and conductive paths of those integrated circuit devices (14)
Reference number (36) refers to a bonding wire connecting the integrated circuit element, reference number (52) refers to a bonding wire connecting the electrode of the integrated circuit element to the pad (50) of the multilayer substrate (40), and further refers to the pad (48) of the multilayer substrate (40). ) And the conductive path (14) are indicated by reference numeral (54).
上記のように、多層基板に形成された導電路を介して
アドレスバス、データバス等の接続が行われる本発明で
は、長スパンの接続が可能になり、マイクロコンピュー
タとその周辺回路素子間の接続、並びにマイクロコンピ
ュータおよびその周辺回路素子と所定の導電路との接続
において、中継パッドを不要とすることができると共
に、多層基板（40）の接着後に集積回路素子を固着する
ため集積回路素子の表面を破損するおそれがない。ま
た、マイクロコンピュータおよびその周辺回路素子のレ
イアウトを規格化し、図示するようにシンプルにするこ
とができる。As described above, according to the present invention in which the connection of the address bus, the data bus, and the like is performed through the conductive path formed on the multilayer substrate, the connection of a long span is possible, and the connection between the microcomputer and its peripheral circuit elements is enabled. In addition, in connecting the microcomputer and its peripheral circuit elements to predetermined conductive paths, relay pads can be dispensed with, and the integrated circuit elements can be fixed after bonding the multilayer substrate (40). There is no risk of damage. Also, the layout of the microcomputer and its peripheral circuit elements can be standardized and simplified as shown.
ここで、本発明の混成集積回路装置を実現する工程例
を以下に簡単に示す。Here, an example of steps for realizing the hybrid integrated circuit device of the present invention will be briefly described below.
半田印刷チップ付（チップ抵抗）半田溶融（210
℃）洗浄接着樹脂含浸シートおよび多層基板配置
多層基板接着（125℃）Agペースト塗布ダイボンデ
ィング（集積回路チップ）Agキュア（155℃）ワイ
ヤボンディング樹脂コート（125℃）外部リード付
ケーシング 以上、本発明を一実施例に基づいて説明したが、本発
明の、例えば接着樹脂含浸シートの素材、レイアウトを
規格化すべきマイクロコンピュータおよびその周辺回路
素子の範囲、種類等は種々の変更が可能であって本発明
が実施例に限定されるものでないことは当業者に明らか
である。With solder printed chip (chip resistance) Solder melting (210
C) Washing adhesive resin impregnated sheet and multilayer board arrangement Multilayer board adhesion (125C) Ag paste application Die bonding (integrated circuit chip) Ag cure (155C) Wire bonding resin coat (125C) Casing with external leads Although the description has been given based on one embodiment, the range and type of the material of the adhesive resin-impregnated sheet, the microcomputer for which the layout should be standardized, and the peripheral circuit elements thereof can be variously changed. It is clear to a person skilled in the art that the invention is not limited to the examples.
（ト）発明の効果 以上述べたように本発明によれば、 （１）ワイヤボンディング数が削減されるため工程が簡
素化される。また、これにより混成集積回路装置の信頼
性が向上する。(G) Effects of the Invention As described above, according to the present invention, (1) the number of wire bondings is reduced, so that the process is simplified. This also improves the reliability of the hybrid integrated circuit device.
（２）中継パッドが削減されるため実装密度が向上す
る。(2) The mounting density is improved because the number of relay pads is reduced.
（３）マイクロコンピュータおよびその周辺回路素子の
所定の電極が最短距離で接続されるため、配線容量に起
因する障害がない。(3) Since the predetermined electrodes of the microcomputer and its peripheral circuit elements are connected in the shortest distance, there is no obstacle due to the wiring capacitance.
（４）マイクロコンピュータおよびその周辺回路素子の
レイアウトを小型かつ規格化することができるため、混
成集積回路装置のパターン設計が容易になる。(4) Since the layout of the microcomputer and its peripheral circuit elements can be reduced in size and standardized, the pattern design of the hybrid integrated circuit device is facilitated.
（５）常温での取扱が容易であって、熱硬化する接着樹
脂含浸シートを使用するため多層基板の接着工程が簡素
化されると共に基板間の絶縁が良好になる。(5) Since it is easy to handle at room temperature and uses a thermosetting adhesive resin impregnated sheet, the process of bonding a multilayer substrate is simplified and insulation between the substrates is improved.
（６）多層基板の接着後に集積回路素子の固着が行われ
るため集積回路素子が破損するおそれがない。(6) Since the integrated circuit element is fixed after the multilayer substrate is bonded, there is no possibility that the integrated circuit element is damaged.
第１図は本発明の一実施例の平面図、第２図は本発明に
特徴的な多層基板の平面図、第３図は第１図のＩ−Ｉ線
断面図、第４図は従来例の平面図。 （12）……絶縁金属基板、（14）（44）……導電路、
（18）……外部リード用パッド、（22）（36）（52）
（54）……ボンディングワイア、（24）〜（32）……集
積回路素子、（34）……チップ抵抗、（40）……多層基
板、（42）……孔。FIG. 1 is a plan view of one embodiment of the present invention, FIG. 2 is a plan view of a multilayer substrate characteristic of the present invention, FIG. 3 is a cross-sectional view taken along line II of FIG. 1, and FIG. FIG. (12) ... insulated metal substrate, (14) (44) ... conductive path,
(18)… Pad for external lead, (22) (36) (52)
(54) bonding wire, (24) to (32) integrated circuit element, (34) chip resistor, (40) multilayer substrate, (42) hole.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 金子 正雄 大阪府守口市京阪本通２丁目18番地 三 洋電機株式会社内 (72)発明者 樫村 和之 群馬県山田郡大間々町大間々414―１ 東京アイシー株式会社内 (72)発明者 比賀 利明 群馬県山田郡大間々町大間々414―１ 東京アイシー株式会社内 (56)参考文献 特開 昭57−17157（ＪＰ，Ａ) 実開 昭62−92653（ＪＰ，Ｕ) ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masao Kaneko 2-18-18 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Kazuyuki Kashimura 414-1, Oma, Oma-machi, Yamada-gun, Gunma Tokyo Inside Icy Co., Ltd. (72) Inventor Toshiaki Higa 41-1, Oma Omachi, Yamada-gun, Gunma Prefecture Tokyo Icy Co., Ltd. (56) References JP-A-57-17157 (JP, A) JP-A-62-292653 ( JP, U)
Claims (1)
集積回路素子を固着するための導電パッド等の導電路が
絶縁樹脂層を介して設けられた金属基板、この金属基板
の少なくとも一周端辺領域に所定の実装領域を残して、
その上に積層される所望形状の導電路が設けられた絶縁
基板、前記絶縁基板は、前記金属基板を露出するための
孔または切り欠きを有し、前記露出領域に所定の前記集
積回路素子が実装され、少なくとも前記所定の集積回路
素子は前記絶縁基板上に形成された導電路と電気的に接
続され、 他の複数の前記集積回路素子は、積層された前記絶縁基
板の外周に設けられた前記実装領域に実装され、 前記所定の集積回路素子は、積層された前記絶縁基板を
介して前記他の複数の集積回路素子と電気的に接続され
た多層構造の混成集積回路装置において、 前記絶縁基板は接着剤が含浸された接着樹脂含浸シート
を介して前記金属基板上に選択的に積層されたことを特
徴とする混成集積回路装置。1. A metal substrate provided with at least a patterned wiring and a conductive path such as a conductive pad for fixing a plurality of integrated circuit elements via an insulating resin layer, and at least one peripheral edge region of the metal substrate. Leaving a predetermined mounting area
An insulating substrate provided with a conductive path of a desired shape laminated thereon, the insulating substrate has a hole or a notch for exposing the metal substrate, and the predetermined integrated circuit element is provided in the exposed region. Mounted, at least the predetermined integrated circuit element is electrically connected to a conductive path formed on the insulating substrate, and the plurality of other integrated circuit elements are provided on the outer periphery of the laminated insulating substrate. The hybrid integrated circuit device having a multilayer structure mounted on the mounting area, wherein the predetermined integrated circuit element is electrically connected to the plurality of other integrated circuit elements via the laminated insulating substrate. A hybrid integrated circuit device, wherein the substrate is selectively laminated on the metal substrate via an adhesive resin impregnated sheet impregnated with an adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2201220A JP2620650B2 (en) | 1990-07-31 | 1990-07-31 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2201220A JP2620650B2 (en) | 1990-07-31 | 1990-07-31 | Hybrid integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0487359A JPH0487359A (en) | 1992-03-19 |
| JP2620650B2 true JP2620650B2 (en) | 1997-06-18 |
Family
ID=16437334
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2201220A Expired - Fee Related JP2620650B2 (en) | 1990-07-31 | 1990-07-31 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2620650B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2801810B2 (en) * | 1992-04-14 | 1998-09-21 | 株式会社東芝 | Resin-sealed semiconductor device |
| JP3543676B2 (en) | 1999-06-02 | 2004-07-14 | セイコーエプソン株式会社 | Multi-chip mounting structure, method of manufacturing the mounting structure, electro-optical device and electronic apparatus |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09145845A (en) * | 1995-11-22 | 1997-06-06 | Canon Inc | Radiation detector and radiation detecting device |
| JP4097455B2 (en) * | 2001-06-25 | 2008-06-11 | 化成オプトニクス株式会社 | Gadolinium oxysulfide phosphor for digital radiography, radiation image conversion screen, and radiation image capturing apparatus |
| JP2003262672A (en) * | 2002-03-11 | 2003-09-19 | Canon Inc | Radiation detection apparatus and method for manufacturing the same |
| EP1489434A1 (en) * | 2002-03-28 | 2004-12-22 | Kabushiki Kaisha Toshiba | X-ray detector |
| JP2004239722A (en) * | 2003-02-05 | 2004-08-26 | Toshiba Corp | Radiation detector |
| JP4307127B2 (en) * | 2003-04-02 | 2009-08-05 | キヤノン株式会社 | Radiography equipment |
| JP2004317300A (en) * | 2003-04-16 | 2004-11-11 | Toshiba Corp | Plane radiation detector and its manufacturing method |
| JP2004340737A (en) * | 2003-05-15 | 2004-12-02 | Toshiba Corp | Radiation detector and its manufacturing method |
| DE102004056999A1 (en) * | 2004-11-25 | 2006-06-01 | Siemens Ag | Making scintillator layer for x-ray detector with spatial resolution, introduces fluorescing polymer mixture into pattern of holes and hardens it |
| JP5313632B2 (en) * | 2008-11-04 | 2013-10-09 | 富士フイルム株式会社 | Radiation image detector |
| JP2011007552A (en) * | 2009-06-24 | 2011-01-13 | Konica Minolta Medical & Graphic Inc | Scintillator panel, radiation detection device, and method of manufacturing the scintillator panel |
| JP5369979B2 (en) * | 2009-08-05 | 2013-12-18 | コニカミノルタ株式会社 | Radiation image detection device |
| JP2011257339A (en) * | 2010-06-11 | 2011-12-22 | Konica Minolta Medical & Graphic Inc | Radiation image detection device |
| KR101925823B1 (en) * | 2011-05-26 | 2018-12-06 | 도레이 카부시키가이샤 | Scintillator panel and method for manufacturing scintillator panel |
-
1990
- 1990-07-31 JP JP2201220A patent/JP2620650B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0487359A (en) | 1992-03-19 |
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