JP2615149B2 - IC chip mounting method - Google Patents
IC chip mounting methodInfo
- Publication number
- JP2615149B2 JP2615149B2 JP18931588A JP18931588A JP2615149B2 JP 2615149 B2 JP2615149 B2 JP 2615149B2 JP 18931588 A JP18931588 A JP 18931588A JP 18931588 A JP18931588 A JP 18931588A JP 2615149 B2 JP2615149 B2 JP 2615149B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- pattern
- substrate
- electrodes
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 「本発明の利用分野」 この発明は低コスト化を図るために、プリント基板、
硝子基板等の絶縁基板もしくは絶縁性表面を有する基板
上に電気配線を精密印刷する方法を用いたICチップの実
装方法。DETAILED DESCRIPTION OF THE INVENTION "Field of Application of the Present Invention" The present invention relates to a printed circuit board,
A method of mounting IC chips using a method of precision printing electrical wiring on an insulating substrate such as a glass substrate or a substrate having an insulating surface.
「従来の技術」 従来、プリント基板上に電気配線を形成するにはガラ
スエポキシ等の絶縁基板上に銅箔を貼り付け、公知であ
るフォトリソグラフィー工程を用いて、ウェットエッチ
ング法により電気配線を形成する手法がとられていた。"Prior art" Conventionally, to form electric wiring on a printed circuit board, a copper foil is pasted on an insulating substrate such as glass epoxy, and the electric wiring is formed by a wet etching method using a known photolithography process. Had to be taken.
またサーマルヘッド等の装置の場合においては絶縁体
であるセラミック基板上にAuを中心とする導電金属を基
板表面全体にイオンプレーティング法等により蒸着し、
プリント基板の場合と同様にフォトリソグラフィー法を
用いて、ウェットエッチング法により電気配線を形成す
る手法が採られていた。In the case of a device such as a thermal head, a conductive metal centering on Au is deposited on a ceramic substrate, which is an insulator, over the entire substrate surface by an ion plating method or the like,
As in the case of a printed circuit board, a method of forming an electric wiring by a wet etching method using a photolithography method has been adopted.
プリント基板等において、半導体素子の端子を入れる
穴と穴とのピン間隔は0.1インチ(2.45mm)で、この間
に3本以上の電気配線回路を描く高密度プリント配線板
のパターン形成はもっぱらフォトリソグラフィー法が用
いられていた。プリント配線板にドライフィルムを貼
り、この上に露光、現像という写真技術で配線パターン
を描いて、不要部分を溶剤で溶かしてパターンを形成す
る方法が採られてきた。On printed circuit boards, etc., the pin spacing between the holes for the terminals of the semiconductor element is 0.1 inch (2.45 mm), and the pattern formation on the high-density printed wiring board, in which three or more electrical wiring circuits are drawn, is exclusively formed by photolithography. Method was used. A method has been adopted in which a dry film is attached to a printed wiring board, a wiring pattern is drawn on the dry film by photographic techniques of exposure and development, and an unnecessary portion is dissolved with a solvent to form the pattern.
この方法に使用される銅箔およびドライフィルム、現
像液等の材料費が高価であるとともに、露光装置も高価
であるために、製造原価をあげる一因となっていた。The material cost of the copper foil, dry film, developer and the like used in this method is expensive, and the exposure apparatus is also expensive, which has contributed to increase the manufacturing cost.
さらにフォトリソグラフィー法は、その工程が複雑で
ありまた所要時間も相当必要であり、この方法自身がコ
スト高につながっていた。Furthermore, the photolithography method requires a complicated process and requires a considerable amount of time, and this method itself has led to high costs.
またサーマルヘッド、イメージセンサ、液晶表示装置
の電極パターン形成時においても同様にフォトリソグラ
フィー工程が用いられ、各々の装置の製造原価をあげて
いた。In addition, a photolithography process is also used when forming an electrode pattern for a thermal head, an image sensor, and a liquid crystal display device, which increases the manufacturing cost of each device.
かかる問題を解決するため、印刷法により直接基板上
に形成することで、従来法で必要であった配線のベース
となる銅箔、フォトレジスト、現像液等の材料費および
その工程にかかわる時間および人件費を省くことがで
き、コストの低減を行う方法が提案されている。In order to solve such a problem, by directly forming on a substrate by a printing method, a material cost of a copper foil, a photoresist, a developing solution and the like required as a wiring base and a time required for the process required in the conventional method and There have been proposed methods of reducing labor costs and reducing costs.
ガラス、ガラスエポキシ、セラミック等の絶縁基板上
または既に配線の設けられた基板上に絶縁層を形成した
その上に金属粉または合金属粉を含む導電性印刷用イン
クを印刷法により1〜20μm程度の膜厚を有するパター
ンの印刷を行うものである。An insulating layer is formed on an insulating substrate such as glass, glass epoxy, or ceramic, or a substrate on which wiring is already provided. A conductive printing ink containing metal powder or mixed metal powder is formed on the insulating layer by a printing method to about 1 to 20 μm. Is to print a pattern having a film thickness of
このような手法により基板上に直接描かれた回路上に
電子装置駆動用のICを実装するにはCOB(チップオンボ
ード)技術が知られており、このCOBにおいても従来はI
Cの電極パッドと基板上の回路の信号入出力部とを金属
細線を用いて1本づつ接続を行っていた。COB (chip-on-board) technology is known for mounting an IC for driving an electronic device on a circuit drawn directly on a substrate by such a method.
The C electrode pad and the signal input / output part of the circuit on the substrate were connected one by one using a thin metal wire.
しかし生産性及びコスト面などの要求よりICパッドに
バンプを設け基板上の回路の信号入出力部とを直接接触
させるフリップチップ法が開発されている。However, a flip chip method has been developed in which bumps are provided on IC pads to directly contact signal input / output portions of a circuit on a substrate due to demands such as productivity and cost.
この場合ICバンプと基板上の回路の信号入出力部との
接触が完全になされず、導通不良を起こし製品の歩留り
低下をおこすという問題が生じていた。In this case, the contact between the IC bumps and the signal input / output portion of the circuit on the substrate is not completely made, causing a problem that a conduction failure occurs and a product yield is reduced.
本願発明はその構成として基板上に直接印刷法等に描
かれた電極又はリード等による回路の少なくともICのバ
ンプと接触する部分に対し、プレス処理を施すことによ
り基板上の回路の信号入出力部の高さを揃えた後ICバン
プを基板上の回路の信号入出力部に接触させ電気的接続
を行うことにより前述の問題を解決し、製品の製造歩留
りを向上せしめ製品の製造コストを下げるという効果を
有するものであります。The invention of the present application has a structure in which a signal input / output portion of a circuit on a substrate is subjected to press processing at least on a portion of the circuit formed by electrodes or leads drawn directly on the substrate by a printing method or the like so as to contact the bump of the IC. After adjusting the height of the IC, the IC bump is brought into contact with the signal input / output part of the circuit on the board to make the electrical connection, thereby solving the above-mentioned problem, improving the product manufacturing yield and reducing the product manufacturing cost. It has an effect.
以下に実施例により本発明を説明する。 Hereinafter, the present invention will be described by way of examples.
「実施例」 導電性印刷インクとして市販されているポリマー型銅
ペーストを用いて絶縁性表面を有する基板上に所定の電
極又はリードのパターン(2)を公知のスクリーン印刷
法により印刷した。Example A predetermined electrode or lead pattern (2) was printed on a substrate having an insulating surface by a known screen printing method using a polymer type copper paste commercially available as a conductive printing ink.
本実施例にて使用したポリマー型銅ペーストは三井金
属鉱業製で商品名S−5000として市販されており5μm
程度の粒子径を有する銅粒子と、エポキシ樹脂と有機溶
剤とから構成されている。The polymer type copper paste used in this example is commercially available from Mitsui Mining & Smelting under the trade name S-5000 and has a thickness of 5 μm.
It is made up of copper particles having a particle size of the order, an epoxy resin and an organic solvent.
このような導電性印刷ペーストを200〜400メッシュの
スクリーンを用いて所定のパターン(2)に印刷する。
この場合印刷パターンの電極又はリードの巾は最小40μ
m最大100μm程度でありスクリーンメッシュの空いて
いる間隔が20〜40μmであり、当然印刷されたパターン
(2)にはメッシュに相当する高低差が存在する。Such a conductive printing paste is printed in a predetermined pattern (2) using a 200 to 400 mesh screen.
In this case, the width of the electrode or lead of the printed pattern should be at least 40μ.
m is about 100 μm at maximum, and the space between screen meshes is 20 to 40 μm. Naturally, the printed pattern (2) has a height difference corresponding to the mesh.
今、厚さ20μm巾40μmで100本の直線状の電極の印
刷を行った場合、最大の厚さ27μm最小の厚さ13μmで
あり、1本の電極間においても高低差が存在し複数本の
電極間においても高低差が存在していた。その様子を第
2図(a)に示す。Now, when printing 100 linear electrodes with a thickness of 20 μm and a width of 40 μm, the maximum thickness is 27 μm and the minimum thickness is 13 μm. There was also a height difference between the electrodes. This is shown in FIG.
このように約15μmも高低差の存在する電極パターン
に対してICチップを接触させて完全な導通を得ることは
当然ながら不可能であった。As described above, it is naturally impossible to bring the IC chip into contact with an electrode pattern having a height difference of about 15 μm to obtain perfect conduction.
そのため本実施ではまず第1図に示す電極又はリード
パターン(2)を絶縁性表面を有する基板(1)上に前
述の導電性ペーストを用いて印刷した。第1図はその一
部しか示されていないが80本の電極パターンを印刷し
た。この状態では前述の如く電極又はリードパターンは
高低差が存在し、例えば電極(33)の高さは15μmであ
り、電極(3)の高さは29μmで80本の電極の平均は1
9.5μmであった。Therefore, in this embodiment, first, the electrodes or lead patterns (2) shown in FIG. 1 were printed on the substrate (1) having an insulating surface by using the above-mentioned conductive paste. Although FIG. 1 shows only a part thereof, 80 electrode patterns were printed. In this state, the electrode or the lead pattern has a height difference as described above. For example, the height of the electrode (33) is 15 μm, the height of the electrode (3) is 29 μm, and the average of 80 electrodes is 1 μm.
It was 9.5 μm.
次にこの印刷したパターンに対し、予備の熱処理を行
う。すなわち導電性ペーストが完全に固形化しない程度
に熱を加え印刷されたパターン中に存在する有機溶剤の
一部を飛ばす処理を行った。実際には60℃で約5分の予
備の熱処理を行った。Next, preliminary heat treatment is performed on the printed pattern. That is, a process was performed in which heat was applied to such an extent that the conductive paste was not completely solidified to remove a part of the organic solvent present in the printed pattern. Actually, preliminary heat treatment was performed at 60 ° C. for about 5 minutes.
次にこの電極に対し、プレス処理を施した。本実施例
の場合ロールプレスを用いて面圧力20kg/cm2の圧力で、
この予備の熱処理が施された印刷パターンにプレス処理
を行った。この後180℃30分間の熱処理を施し電極パタ
ーンの完全固形化を行った。この時に電極(33)の高さ
は14μmとなり、電極(3)の高さは20μmとなって,8
0本の電極の平均の高さは18.0μmであった。プレス後
の電極パターンの様子を第2図(b)に示す。Next, the electrode was subjected to a press treatment. In the case of this embodiment, using a roll press at a surface pressure of 20 kg / cm 2 ,
Press processing was performed on the print pattern subjected to the preliminary heat treatment. Thereafter, heat treatment was performed at 180 ° C. for 30 minutes to completely solidify the electrode pattern. At this time, the height of the electrode (33) is 14 μm, and the height of the electrode (3) is 20 μm.
The average height of the zero electrodes was 18.0 μm. FIG. 2 (b) shows the state of the electrode pattern after pressing.
このプレス処理は基板(1)上に形成された電極パタ
ーンのうちのICチップのバンプと接触する部分だけでよ
いが電極パターン全体又はほぼ全体を行うとプレス処理
により形成されたパターン中に存在する銅粒子同志の接
触面積が増し、電極の導電性が向上するという別の特徴
を有する。This press processing may be performed only on the portion of the electrode pattern formed on the substrate (1) that is in contact with the bumps of the IC chip, but if the entire electrode pattern or almost the entire electrode pattern is performed, the electrode pattern is present in the pattern formed by the press processing. Another feature is that the contact area between the copper particles is increased, and the conductivity of the electrode is improved.
次にICチップ(5)のバンプ(6)と基板上のパター
ン(2)の信号入出力部との位置合わせを行い両者を接
触させる。Next, the bumps (6) of the IC chip (5) and the signal input / output portion of the pattern (2) on the substrate are aligned and brought into contact.
この時150℃程度に加熱しながら紫外光硬化接着剤
(4)をICチップ(5)に塗布し、紫外光を照射して接
着した後、加熱を中止してICチップの基板上への実装を
終了する。この時の様子を第3図に示す。At this time, apply an ultraviolet light curable adhesive (4) to the IC chip (5) while heating to about 150 ° C., irradiate the ultraviolet light and bond, then stop heating and mount the IC chip on the substrate. To end. The situation at this time is shown in FIG.
ICチップ(5)を基板上に接着する接着剤(4)は温
度変化に伴って体積膨張収縮を行う。本実施例では加熱
した状態すなわち体積が膨張した状態で硬化させたので
温度を下げて行っても接着剤は体積収縮しICチップ
(5)を基板に押しつける力が増すのみで、温度サイク
ル試験等に十分耐えるという特徴を持っている。The adhesive (4) for bonding the IC chip (5) to the substrate expands and contracts in volume with a change in temperature. In the present embodiment, the adhesive was cured in a heated state, that is, in a state where the volume was expanded. Therefore, even if the temperature was lowered, the adhesive contracted in volume and only increased the force pressing the IC chip (5) against the substrate. It has the characteristic that it can withstand enough.
比較のためにプレス処理を行わない印刷パターンにIC
チップを実装し、その電気的な接続の特性を調べた結果
を以下の表に示す。IC for print pattern without press processing for comparison
The results of mounting the chip and examining the electrical connection characteristics are shown in the table below.
このようにプレス処理が施された本発明方法はすべて
の接続部分が良導通性を示し、接続部の歩留りは100%
とすることができた。 In the method of the present invention thus subjected to the press treatment, all the connection parts show good conductivity, and the yield of the connection parts is 100%.
And could be.
本実施例ではプレス後の電極の高さの最高と最低の差
が6μmであった。本来この高低差0が最も良い結果を
示すと考えられるが本発明者らによると高低差が8μm
でも接続可能であることが判明している。In this embodiment, the difference between the highest and lowest electrode heights after pressing was 6 μm. Originally, it is considered that this height difference 0 shows the best result, but according to the present inventors, the height difference is 8 μm
But it turns out that it can be connected.
本発明方法により印刷法にて形成された電極パターン
の高さを揃えて形成することができ、ICチップの実装時
の不良導通箇所が全くなく完全な導通が得られた。According to the method of the present invention, the electrode patterns formed by the printing method can be formed to have the same height, and complete conduction can be obtained without any defective conduction portion when mounting the IC chip.
又、プレス処理により電極の抵抗値が下がるという特
徴も有する。Another feature is that the resistance value of the electrode is reduced by the press treatment.
第1図及び第2図は本発明方法による電極の印刷パター
ンを示す。 第3図はICチップ実装の様子を示す。 1……基板、5……ICチップ 2……電極パターン 4……接着剤1 and 2 show a printed pattern of an electrode according to the method of the present invention. FIG. 3 shows how the IC chip is mounted. 1 ... substrate 5 ... IC chip 2 ... electrode pattern 4 ... adhesive
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山崎 博史 京都府京都市右京区花園土堂町10番地 立石電機株式会社内 審査官 金 公彦 (56)参考文献 特開 平1−170079(JP,A) 特開 平2−10844(JP,A) ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hiroshi Yamazaki 10 examiner, Tateishi Electric Co., Ltd., Hanazono Todocho, Ukyo-ku, Kyoto-shi, Kyoto, Japan Examiner Kimikohiko Kim (56) JP-A-2-10844 (JP, A)
Claims (2)
有するペーストをスクリーン印刷法により電極又はリー
ドのパターンに印刷する工程と前記印刷パターンの少な
くともICチップと接触する部分に対しプレス処理を施し
高さを揃える工程と前記印刷パターンに対し熱処理を施
し電極又はリードを完成する工程と前記電極又はリード
の信号入出力部のパッドとICチップの信号入出力部のバ
ンプとを対抗させ電気的に接続させる工程とを有するこ
とを特徴とするICチップの実装方法。1. A step of printing a paste having conductive particles on a substrate having an insulating surface on a pattern of electrodes or leads by a screen printing method, and performing a pressing process on at least a portion of the printed pattern which is in contact with an IC chip. The step of making the applied height uniform, the step of performing a heat treatment on the printed pattern to complete the electrodes or leads, and the step of opposing the pads of the signal input / output sections of the electrodes or leads and the bumps of the signal input / output sections of the IC chip. Connecting the IC chip to the IC chip.
ターンの少なくともICチップと接触する部分に対しプレ
ス処理を施し電極又はリードの高さを揃える工程に先立
って前記印刷パターンに予備の熱処理を施すことを特徴
とするICチップの実装方法。2. A preliminary heat treatment is performed on the print pattern prior to the step of performing a press process on at least a portion of the print pattern that is in contact with the IC chip to adjust the height of the electrodes or leads according to claim 1. IC chip mounting method characterized by applying
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18931588A JP2615149B2 (en) | 1988-07-27 | 1988-07-27 | IC chip mounting method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18931588A JP2615149B2 (en) | 1988-07-27 | 1988-07-27 | IC chip mounting method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0237734A JPH0237734A (en) | 1990-02-07 |
JP2615149B2 true JP2615149B2 (en) | 1997-05-28 |
Family
ID=16239300
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18931588A Expired - Lifetime JP2615149B2 (en) | 1988-07-27 | 1988-07-27 | IC chip mounting method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2615149B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3194553B2 (en) * | 1993-08-13 | 2001-07-30 | 富士通株式会社 | Method for manufacturing semiconductor device |
JP4821424B2 (en) * | 2006-04-10 | 2011-11-24 | 株式会社村田製作所 | Ceramic multilayer substrate and manufacturing method thereof |
-
1988
- 1988-07-27 JP JP18931588A patent/JP2615149B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH0237734A (en) | 1990-02-07 |
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