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JP2696750B2 - Semiconductor element pattern formation method - Google Patents

Semiconductor element pattern formation method

Info

Publication number
JP2696750B2
JP2696750B2 JP7188985A JP18898595A JP2696750B2 JP 2696750 B2 JP2696750 B2 JP 2696750B2 JP 7188985 A JP7188985 A JP 7188985A JP 18898595 A JP18898595 A JP 18898595A JP 2696750 B2 JP2696750 B2 JP 2696750B2
Authority
JP
Japan
Prior art keywords
layer
photosensitive film
colloid
pattern
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7188985A
Other languages
Japanese (ja)
Other versions
JPH08172098A (en
Inventor
儁 黄
容 和 金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of JPH08172098A publication Critical patent/JPH08172098A/en
Application granted granted Critical
Publication of JP2696750B2 publication Critical patent/JP2696750B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/38Treatment before imagewise removal, e.g. prebaking

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は半導体素子のパター
ン形成方法に関し、特に反射の激しい下部層に微細のパ
ターンを形成するために、コロイド(Colloid) 及び金属
層をエッチング障壁(Etching Barrier) に用いて感光膜
(Photoresist) 及び導電層をエッチングすることによ
り、パターン幅の変化(Pattern Width Variation) を防
止することが出来るようにした半導体素子のパターン形
成方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a pattern of a semiconductor device, and more particularly to a method for forming a fine pattern on a highly reflective lower layer by using a colloid and a metal layer as an etching barrier. The photosensitive film
The present invention relates to a method of forming a pattern of a semiconductor device, which can prevent a change in pattern width (Pattern Width Variation) by etching (Photoresist) and a conductive layer.

【0002】[0002]

【従来の技術】従来、半導体素子のパターン形成方法
は、パターニングさせるための導電層又は絶縁層の上部
に感光膜を塗布し、マスクを用いて前記感光膜の所定部
分を露光させた後で現像して、感光膜のパターンを形成
させる。次いで、エッチング障壁として感光膜パターン
を用いて前記導電層又は絶縁層をエッチングする。
2. Description of the Related Art Conventionally, a method for forming a pattern of a semiconductor device is to apply a photosensitive film on a conductive layer or an insulating layer for patterning, expose a predetermined portion of the photosensitive film using a mask, and develop the photosensitive film. Thus, a pattern of the photosensitive film is formed. Next, the conductive layer or the insulating layer is etched using a photosensitive film pattern as an etching barrier.

【0003】[0003]

【発明が解決しようとする課題】しかし、露光の時、下
部層である導電層及び絶縁層の反射率が高くなる場合に
は、強い露光エネルギー(Energy)による乱反射等に基づ
いて前記感光膜パターンのサイズ変化が発生し、これに
よって形成されるパターンのサイズも変化する。さら
に、半導体素子が高集積化されることによって上述のよ
うな問題点に基づいて微細パターンの形成は一層難しく
なる。
However, when the reflectivity of the lower conductive layer and the insulating layer increases during exposure, the pattern of the photosensitive film is determined based on irregular reflection due to strong exposure energy. And the size of the pattern formed thereby also changes. Further, as the semiconductor element is highly integrated, it becomes more difficult to form a fine pattern based on the above-mentioned problems.

【0004】したがって、本発明は反射(Reflection)の
激しい下部層に微細のパターンを形成するためにコロイ
ド(Colloid) 及び金属層をエッチング障壁(Etching Bar
rier) に用いて感光膜及び導電層をエッチングすること
により、上述の問題点を解消することが出来る半導体素
子のパターン形成方法を提供することを目的とする。
Accordingly, the present invention provides a method of forming a colloid and a metal layer on an etching barrier to form a fine pattern on a lower reflection layer.
An object of the present invention is to provide a method for forming a pattern of a semiconductor device, which can solve the above-mentioned problems by etching a photosensitive film and a conductive layer by using the film as a carrier.

【0005】[0005]

【課題を解決するための手段】このような目的を達成す
るための本発明のパターン形成方法は基板上に形成され
る導電層又は絶縁層を、素子で要求されるパターンに形
成するために、その上部に感光膜を塗布した後、マスク
により露出された前記感光膜の表面に薄い露光領域を形
成させる段階と、前記露光領域が形成された全体構造上
部にコロイド層を形成させた後、現像液を用いて前記露
光領域の上部のコロイド及び露光領域を除去させる段階
と、残りの前記コロイドの上部にのみ選択的に金属層を
形成させ、この金属層をエッチング障壁として用いて前
記感光膜及び導電層又は絶縁層を除去させる段階と、前
記金属層、コロイド及び感光膜を順次的に除去させる段
階からなることを特徴とする。
In order to achieve the above object, a pattern forming method of the present invention is to form a conductive layer or an insulating layer formed on a substrate into a pattern required by an element. Forming a thin exposure region on the surface of the photosensitive film exposed by the mask after applying a photosensitive film on the upper surface, and forming a colloid layer on the entire structure on which the exposure region is formed, and then developing. Removing the colloid and the exposed region above the exposed region using a liquid, selectively forming a metal layer only on the remaining colloid, and using the metal layer as an etching barrier to form the photosensitive film and the photosensitive layer. The method comprises the steps of: removing a conductive layer or an insulating layer; and sequentially removing the metal layer, the colloid, and the photosensitive film.

【0006】[0006]

【発明の実施の形態】以下、添付された図面によって本
発明を詳細に説明すると、次のようである。図1(A)
ないし図1(E)は、本発明による半導体素子のパター
ン形成方法を説明するための断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 (A)
FIG. 1E is a cross-sectional view illustrating a method for forming a pattern of a semiconductor device according to the present invention.

【0007】図1(A)は、導電層又は絶縁層2が形成
された所定の基板1上に感光膜3を塗布した後、選択さ
れた位置にマスク4を在置させ、低い露光エネルギーを
用いて露光させる状態の断面図である。下部層を平坦化
するために使用される前記感光膜3は、形成用として例
えば1乃至2μmほどの厚さに形成される。露光の時、
前記感光膜3は低い露光エネルギーにより、ほとんど表
面(表面から0.5 μm程の厚さ以内)だけが露光される
ようにする。
FIG. 1A shows that after a photosensitive film 3 is applied on a predetermined substrate 1 on which a conductive layer or an insulating layer 2 is formed, a mask 4 is placed at a selected position, and a low exposure energy is applied. FIG. 6 is a cross-sectional view of a state where the exposure is performed using the light emitting device. The photosensitive film 3 used for flattening the lower layer is formed, for example, to a thickness of about 1 to 2 μm. At the time of exposure,
The photosensitive film 3 is exposed only at its surface (within a thickness of about 0.5 μm from the surface) by low exposure energy.

【0008】図1(B)は、露出された感光膜3の表面
に露光領域が形成された状態で全ての上部面にコロイド
層5を形成させた状態の断面図である。前記コロイド層
5は、コロイダル(Colloidal) のPd/Sn触媒剤(Cat
alyst)を用いて気相蒸着(Vapor deposition)方法で形成
される。
FIG. 1B is a cross-sectional view showing a state in which a colloid layer 5 is formed on all upper surfaces in a state where an exposed region is formed on the exposed surface of the photosensitive film 3. The colloid layer 5 is formed of a colloidal Pd / Sn catalyst (Cat
alyst) using a vapor deposition method.

【0009】図1(C)においては、現像液を用いて前
記露光領域6及びその上部のコロイド5が除去される。
即ち、現像液は露光領域に染み込んで前記露光領域6を
除去させるとともに、前記露光領域6の上部のコロイド
5を除去させる。その後、無電解鍍金液槽(Electroless
plating bath)にディッピング(Dipping) して残りの前
記コロイド5の上部にのみ選択的に金属層が形成され
る。
In FIG. 1C, the exposed area 6 and the colloid 5 thereon are removed using a developing solution.
That is, the developer penetrates into the exposed area to remove the exposed area 6 and remove the colloid 5 above the exposed area 6. After that, electroless plating solution tank (Electroless
The metal layer is selectively formed only on the remaining colloid 5 by dipping in a plating bath.

【0010】図1(D)は、エッチング障壁として前記
金属層7を用いて前記感光膜3をプラズマエッチング(P
lasma Etching)方法で除去した状態である。その後、露
出した前記導電層又は絶縁層2もプラズマエッチング方
法により除去し、前記金属層7、コロイド層5及び感光
膜3を順次的に除去すると、図1(E)のように前記導
電層又は絶縁層2がパターニングされる。
FIG. 1D shows that the photosensitive film 3 is plasma-etched (P) using the metal layer 7 as an etching barrier.
(laser etching) method. Thereafter, the exposed conductive layer or insulating layer 2 is also removed by a plasma etching method, and the metal layer 7, the colloid layer 5 and the photosensitive film 3 are sequentially removed. As shown in FIG. The insulating layer 2 is patterned.

【0011】前記金属層7、コロイド層5は、ディッピ
ング及び気相蒸着方法のいずれを使っても、前記基板1
の背面に残り滓(カス)が存在する場合があるので、希
窒酸(Nitric acid) で除去するのが望ましい。
The metal layer 7 and the colloid layer 5 can be formed on the substrate 1 by any of dipping and vapor deposition methods.
It is desirable to remove with a dilute nitric acid (Nitric acid) since residue may be present on the back surface of the metal.

【0012】[0012]

【発明の効果】以上述べたように、本発明によれば、露
光されない部分の感光膜上部にのみ残留されるコロイド
と、そのコロイドの上部にのみ選択的に形成される金属
層をエッチング障壁として用いて感光膜を除去し、次い
で導電層又は絶縁層をパターニングすることにより、下
部層が導電層である場合にもノッチング(Notching)及び
ネッキング(Necking) の現状が防止され、パターン幅の
変化が発生しない優れた効果がある。
As described above, according to the present invention, a colloid remaining only on an unexposed portion of a photosensitive film and a metal layer selectively formed only on the colloid are used as an etching barrier. By removing the photosensitive film and then patterning the conductive layer or the insulating layer, the current state of Notching and Necking is prevented even when the lower layer is a conductive layer, and a change in the pattern width is prevented. There is an excellent effect that does not occur.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明による半導体素子のパターン形成方法を
説明するための断面図である。
FIG. 1 is a cross-sectional view illustrating a method for forming a pattern of a semiconductor device according to the present invention.

【符号の説明】[Explanation of symbols]

1…基板、2…導電層又は絶縁層、3…感光膜、4…マ
スク、5…コロイド層、6…露光領域、7…金属層
DESCRIPTION OF SYMBOLS 1 ... Substrate, 2 ... Conductive layer or insulating layer, 3 ... Photosensitive film, 4 ... Mask, 5 ... Colloid layer, 6 ... Exposure area, 7 ... Metal layer

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体素子のパターン形成方法において、 基板上に形成される導電層又は絶縁層を、素子で要求さ
れるパターンに形成するために、その上部に感光膜を塗
布した後、マスクにより露出された前記感光膜の表面に
薄い露光領域を形成させる段階と、 前記露光領域が形成された全体構造上部にコロイド層を
形成させた後、現像液を用いて前記露光領域の上部のコ
ロイド及び露光領域を除去させる段階と、 残りの前記コロイドの上部にのみ選択的に金属層を形成
させ、この金属層をエッチング障壁として用いて前記感
光膜及び導電層又は絶縁層を除去させる段階と、 前記金属層、コロイド及び感光膜を順次的に除去させる
段階からなることを特徴とする半導体素子のパターン形
成方法。
In a method of forming a pattern of a semiconductor device, a photosensitive film is applied on a conductive layer or an insulating layer formed on a substrate to form a pattern required by the device, and then a mask is formed thereon by a mask. Forming a thin exposure area on the exposed surface of the photosensitive film; forming a colloid layer on the entire structure having the exposure area formed thereon; Removing the exposed area; selectively forming a metal layer only on the remaining colloid; removing the photosensitive film and the conductive layer or the insulating layer using the metal layer as an etching barrier; A method for forming a pattern of a semiconductor device, comprising: sequentially removing a metal layer, a colloid, and a photosensitive film.
【請求項2】前記露光領域は、前記感光膜の表面部位か
ら0.3 乃至0.5 μmほどの深みに形成されることを特徴
とする請求項1に記載の半導体素子のパターン形成方
法。
2. The method according to claim 1, wherein the exposure region is formed at a depth of about 0.3 to 0.5 μm from a surface portion of the photosensitive film.
【請求項3】前記コロイド層は、コロイダルのPd/S
n触媒材を用いた気相蒸着方法によって形成されること
を特徴とする請求項1に記載の半導体素子のパターン形
成方法。
3. The colloid layer is a colloidal Pd / S
2. The method according to claim 1, wherein the pattern is formed by a vapor deposition method using an n-catalyst material.
【請求項4】前記金属層は、無電解鍍金液槽を用いたデ
ィッピングによって形成されることを特徴とする請求項
1に記載の半導体素子のパターン形成方法。
4. The method according to claim 1, wherein the metal layer is formed by dipping using an electroless plating bath.
JP7188985A 1994-07-28 1995-07-25 Semiconductor element pattern formation method Expired - Fee Related JP2696750B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR94-18404 1994-07-28
KR1019940018404A KR0148610B1 (en) 1994-07-28 1994-07-28 Patterning method for semiconductor device

Publications (2)

Publication Number Publication Date
JPH08172098A JPH08172098A (en) 1996-07-02
JP2696750B2 true JP2696750B2 (en) 1998-01-14

Family

ID=19389106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7188985A Expired - Fee Related JP2696750B2 (en) 1994-07-28 1995-07-25 Semiconductor element pattern formation method

Country Status (4)

Country Link
JP (1) JP2696750B2 (en)
KR (1) KR0148610B1 (en)
CN (1) CN1124406A (en)
GB (1) GB2291977A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200425327A (en) 2003-02-21 2004-11-16 Matsushita Electric Ind Co Ltd Method and apparatus for liquid etching
JP2005077955A (en) * 2003-09-02 2005-03-24 Sanyo Electric Co Ltd Etching method and method for manufacturing circuit device by using same
JP4519512B2 (en) * 2004-04-28 2010-08-04 株式会社半導体エネルギー研究所 Manufacturing method and removal method of semiconductor device
TW200619866A (en) * 2004-10-13 2006-06-16 Nikon Corp Aligner, exposing method, and device manufacturing method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5053318A (en) * 1989-05-18 1991-10-01 Shipley Company Inc. Plasma processing with metal mask integration

Also Published As

Publication number Publication date
JPH08172098A (en) 1996-07-02
GB2291977A (en) 1996-02-07
KR0148610B1 (en) 1998-12-01
CN1124406A (en) 1996-06-12
GB9515148D0 (en) 1995-09-20

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