JP2692850B2 - Multipoint synchronizer - Google Patents

Description

TECHNICAL FIELD The present invention relates to a multipoint synchronizing device used in a laser recording device, a laser reading device, or the like.

(Prior Art) Conventionally, a multi-point synchronizer detects a steering beam at a plurality of points in a one-line scanning area to generate a reference pulse, and inputs this reference pulse to a phase synchronization system composed of a PLL (Phase Locked Loop) circuit. To generate the image clock.

FIG. 3 shows an optical system in an example of the multipoint synchronizer.
The scanning laser beam emitted from the scanning semiconductor laser 11 is deflected by the rotating polygon mirror 12, passes through the fθ lens 13, and then is reflected by the mirror 14 to scan on the photoconductor 15. Further, the reference pulse generating laser beam emitted from the reference pulse generating semiconductor laser 16 is incident on the rotary polygon mirror 12 at a certain interval from the scanning laser beam, is deflected, passes through the fθ lens 13, and is then exposed. A grating 17 arranged at a position equivalent to the body 15 is scanned. The grating 17 has bright portions and dark portions alternately arranged in the scanning direction, and is also called a slit plate, a grit, or a scale. The laser beam transmitted through the bright portion of the grating 17 is passed through the lens array 18 to a plurality of light receiving elements 19a.
It is condensed to ~ 19e and photoelectrically converted to obtain a reference pulse. Here, the grating 17 is, for example, an image area (photoreceptor 15
Bright areas and dark areas are alternately arranged in a region corresponding to the upper image writing region), and a reference pulse is generated each time the laser beam scans the image region. The reference pulses from the light receiving elements 19a to 19e are added by a circuit (not shown) and input as one pulse train to a phase-locked system composed of a PLL circuit, and this phase-locked system outputs an image clock in synchronization with the reference pulse. The logic circuit generates a video signal for one pixel each time one of the pixel clocks is input, and the laser drive modulation circuit uses the video signal to scan the semiconductor laser 11 for scanning.
To modulate. The photoconductor 15 is scanned by the movement in the sub-scanning direction and the deflection of the laser beam in the main scanning direction by the rotary polygon mirror 12, and a video signal is written.

However, in this multipoint synchronizer, the reference pulse Pr input to the PLL circuit is intermittently generated in the image area and the non-image area as shown in FIG. Therefore, in the non-image area, the output frequency of the PLL circuit becomes the free-running frequency of the voltage-controlled oscillator in the PLL circuit, and the PLL circuit waits until the oscillation frequency of the voltage-controlled oscillator stabilizes even if the reference pulse Pr is input in the image area ( Plunge time) tp was needed.

Therefore, a multipoint synchronizing apparatus has been considered in which the grating 17 is configured so that the reference pulse Pr from the light receiving elements 19a to 19e is generated before the start of scanning the image area for a time corresponding to the pull-in time tp. But with this multipoint synchronizer
Since the pull-in time tp changes as the oscillation frequency of the voltage-controlled oscillator in the PLL circuit changes due to temperature changes, even if the PLL circuit reaches the scanning of the image area, it may not lock to the reference pulse Pr, resulting in a good written image. You won't get it. Also, grating 17 is pull-in time tp
And the device becomes larger.

In the PLL circuit, a constant voltage is forcibly applied to the low-pass filter when the PLL circuit is asynchronous so that the oscillation frequency of the voltage controlled oscillator approaches the frequency of the input signal.
It is known from Japanese Patent Laid-Open No. 62-3528, and it is conceivable to use this PLL circuit in the multipoint synchronization device. However, in such a multi-point synchronizer, the voltage is vulnerable to temperature changes, so it is easily affected by temperature changes, and the voltage applied to the low-pass filter becomes discontinuous between the image region and the non-image region, resulting in a voltage-controlled oscillator. The instability of the oscillation frequency causes the pixel clock frequency to become unstable.

(Object) It is an object of the present invention to provide a multi-point synchronization device that can improve the above-mentioned drawbacks, obtain a stable pixel clock, and prevent the device from becoming large.

(Structure) The invention according to claim 1 generates a pixel clock in synchronism with a grating scanned by a scanning beam, a light detecting means for detecting a beam transmitted through the grating, and a reference pulse from the light detecting means. A multi-point synchronizer having a phase-locking system for generating a pseudo-pulse generating unit that generates a pseudo-pulse having the same frequency as the reference pulse in a non-image area and outputs the pseudo-pulse to the phase-locking system. In the invention described in 2, the grating scanned by the scanning beam from the rotary polygon mirror, the light detection means for detecting the beam transmitted through the grating, and the pixel clock generated in synchronization with the reference pulse from the light detection means. In the multipoint synchronization device having a phase-locking system for generating a pseudo pulse having the same frequency as the reference pulse in the non-image area, A pseudo pulse generating means for outputting a synchronous,
With respect to the pseudo pulse generating means, the generation timing of the pseudo pulse is changed in accordance with the division angle error of the rotary polygon mirror so that the phase of the pulse at the starting end of the reference pulse and the phase of the pseudo pulse match. And means for varying the scanning time.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a circuit portion in one embodiment of the present invention, and FIG. 2 shows its operation timing. In this embodiment, the optical system is the same as that shown in FIG. 3, and the light receiving elements 19a to 19e are provided.
The output signal of is added by the circuit not shown and the reference pulse Pr
Is input only when scanning the image area. In this embodiment, a pseudo pulse Pr 'having the same frequency as that of the reference pulse Pr is generated in a non-image area and input to a phase locked system composed of a PLL circuit. As shown in FIG. It occurs in the entire image area. In this case, the relationship between the scanning cycle T and the cycle t ₁ of the reference pulse Pr is T = n · t ₁ , and n (= n ₁ + n ₂ ) where n ₁ and n ₂ are integers. The period t ₂ of the pseudo pulse Pr ′ is t ₂ = t ₁ .

The reference pulse Pr obtained by adding the output signals of the light receiving elements 19a to 19e in a circuit (not shown) is supplied to the PLL via the OR circuit 27.
The signal is output to the phase-locked loop composed of a circuit, inverted by the inverter 20 and input to the counter 21, and the counter 21 counts n ₁ − at the first rising edge of the output pulse ▲ ▼.
2 is loaded and the counting of the input pulse ▲ ▼ is started from the second rising γ _{2 of the} input pulse ▲ ▼. When the counter 21 counts n ₁ -2, it generates an output signal to invert the flip-flop 22 and sends the output signal to the load terminal of the counter 23 via the inverter 34. The counter 23 outputs the output signal of the flip-flop 22. , 24 becomes ready. The counter 23 counts the clock from the oscillator 25 having a sufficient resolution for the reference pulse Pr and outputs the signal P ₃ every t _1/2 . This signal P ₃ is divided by 2 by the flip-flop 26,
The output signal P _{4 of} 26 is input as a pseudo pulse Pr ′ through the OR circuit 27 to the phase synchronization system composed of the PLL circuit. The output signal P ₄ of the flip-flop 26 is inverted by the inverter 28 and counted by the counter 24. The counter 24 counts n ₂ output signals of the inverter 28 and outputs the output signals.
The flip-flop 22 is inverted by the output signal P ₆ of the flip-flop 29 by outputting P ₅ to invert the flip-flop 29.
Is cleared. By clearing this flip-flop 22, the counter 23 is disabled and the counter 24
Is cleared, and the flip-flops 26 and 29 are cleared. When the flip-flop 29 is cleared, the flip-flop 22 becomes ready for the output signal of the counter 21. The reference pulse Pr of the timer 30 is the inverter 2
It is input via 0, 31 and is triggered by this input pulse to clear the counter 21 in the non-image area. A resistor 32 and a capacitor 33 are externally attached to the timer 30, and the width τ of the output pulse P ₁ is set so that t ₁ <τ <t ₀ −t ₁ . Here, t ₀ is the time interval for scanning the image type as shown in FIG. 5, that is, the pseudo pulse Pr ′ generation time corresponding to the non-image area. Therefore, regardless of the image area or the non-image area, the pulse of the cycle t ₁ is continuously input from the OR circuit 27 to the PLL circuit, and the PLL circuit generates the pixel clock in synchronization with the input pulse and outputs it to the logic circuit. To do. Therefore, the pull-in time required for the PLL circuit to lock to the input pulse is only when the power is turned on.
Once the circuit locks to the input pulse, a stable pixel clock is obtained from the PLL circuit over the entire image area, and the grating 17 need only be the length of the image area.

 Next, another embodiment of the present invention will be described.

In the multi-point synchronizer described above, in the disconnection state (non-image area) of the reference pulse Pr, as shown in FIG. 6, the difference in scanning time t ₃₁ , t _32, ... Is large due to the division angle error of the rotary polygon mirror 12. It may occur at (≈T / 2). At this time, as shown in FIG. 7, when the pseudo pulse Pr 'is generated for a certain period of time after the end of the reference pulse Pr and is input to the PLL circuit, the pseudo pulse Pr'
Is due to the phase shift Δt of the reference pulse Pr due to the division angle error of the rotary polygon mirror 12, and at the generation point A of the reference pulse Pr, the start point B of the next reference pulse Pr even if the phase matches the reference pulse Pr.
Then, the phase may be inverted from the reference pulse Pr,
There is a risk that not only the output of the voltage controlled oscillator in the PLL circuit, that is, the pixel clock becomes unstable, but also the PLL circuit is unlocked. Therefore, in another embodiment of the present invention, by changing the generation timing of the pseudo pulse Pr ', the phases of the reference pulse Pr and the pseudo pulse Pr' are matched to obtain a stable pixel clock. The scanning times t ₃₁ , t _32, ... t ₃ m (m is the number of surfaces of the rotary polygon mirror 12) in the non-image area can be easily obtained in advance. Now, assuming that t ₃₁ is the shortest, the pseudo pulse Pr ′ is generated so as to match the phase of the reference pulse Pr after the end (A ₀ ) of the reference pulse Pr as shown in FIG. End of reference pulse Pr (A ₀ )
After that, the timing of generation of this pseudo pulse Pr ′ is
Assuming that t ₃₀ is scheduled, if the pseudo pulse Pr ′ is generated with a delay of Δt _N −t ₃₁ ( _N is 2 to m) time from t ₃₀ , the reference point Pr at the generation point B ₀ of the next reference pulse Pr It will be in phase with the pulse Pr.

FIG. 9 shows a circuit diagram of this embodiment, and FIG. 10 shows its operation. In this embodiment, the optical system is the same as that shown in FIG. 3, and the output signals of the light receiving elements 19a to 19e are added by a circuit (not shown) and input to the OR circuit 35 as a reference pulse Pr only when scanning the image area. To be done. Polygon surface detection sensor 36
Detects the scanning surface of the rotary polygon mirror 12 by detecting the reflected light from the marker provided on the surface of the rotary polygon mirror 12. The pseudo pulse (Pr ') generation timing circuit 37 determines the delay amount of the pseudo pulse Pr' generation from the detection signal of the polygon surface detection sensor 36, and the pseudo pulse (Pr ') generation circuit 38 outputs t.
_By generating the pseudo pulse Pr ′ from ₃₀ with a delay amount obtained by the pseudo pulse (Pr ′) generation timing circuit 37, the pseudo pulse Pr ′ is generated so as to be in phase with the reference pulse Pr as described above, that is, As shown in FIG. 8, the generation timing of the pseudo pulse Pr ′ is set to Δt based on the scheduled generation timings t ₃₀ , t ₃₁ ... That the phases of the pulse at the start end of the reference pulse Pr and the pseudo pulse Pr ′ match. _N (Δt ₂ , Δt ₃
..) to generate a pseudo pulse Pr ′, which is sent to the OR circuit 35. The PLL circuit generates a pixel clock in synchronization with the pulse from the OR circuit 35 and outputs it to the logic circuit. Since t ₃₁ , t _32, ... T ₃ m are constant, once they are detected by the polygon surface detection sensor 36, they may be used repeatedly. By generating the pseudo pulse Pr ′ in this way,
The input pulse of the PLL circuit may become discontinuous after the end of the reference pulse Pr and the pixel clock may become unstable. However, the input pulse of the PLL circuit at the start end of the reference pulse Pr (at the start of writing) is in the non-image area. Since it is continuous from, the pixel clock becomes stable in the image area as shown in FIG. 10 and a good written image can be obtained.

(Effect) As described above, according to the invention described in claim 1, the grating is scanned by the scanning beam, the light detecting means for detecting the beam transmitted through the grating, and the reference pulse from the light detecting means are synchronized. A multipoint synchronizing apparatus having a phase-locking system for generating a pixel clock is provided with a pseudo-pulse generating means for generating a pseudo-pulse having the same frequency as the reference pulse in a non-image area and outputting the pseudo-pulse to the phase-locking system. So you can get a stable pixel clock,
Moreover, it is not necessary to increase the size of the grating by the amount corresponding to the pull-in time, and it is possible to prevent the device from becoming large.

According to the second aspect of the invention, the grating is scanned by the scanning beam from the rotary polygon mirror, the light detecting means for detecting the beam transmitted through the grating, and the reference pulse from the light detecting means are synchronized. In a multi-point synchronizing device having a phase-locking system for generating a pixel clock, a pseudo-pulse generating means for generating a pseudo-pulse having the same frequency as the reference pulse in a non-image area and outputting the pseudo-pulse to the phase-locking system. Scanning of a non-image area in which the generation timing of the pseudo pulse with respect to the pseudo pulse generation means is changed by the division angle error of the rotary polygon mirror so that the phase of the pulse at the starting end of the reference pulse matches the phase of the pseudo pulse Since the means for changing the scanning time in the non-image area changes due to the division angle error of the rotary polygon mirror, the pixel clock can be changed according to the time. In good writing image becomes that stable is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit portion of one embodiment of the present invention,
FIG. 2 is a timing chart showing the operation of the same embodiment, FIG. 3 is a perspective view showing an optical system of an example of a multipoint synchronizing device, and FIG.
FIG. 5 is a waveform diagram for explaining a conventional multipoint synchronizer,
FIG. 6 is a waveform diagram for explaining the above embodiment, FIGS. 6 and 7 are waveform diagrams for explaining a conventional multipoint synchronizing apparatus, and FIG. 8 is a diagram for explaining another embodiment of the present invention. 9 is a block diagram showing the circuit portion of the same embodiment, and FIG. 10 is a timing chart showing the operation of the same embodiment. 17 …… Grating, 18,19a to 19e …… Light detection means, 2
0 ~ 26, 28 ~ 34, 36 ~ 38 ... Pseudo pulse generating means.

Claims (2)

(57) [Claims] 1. A grating which is scanned by a scanning beam, a light detecting means which detects a beam transmitted through the grating, and a phase synchronization system which generates a pixel clock in synchronization with a reference pulse from the light detecting means. The multipoint synchronizing apparatus having the above-mentioned multipoint synchronizing apparatus, comprising pseudo pulse generating means for generating a pseudo pulse having the same frequency as the reference pulse in a non-image area and outputting the pseudo pulse to the phase synchronization system. 2. A grating scanned by a scanning beam from a rotary polygon mirror, a light detecting means for detecting a beam transmitted through the grating, and a pixel clock in synchronization with a reference pulse from the light detecting means. In a multipoint synchronizer having a phase-locking system, a pseudo-pulse generating means for generating a pseudo-pulse having the same frequency as the reference pulse in a non-image area and outputting the pseudo-pulse to the phase-locking system, and the pseudo-pulse generating means. Means for varying the generation timing of the pseudo pulse according to the scanning time of the non-image area that changes due to the division angle error of the rotary polygon mirror so that the phase of the pulse at the starting end of the reference pulse and the phase of the pseudo pulse match. And a multipoint synchronization device.