JP2685609B2 - Display device drive circuit - Google Patents

Description

The present invention relates to a plurality of parallel signal electrodes, a plurality of scanning electrodes intersecting with the signal electrodes, and a vicinity of each intersection of the signal electrodes and the scanning electrodes. For driving a display unit having a pixel electrode provided, a counter electrode provided so as to face the pixel electrode, and an auxiliary capacitance electrode for forming a capacitance with the pixel electrode, The present invention relates to a drive circuit of a display device. A matrix type liquid crystal display device will be described below as an example of a display device, but the present invention is not limited to the display device of another type, for example, an EL device.
It is also applicable to a drive circuit of an (electroluminescence) display device, a plasma display, or the like.

(Prior Art) FIG. 9 schematically shows an example of a conventional matrix type liquid crystal display device. The matrix type liquid crystal display device of FIG. 9 has a TFT (Thin Film Transistor) 1 as a switching element for driving the pixel electrodes 103 arranged in a matrix.
A TFT liquid crystal panel 100 using 04 is provided. The TFT liquid crystal panel 100 includes a plurality of scanning electrodes 101 arranged in parallel with each other.
And a plurality of signal electrodes 102 arranged orthogonal to the scanning electrodes 101 and parallel to each other. A TFT 104 for driving the pixel electrode 103 is provided near each intersection of the scanning electrode 101 and the signal electrode 102. A counter electrode 105 is provided so as to face the pixel electrode 103. The counter electrode 105 is shown schematically in FIG. 9, but normally all the pixel electrodes 10
The counter electrode 105 is one conductive layer commonly disposed in
A constant voltage V _c is applied to. The TFT liquid crystal panel 100 further has an auxiliary capacitance electrode 106. Auxiliary capacitance electrode 106
Will be described later.

The TFT liquid crystal panel 100 is driven by a driving circuit including a source driver 200 and a gate driver 300. The source driver 200 and the gate driver 300 are connected to the signal electrode 102 and the scan electrode 101 of the TFT panel 100, respectively.
The source driver 200 samples and holds the input analog image signal or video signal, and supplies the sampled and held signal to the signal electrode 102. On the other hand, the gate driver 300 sequentially outputs scan pulses to the scan electrodes 101. Control signals such as timing signals input to the gate driver 300 and the source driver 200 are given from the control circuit 400.

The source driver 200 will be described in detail with reference to FIG. The source driver 200 includes a shift register 210,
A sample hold circuit 220 and an output buffer 230 are provided. In the shift register 210, a shift pulse input from the control circuit 400 is shifted according Shikutokurokku, line _{B 1, B 2, ...,} B i, ..., sequentially sampling pulses B _m is output. Analog switch ASW1 of sample and hold circuit 220 by sampling pulse
, (1), ..., ASW1 (i), ..., ASW1 (m) sequentially become conductive, and the sampling capacitor 221 is sequentially charged to the instantaneous amplitude v (i, j) of the input analog image signal. Here, v (i, j) is a pixel electrode corresponding to the intersection of the i-th signal electrode and the j-th scanning electrode of the TFT panel 100.
It is the instantaneous amplitude of the analog image signal to be written to 103. In this way, after the image signal for one horizontal scanning period is sampled by the sample hold circuit 220,
The output pulse OE is input, and the image signal is transferred from the sampling capacitor 221 to the hold capacitor 222. The image signal held by the hold capacitor 222 is output to the signal electrode 102 via the output buffer 230.

FIG. 11 shows an outline of input / output signal waveforms in the source driver 200. In FIG. 11, v (C _SPL (i)),
v (C _H (i)) and v _S (i) are the voltage of the i-th sampling capacitor 221 and the i-th holding capacitor 222.
And the output voltage of the i-th output buffer 230 are shown. As seen in FIG. 11, the signal electrode 10
2 is usually AC driven so that the level of the applied voltage with respect to the voltage v _c of the counter electrode 105 is different between adjacent fields.

Figure 12 shows the equivalent circuit of picture elements. As shown in FIG. 12, in addition to the picture element capacitance C _LC formed between the picture element electrode 103 and the counter electrode 105, the auxiliary capacitance formed between the picture element electrode 103 and the auxiliary capacitance electrode 106. C _S is provided. In the TFT liquid crystal panel 100, even if the signal electrode 102 is AC-driven, the AC applied waveform to the liquid crystal element still has asymmetry, and due to this asymmetry, a polarization electric field is formed in the liquid crystal element, which deteriorates the liquid crystal element. Etc. will result in a decrease in reliability. The auxiliary capacitor C _S is attached for the purpose of improving such problems and reducing the flicker phenomenon. The pixel electrode 103 also serves as one electrode of the auxiliary capacitance C _S. The following two types of methods are known as connection methods for the other electrode, that is, the auxiliary capacitance electrode 106.

In the first method, as shown in FIG. 9, the auxiliary capacitance electrode 106 corresponding to the jth scan electrode 101 is adjacent to the jth scan electrode 101.
-It is electrically connected to the i-th scan electrode 101. However,
The auxiliary capacitance electrode 106 corresponding to the j = 0th scan electrode 101
Is connected to the counter electrode 105. This method is called the C _{S on-} gate method.

The second method is as shown in FIG.
The 106 is electrically connected to the counter electrode 105. In this case, the voltage v _x of the voltage of the storage capacitor electrode 106 is the counter electrode 1
It becomes equal to the voltage v _c of 05.

In the second method, a take-out bus line for connecting the auxiliary capacitance electrode 106 to the counter electrode 105 needs to be wired in parallel with the scan electrode 101, which causes a problem of reduction in aperture ratio. On the other hand, the first method is advantageous from the viewpoint of aperture ratio because the extraction bus line can be shared with the gate electrode.

(Problems to be Solved by the Invention) By the way, a conventional source driver includes a logic circuit section that operates at a low voltage such as a shift register and a counter, and a medium voltage section such as a sample hold circuit, a level shifter circuit, and an output buffer. Has been done. When monolithic LSI is used for the above parts having different operating voltages, it is necessary to adopt design rules and manufacturing processes suitable for the medium breakdown voltage part. Therefore, it is difficult to increase the speed of the logic circuit section, and it is difficult to achieve high integration, low cost, and low power consumption of the LSI.

The present invention has been made in view of such a current situation, and its purpose is to enable high speed, high integration, low cost, low power consumption, etc. of the signal electrode drive system, Another object of the present invention is to provide a drive circuit of a display device which can realize driving of a signal electrode drive system with a single power source.

(Means for Solving the Problems) A drive circuit of a display device of the present invention corresponds to a plurality of parallel signal electrodes, a plurality of scan electrodes intersecting with the signal electrodes, and intersections of the signal electrodes and the scan electrodes. For driving a display unit having a picture element electrode provided with a counter electrode, a counter electrode provided so as to face the picture element electrode, and an auxiliary capacitance electrode that forms a capacitance with the picture element electrode, A drive circuit of a display device, comprising signal electrode drive means for driving the signal electrode,
Counter electrode driving means for applying an AC voltage to the counter electrode to the counter electrode, and to the predetermined reference voltage during a positive period when the AC voltage applied to the counter electrode is higher than the predetermined reference voltage. A plurality of positive and negative voltage signals of different levels and a voltage signal belonging to the negative side having a wider gradation display range than the voltage signal belonging to the positive side is applied to the counter electrode. During a negative period in which the AC voltage is lower than the predetermined reference voltage, the AC signal is composed of a plurality of positive and negative voltage signals of different levels with respect to the predetermined reference voltage, and the voltage signal belonging to the positive side is the negative side. A second voltage signal group having a wider gradation display range than that of the voltage signal belonging to the signal electrode driving means, the voltage electrode supplying means supplying the second voltage signal group to the signal electrode driving means, and the signal electrode driving means according to the input image signal. To the voltage signal supply means One of the supplied first voltage signal group and the second voltage signal group is selected from the first voltage signal group during the positive period and the second voltage signal group is supplied during the negative period. A voltage signal is selected from a voltage signal group, the selected voltage signal is sent to the signal electrode as a drive voltage, and the drive voltage having the same phase as the AC voltage applied to the counter electrode by the counter electrode driving means is used for the auxiliary capacitance. The structure is such that the electrodes are driven, whereby the above-mentioned object is achieved.

Each of the auxiliary capacitance electrodes is associated with a predetermined scan electrode of the scan electrodes, and each of the auxiliary capacitance electrodes is electrically connected to a scan electrode other than the predetermined scan electrode. May be.

Alternatively, the auxiliary capacitance electrode may be electrically connected to the counter electrode.

It is preferable that scan electrode driving means for driving the scan electrodes is further provided, and the scan electrode driving means operates in a floating state.

Further, it is preferable that the signal electrode driving means is operated by a single power source.

The amplitude of the AC applied voltage in the AC drive of the storage capacitor electrode is substantially equal to the amplitude of the AC applied voltage of the counter electrode.

(Operation) The purpose of the drive circuit of the present invention to include means for AC driving the counter electrode is to reduce the drive voltage of the signal electrode. For example, as shown in FIG. 2A, the polarity of the voltage applied to the signal electrode for each selection of the scanning electrode is “j” in the selection of the scanning electrode (FIGS. 2A to 2C). -2 ",
“J−1”, ... Represents the number of the selected scanning electrode), and when the signal electrode is AC-driven so as to be inverted with respect to the voltage V _a , When AC voltages (center voltage or reference voltage is voltage V _a ) whose phases are different by 180 degrees are applied to the counter electrode (Fig. 2 (b)),
The substantial amplitude of the applied voltage seen from the counter electrode is the amplitude of the signal electrode applied voltage plus the amplitude of the counter electrode applied voltage. Therefore, the signal electrode drive voltage required to obtain the same applied voltage as in the conventional case can be smaller than that in the case where the AC drive of the counter electrode is not performed. Therefore, it becomes possible to lower the operating voltage of the medium withstand voltage portion conventionally included in the signal electrode driving means, and further, the entire signal electrode driving means is
Voltage that matches the logic level of the logic circuit (eg + 5V)
It can also be driven by a single power supply.

For example, in a matrix type liquid crystal display device having picture elements represented by the equivalent circuit shown in FIG.
When the potential v _{c of} 105 is constant, the voltage V _LC held by the capacitance C _{LC of the} liquid crystal element is constant during the holding period in which the pixel electrode 103 is not driven. However, for example, when AC driving of the counter electrode 105 as shown in FIG. 2B is performed, the voltage V _LC changes as the potential of the counter electrode 105 changes.
It becomes like the following formula.

Here the voltage V _B is constant and C _S is the auxiliary capacitance. Further, ± ΔV / (1 + C _S / C _LC ) is a voltage fluctuation amount caused by AC driving of the counter electrode 105. The drive circuit of the present invention is
In order to cancel such a variation of V _LC , a means for AC driving the auxiliary capacitance electrode in the same phase as the AC driving of the counter electrode is provided. In particular, if an AC voltage having an amplitude substantially the same as the amplitude of the AC applied voltage to the counter electrode is applied to the auxiliary capacitance electrode, the voltage V _LC hardly changes. More specifically, as shown in FIG. 6 (a), in the positive period in which the drive voltage applied to the counter electrode (see FIG. 6 (b)) is high with respect to the reference voltage (va), the reference potential is high. (va) voltage levels for is positive "-V _0", "- V _1" and the like, a is negative "-V _3", "- V _4", "- V _5", "- V ₆ "," -V ₇ "
And so on. Here, as shown in FIG. 6C, the gradation display range of the voltage signal belonging to the negative side with respect to the reference potential (va) is wider than that of the voltage signal belonging to the positive side. In the negative period when the drive voltage applied to the counter electrode is low with respect to the reference potential (va), the voltage level is negative with respect to the reference potential (va) such as “+ V ₀ ”, “+ V ₁ ”, and the like. , positive there "+ V _3", "+ V _4", "+ V _5", "+ V _6", "+ V _7"
And so on. Here, as shown in FIG. 6C, the gradation display range of the voltage signal belonging to the positive side with respect to the reference potential (va) is wider than that of the voltage signal belonging to the negative side. However, “−V ₀ ” and “+ V ₀ ” are not only those in which the positive and negative polarities are inverted, but also the absolute values are different, as shown in Table 1. This is the same between other "-V ₁ " and "+ V ₁ ".

In the present invention, the first and second objects to be selected
Of the first voltage signal group, the voltage signals of the first voltage signal group independently, the voltage signals of the second voltage signal group independently, and the first voltage signal group and the second voltage signal group. It is also possible to independently determine each voltage signal with respect to the voltage signal group of, and it is possible to set so as to obtain the optimum gradation according to the applied voltage-light transmittance characteristics of the display panel. it can.

(Examples) The present invention will be described below with reference to examples.

FIG. 1 schematically shows an example of a matrix type liquid crystal display device using an embodiment of the present invention. As the TFT liquid crystal panel 100, a C _{S on-} gate type is taken as an example. The drive circuit 1 for displaying on the TFT liquid crystal panel 100 includes a source driver 2, a gate driver 3, an AC bias circuit 7 as a voltage signal supply means, a counter electrode drive circuit 8 and a control circuit 4. The gate driver 3 has substantially the same structure as the gate driver 300 of the conventional drive circuit shown in FIG. The AC bias circuit 7 supplies to the source driver 2 a plurality of voltage signals having different levels in which a positive voltage period and a negative voltage period with respect to an appropriate reference voltage are alternately provided. The timing signal necessary for the operation of the AC bias circuit 7 is given from the control circuit 4. The source driver 2 selects one of a plurality of levels of voltage signals provided from the AC bias circuit 7 according to the value of the input digital image signal or video signal, and uses the selected voltage signal as a signal electrode of the TFT liquid crystal panel 100. It is sent to 102. The source driver 2 includes an up / down counter and decoder circuit 20, a digital data memory 30, a data decoder circuit 40, and a voltage level selection circuit 50. Various signals necessary for the operation of the source driver 2 are supplied from the control circuit 4.
The output of the counter electrode drive circuit 8 is given to the counter electrode 105 and the gate driver power supply circuit 9.

The source driver 2 is shown in more detail in FIG. The example shown in FIG. 3 corresponds to color display, and R, G and B signals are 3-bit data R _{0 to} R ₂ , G _{0 to} G ₂ , respectively.
And R represented by B ₀ .about.B _2, an image signal composed of G and B signals are input to the source driver 2. The up-down counter and decoder circuit 20 includes an up-down counter 21
And a counter decoder 22. The up / down counter 21 is supplied with a U / D signal for designating a count in the increasing direction or a count in the decreasing direction and a clock CK for causing the up / down counter 21 to perform a counting operation. The output of the up / down counter 21 is decoded by the counter decoder 22. The up / down counter and decoder circuit 20 can also be configured with a shift register.

R signal (R ₀ ~ included in the input digital image signal
R ₂ ), G signal (G _{0 to} G ₂ ), and B signal (B _{0 to} B ₂ ) are once latched by latches 31, 32, and 33, respectively, and then digital data memory according to the output of the decoder 22. The R memory 34, the G memory 35, and the B memory 36 constituting the memory 30 are stored in corresponding storage units. After the digital image signal for one horizontal scanning period is stored in the digital data memory 30, by inputting the latch strobe signal LS,
The data in the digital data memory 30 is given to the data decoder circuit 40 in parallel. The output of the data decoder circuit 40 is given to the voltage level selection circuit 50. The voltage level selection circuit 50 includes a voltage signal ± V ₀ to ± V from the AC bias circuit 7.
V ₇ is input.

A system for processing one R signal in the data decoder circuit 40 and the voltage level selection circuit 50 is shown in FIG. Details of the voltage level selection circuit 50 are also shown in FIG. In the data decoder circuit 40, the R signal R ₀ (i) to
A 3-bit latch circuit 41 to which R ₂ (i) is applied and a data decoder 42 are provided. R signal R ₀ (i) ~ R
₂ (i) is latched by the latch circuit 41 when the latch strobe signal LS is input, and decoded by the data decoder 42. The output from the output terminals 0 to 7 of the data decoder 42 is one of the outputs depending on the contents of the R signals R ₀ (i) to R ₂ (i).
The individual becomes the H level, and the other becomes the L level. The output of the data decoder 42 is applied to the voltage level selection circuit 50.

In the voltage level selection circuit 50, an output terminal and line 51 _{0-51 7} supplies a voltage signal ± V ₀ ~ ± V ₇ from the AC bias circuit
Analog gates AG _{0 to} AG ₇ are provided between the analog gates 52 and 52, respectively. The output of the data decoder 42 is applied to the gate input terminals of the analog gates AG _{0 to} AG ₇ , respectively, and the outputs are rendered conductive when the output is at the H level. For example, if the output of the terminal 7 of the data decoder 42 is at H level,
Analog gate AG ₇ is conducting and the voltage signal on line 51 ₄ ±
V ₇ is sent to the 3i-th signal electrode 102 as an R (i) signal. Data decoder circuit 40 corresponding to each signal electrode 102
And each part of the voltage level selection circuit 50 operates in parallel as described above.

The AC bias circuit 7 will be described. The AC bias circuit 7 includes a first voltage signal output circuit 70, a second voltage signal output circuit 74, and a selection circuit 79. The first voltage signal output circuit 70 is connected in series between the terminal 701 to which the power supply voltage V _CC is applied and the terminal 702 to which the ground voltage V _SS is applied.
It has resistors R _{0 to} R ₇ . Resistor R ₀ buffer 71 from the connection point of the to R _{7 0} -71 ₆ a through respective voltage signal + V ₀ ~ + V ₆
Is taken out. The power supply voltage V _CC is taken out as a voltage signal + V ₇ . The voltage signal + V ₀ to + V ₇ is the analog gate 72
_{0-72 7} via respectively, are supplied to the line 51 _{0-51 7} voltage level selection circuit 50. The second voltage signal output circuit 74 is
The resistors R _{0 to} R ₇ are connected in series between the terminal 741 to which the power supply voltage V _CC is applied and the terminal 742 to which the ground voltage V _SS is applied. From the connection point of resistors R _{0 to} R ₇ to buffer 75 ₀ to 75 ₆
The voltage signals −V ₀ to −V ₆ are taken out via the respective.
The ground voltage V _SS is taken out as the voltage signal −V ₇ . Voltage signal -V ₀ ~-V ₇ is supplied with the analog gate 76 _{0-76 7} to line 51 _{0-51 7} via respectively.

The selection circuit 79 functions as a T flip-flop 2
It has D flip-flops 791 and 792. The horizontal synchronizing signal H is applied to the clock terminal of the D flip-flop 791.
_SYNC is input. Further, the vertical synchronizing signal V _SYNC is input to the clock terminal of the D flip-flop 792. Therefore, the output of the D flip-flop 791 is the horizontal synchronization signal H.
Inverts every time _SYNC is input, and D flip-flop 792
The output of is inverted every time the vertical synchronization signal V _SYNC is input. The output of the D flip-flops 791 and 792 is the XOR gate 7
It is input to 93 and the output of the XOR gate 793 is given to the non-inverting level shifter 794 and the inverting level shifter 795. Analog gates 72 _{0 to} 72 ₇ depending on the output of non-inverting level shifter 794
Is controlled. The analog gate 76 _{0-76 7} is controlled by the output of the inverting level shifter 795.

Output of D flip-flop 791 and D flip-flop 7
When the output of 92 does not match, the outputs of the level shifters 794 and 795 are H level and L level, respectively.
Analog gate 72 _{0-72 7} becomes conductive, the voltage signal + V ₀ ~ + V ₇
Are supplied to the voltage level selection circuit 50. On the other hand, in the case where the outputs of the D flip-flop 792 of the D flip-flop 791 are coincident, the output of the level shifter 794 and 795, respectively to the L level and H level, the analog gate 76 _{0-76 7} becomes conductive, The voltage signals −V ₀ to −V ₇ are supplied to the voltage level selection circuit 50. The output of the D flip-flop 792 is constant during one frame, and the output of the D flip-flop 791 is inverted every horizontal scanning period. Therefore, in a certain frame, the voltage signal + V ₀ during the odd-numbered horizontal scanning period.
~ + V ₇ is a voltage signal -V ₀ to the even-numbered horizontal scanning period ~ -
V ₇ is supplied to the voltage level selection circuit 50. In the frame next to the above frame, the D flip-flop 792
Since the output of the signal is inverted, the voltage signals + V ₀ to + V ₇ are supplied to the voltage level selection circuit 50 during the even-numbered horizontal scanning period and the voltage signals −V ₀ to −V ₇ are supplied to the odd-numbered horizontal scanning period.

The gate driver 3 will be further described with reference to FIG. The present embodiment is a C _{S on-} gate type TFT liquid crystal panel 1
00, the storage capacitor electrode 106 is AC-driven through the scan electrode 101, as will be described later. For this purpose, it is necessary to make the gate driver 3 perform a floating operation. Control circuit 400 to gate driver 3
As shown in FIG. 5, the scan clock pulse and the scan start pulse, which are control signals to the photocouplers 501 and 5
It is given through 02 respectively. A rectangular wave from the counter electrode drive circuit 8 is applied to the node 91 of the gate driver drive circuit 9, so that the operating voltage of the gate driver 3 seen from a certain common voltage is swung. As a result, AC driving of the auxiliary capacitance electrode 106 is performed.

AC driving of the counter electrode 105 and the auxiliary capacitance electrode 106 will be described. 6 (a) and 6 (b) show the waveforms of the AC voltage applied to the signal electrode 102 and the counter electrode 105, respectively. FIG. 6C shows the signal electrode 1 viewed from the counter electrode 105.
The waveform of the applied voltage of 02 is shown. Fig. 6 (a)-
In (c), “j−1”, “j”, ... Show the numbers of the selected scan electrodes 101. The source driver 2 is assumed to operate with a single + 5V power supply (that is, V _CC = + 5V, V _SS = 0V). The center voltage v _a of AC driving of the signal electrode 102, the counter electrode 105, and the auxiliary capacitance electrode 106 is 2.5V. The level of the voltage signal supplied from the AC bias circuit 7 to the source driver 2 is shown in Table 1 below.

Table 1 _{+ V 0 = 1.5V -V 0 =} 3.5V + V 1 = 2.0V -V 1 = 3.0V + V 2 = 2.5V -V 2 = 2.5V + V 3 = 3.0V -V 3 = 2.0V + V 4 = as shown in _{3.5V -V 4 = 1.5V + V 5} = 4.0V -V 5 = 1.0V + V 6 = 4.5V -V 6 = 0.5V + V 7 = 5.0V -V 7 = 0V Figure 6 (a) In the AC driving of the signal electrode 102, when a voltage −V ₀ to −V ₇ is used when scanning a certain scan electrode 101, a voltage + V ₀ is used when scanning an adjacent scan electrode 101.
This is done by using ~ + V ₇ . Counter electrode 105
As shown in FIG. 6 (b), the counter electrode drive circuit 8 AC drives the signal electrode 102 in a phase different from the AC drive phase by 180 degrees. The voltage applied to the counter electrode 105 is + ΔV = 5.5V and −ΔV = −0.5V. Therefore, the amplitude of the AC drive is ± 3V with respect to the center voltage v _a (= 2.5V). The signal electrode applied waveform viewed from the counter electrode 105 is as shown in FIG. 6 (c). FIG. 6C also shows the transmittance of the liquid crystal element in the normally white display mode. As can be seen from FIGS. 6A to 6C, due to the AC driving of the counter electrode 105, the amplitude of the applied voltage viewed from the counter electrode 105 is large even if the voltage applied to the signal electrode 102 is small.

In order to avoid fluctuations in the holding voltage of the liquid crystal element due to AC driving of the counter electrode 105, a voltage as shown in FIG. 7 is applied to the scan electrode 101. The voltage applied to the (j-1) th scan electrode 101 is applied to the auxiliary capacitance electrode 106 corresponding to the jth scan electrode 101. Regarding the voltage applied to the scan electrode 101, when the voltage applied to the counter electrode 105 is + ΔV, the H level is ((V _BB −V _DD ) / 2 + ΔV) and the L level is − ((V _BB −V _DD ) / 2−ΔV). When the voltage applied to the counter electrode 105 is −ΔV, the H level is ((V _BB −V _DD ) / 2−ΔV) and the L level is −ΔV.
((V _BB −V _DD ) / 2 + ΔV). Where V _BB −V _DD =
It is 24V. As can be seen from FIG. 7, the H level pulse is applied to the scan electrode 101 at the time of selection, and the AC voltage having a center voltage of −12 V is applied during the other periods. FIG. 8 shows the waveform of the voltage applied to the scanning electrode 101 as viewed from the counter electrode 105.

In this way, the auxiliary capacitance electrode 106 is AC-driven with the same phase and the same amplitude as the counter electrode 105 via the scan electrode 101, whereby the signal electrode applied voltage (see FIG. 6C) and the counter electrode viewed from the counter electrode 105. The scanning electrode applied voltage (see FIG. 8) viewed from 105 is completely released from the influence of AC driving of the counter electrode 105, and the conditions are the same as the case where a DC voltage is applied to the counter electrode 105.

The above has been described an embodiment for driving the TFT LCD panel C _S on-gate method, if the auxiliary capacity electrode to drive the TFT liquid crystal panel which is electrically connected to the counter electrode, the counter electrode When AC driving is performed, the auxiliary capacitance electrode is AC driven similarly to the counter electrode.

Further, although the above embodiment is a so-called digital drive circuit, the present invention can be applied to the conventional analog drive circuit.

(Effect of the Invention) In the drive circuit of the display device of the present invention, the amplitude of the voltage applied to the signal electrode for obtaining a predetermined voltage between the pixel electrode and the counter electrode is reduced by AC driving the counter electrode. can do. Therefore, it is possible to lower the operating voltage of the medium breakdown voltage portion in the conventional signal electrode drive system, and it is possible to speed up the signal electrode drive system, increase the degree of integration, reduce the cost, and reduce the power consumption. Further, the signal electrode drive system can be operated by a single power source. Further, regarding the first and second voltage signal groups, each voltage signal of the first voltage signal group is independently, and each voltage signal of the second voltage signal group is independently, and further, It is possible to independently determine each voltage signal between the voltage signal group and the second voltage signal group, and therefore, the counter electrode is more negative than the reference voltage during the positive period higher than the reference voltage. Is used for the first voltage signal group in which the gradation display range is wider than that of the positive side, and the positive side is wider than the negative side than the reference side during the negative period when the counter electrode is lower than the reference side. By using the second voltage signal group having the gradation display range, it is possible to lower the reference potential and achieve low power consumption. Further, by increasing the speed of the signal electrode driving system, a driving circuit capable of processing a high-speed input image signal and thus driving a large-capacity display device is realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram of a matrix type liquid crystal display device using an embodiment of the present invention, and FIGS. 2 (a) to (c) schematically show an example of drive voltage waveforms by a drive circuit of the present invention. FIG. 3 is a block diagram of the source driver of the embodiment shown in FIG. 1, and FIG. 4 is a diagram showing the main parts of the data decoder circuit, voltage level selection circuit and AC bias circuit of the embodiment,
FIG. 5 is a block diagram of a gate driver of the embodiment, FIGS. 6 (a) to (c), FIGS. 7 and 8 are diagrams schematically showing drive voltage waveforms according to the embodiment, and FIG. Is a schematic block diagram of an example of a matrix type liquid crystal display device using a conventional drive circuit, FIG. 10 is a circuit diagram of a source driver of the display device of FIG. 9, and FIG. 11 is an operation of the source driver of FIG. FIG. 12 is a timing chart shown, FIG. 12 is an equivalent circuit diagram of pixels of a TFT liquid crystal panel, and FIG. 13 is a diagram schematically showing a TFT liquid crystal panel in which an auxiliary capacitance is electrically connected to a counter electrode. 1 ... Driving circuit, 2 ... Source driver, 20 ... Up-down counter and decoder circuit, 21 ... Up-down counter, 22 ... Counter decoder, 30 ... Digital data memory, 40 ... Data decoder circuit, 50 ...... Voltage level selection circuit, 7 ... AC bias circuit, 8 ... Counter electrode drive circuit, 9 ... Gate driver power supply circuit, 100 ... T
FT liquid crystal panel, 101 ... Scan electrode, 102 ... Signal electrode, 10
3 ... Pixel electrode, 104 ... TFT, 105 ... Counter electrode, 106 ...
... Auxiliary capacitance electrode.

Claims (3)

(57) [Claims] 1. A plurality of signal electrodes arranged in parallel, a plurality of scanning electrodes intersecting with the signal electrodes, picture element electrodes provided corresponding to respective intersections of the signal electrodes and the scanning electrodes, and the picture element electrodes. A drive circuit of a display device for driving a display unit having a counter electrode provided facing each other and an auxiliary capacitance electrode forming a capacitance between the pixel electrode and the pixel electrode, and driving the signal electrode. Signal electrode driving means, a counter electrode driving means for applying an AC voltage with respect to a predetermined reference voltage to the counter electrode, and a positive period in which the AC voltage applied to the counter electrode is higher than the predetermined reference voltage, A first voltage signal group composed of a plurality of positive and negative voltage signals having different levels with respect to the predetermined reference voltage, and the voltage signal belonging to the negative side has a wider gradation display range than the voltage signal belonging to the positive side. Is applied to the counter electrode. In a negative period in which the voltage is lower than the predetermined reference voltage, the voltage signal is composed of a plurality of positive and negative voltage signals of different levels with respect to the predetermined reference voltage, and the voltage signal belonging to the positive side is the voltage belonging to the negative side. A second voltage signal group having a wider gradation display range than that of the signal, the voltage signal supplying means supplying the signal electrode driving means to the signal electrode driving means, wherein the signal electrode driving means responds to the input image signal with the voltage signal. One of the first voltage signal group and the second voltage signal group supplied by the supply means is selected from the first voltage signal group during the positive period, and is selected during the negative period. By selecting from the second voltage signal group, sending the selected voltage signal as a drive voltage to the signal electrode, and by using a drive voltage having the same phase as the phase of the AC voltage applied to the counter electrode by the counter electrode driving means. The storage capacitor electrode is driven. Drive circuit of the display device. 2. The auxiliary capacitance electrodes are respectively associated with predetermined scan electrodes of the scan electrodes, and are electrically connected to scan electrodes other than the predetermined scan electrodes. A drive circuit of the display device according to. 3. The drive circuit of the display device according to claim 1, wherein the auxiliary capacitance electrode is electrically connected to the counter electrode.