JP2677972B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a field effect transistor having a high breakdown voltage between electrodes.

[0002]

2. Description of the Related Art FIG. 3 shows an example of an electrode structure of a field effect transistor (hereinafter simply referred to as FET) in the prior art.
The figure (A) is a top view and the figure (B) shows the sectional view. As shown in the plan view, 31 is an n-layer pattern and 32 is a p-layer.
A layer pattern, 33 is a gate electrode pattern, 34 is a source electrode pattern, and 35 is a drain electrode pattern. Further, as shown in the cross-sectional view, the n layer 31 is an active region layer (also simply referred to as an active layer), and the p layer 32 is a buried structure layer (also simply referred to as a buried layer).
It is formed as. The spread of the p-layer pattern with respect to the n-layer pattern is matched with the alignment margin of the exposure device. In this pattern, since the source and the drain are connected via the p layer, there is a possibility that a leak may occur between the source and the drain, so that the expansion of the p layer cannot be increased. Specifically, the protrusion width related to the increase in the spread of the p layer with respect to the n layer in FIG. 3, that is, for example, in FIG.
In (B), the contact width between the source electrode 34 and the p layer 32 is 0.2.
It is only about μm. Therefore, in such a conventional technique, the electrode is not sufficiently connected to the p layer.

In the present specification, unless otherwise specified, for the sake of convenience, a description will be given using a conductive type FET in which the active layer is an n layer and the buried layer is a p layer. This is because the gist of the description does not change even with FETs having different conductivity types.

[0004]

As described above, in the prior art, the electrode structure on the source side is not designed to form a sufficient ohmic electrode for the p layer.
There is no escape route for excess holes generated by ionization, the hole extraction time becomes longer, and the channel potential is lowered.Therefore, a larger amount of current flows, and positive feedback that promotes ionization occurs, resulting in drainage due to hole accumulation. This caused a decrease in withstand voltage.

The phenomenon in the semiconductor will be described in a little more detail. The electric field related to the drain withstand voltage of the FET becomes a high electric field at the drain end of the gate,
Higher ionization probability. Therefore, a large number of electron-hole pairs are generated at this place. The electrons escape to the drain, but the holes try to escape to the source side through the p-layer, but the source side does not have enough ohmic electrodes for the holes and is driven back into the channel and returns. Come on. Then, it accumulates near the source. Some of them recombine with electrons to emit band-edge light, but a considerable part of them stays at the source end of the gate, increasing the hole concentration in this region. When the hole concentration increases, the potential in that region decreases, electrons flow more easily, and the current increases. Then, the ionization will proceed further. In this way, positive feedback is applied and the current value destructively increases, resulting in a decrease in drain breakdown voltage.

As described above, the conventional electrode structure of the FET has a problem that the breakdown voltage between the electrodes is lowered. An object of the present invention is to provide a semiconductor device having an electrode structure of an FET that can improve the withstand voltage between electrodes.

[0007]

In order to achieve the above object, the present invention has, as a basic structure, an active region layer of a first conductivity type, for example, n layers, and an active region of the first conductivity type. Territory
In a FET having a buried structure layer of a second conductivity type, for example, ap layer formed so as to cover the bottom surface and all side surfaces of the region layer , for example, as shown in FIG. Of the conductivity type, for example, an electrode structure connected to the buried structure layer of the p layer, and conversely, the active region layer of the first conductivity type is the p layer and the buried structure of the second conductivity type is provided. If the structure layer is an n layer, either the source electrode or the drain electrode is provided so that only the drain electrode has an electrode structure connected to at least the buried structure layer of the second conductivity type n layer. And only comprises an electrode structure connected to at least a second conductive type buried structure layer.
That is, one of the source electrode and the drain electrode forms at least a buried structure layer of the second conductivity type and a sufficient ohmic electrode, and the other of the source electrode and the drain electrode has an activity of the first conductivity type. It is to form an electrode structure connected to the region layer.

Here, the electrode structure connected to at least the second conductive type buried structure layer is provided with a part of the electrode structure connected to the first conductive type active region layer.
For example, as illustrated in the source electrode 14 of FIG. 1, one electrode structure common to both the active region layer and the buried structure layer may be provided.

Alternatively, the electrode structure connected to at least the second conductive type buried structure layer has a second conductive type buried structure as shown in, for example, the electrodes 24 and 26 of FIG. An electrode structure connected only to the structure layer and an electrode structure connected only to the first conductivity type active region layer may be provided with a structure having a shape separated from each other. This has the advantage that electrodes suitable for each conductivity type can be formed.

[0010]

According to the present invention, only one of the source electrode and the drain electrode has an electrode structure connected to at least the second conductive type buried structure layer. The drain electrode is not connected via the buried structure layer. Therefore, there is no leak current between both electrodes via the buried structure layer. Therefore, more importantly, according to the present invention, it becomes possible to form a sufficient ohmic electrode for the buried structure layer. Therefore, in the present invention, in the case of a conductive type FET as shown in FIG. 1 or 2, for example, holes generated by ionization can be promptly removed via a source electrode which can be an ohmic electrode sufficient for this. It will be possible. Therefore, the drain breakdown voltage can be improved by intentionally breaking the positive feedback. That is, the electrode structure of the present invention can improve the inter-electrode breakdown voltage.

[0011]

FIG. 1 shows an embodiment of the electrode structure of the present invention, and FIG. 2 shows another embodiment of the electrode structure of the present invention. Among them, (A) is a plan view and (B) is a sectional view. In FIG. 1, 11 is an n-layer pattern serving as an active layer, and 12 is an n- layer pattern.
A p-layer pattern as a buried structure layer formed so as to cover the bottom surface and all side surfaces of the tongue 11, and 13, 14, and 15 are a gate electrode, a source electrode, and a drain electrode, respectively. When this FET has n + for reducing the source resistance, this n-layer pattern is the sum of the n + layer and the n-layer pattern. Furthermore, surrounding this n-layer pattern, 12 p
There are layer patterns. Although the n layer is surrounded by the entire circumference in this figure, the ohmic electrode is not necessarily formed on the entire circumference as long as the ohmic electrode is formed on the buried p layer. In the case of the present embodiment, the ohmic electrode for the buried p layer and the source electrode for the n layer are formed of electrodes having the same structure. In the conventional technique, since the source electrode and the drain electrode are also on the p layer, a leak is generated between the source electrode and the drain electrode via the p layer.
It was not possible to form a sufficient ohmic electrode for the layer. Then, as described above, the protrusion width of the p-layer pattern with respect to the n-layer pattern was only about 0.2 μm. In this embodiment, the drain side is not connected to the p layer, and naturally no leak current is generated through the p layer. Therefore, on the source side of the present embodiment, the width of the p-layer where the p-layer and the ohmic electrode are formed is 5
The thickness is increased to about μm, whereby a sufficient ohmic electrode for the p layer is formed. And for this reason, the holes generated by ionization can be quickly removed,
Therefore, holes are not accumulated on the source side, and the positive feedback loop can be broken.

In the embodiment of FIG. 2, the source side electrode has a structure in which the ohmic electrode 26 to the buried p layer and the source electrode 24 formed on the active layer of the n layer are separated from each other. It was done. Holes generated by ionization are intentionally removed by the ohmic electrode 26 to the buried p layer, and there is no leak through the buried layer, which has the same effect as that of the embodiment of FIG. ing. However, in the case of this embodiment, there is an advantage that an electrode that is better suited to each of the n layer and the p layer can be independently formed.

In the above embodiments, the case where the active layer is the n layer and the buried layer is the p layer has been described. However, in this case, FETs each having a conductivity type opposite to that of the FET are formed. In addition, the same effect can be obtained even if only the drain electrode has an electrode structure connected to at least the buried layer.

Furthermore, the present invention also includes the case where an electrode is provided for the buried p layer when there is an n + layer and a buried p layer for the n + layer.

[0015]

As described above, by using the structure of the present invention, it is possible to prevent the FET from being destroyed even when a high voltage is applied to the drain or the source corresponding to the conductivity type. The present invention is advantageous as a high power FET because it is very important to apply a high voltage when high power is taken out from the FET.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of an electrode structure of the present invention.

FIG. 2 is a diagram showing another embodiment of the electrode structure of the present invention.

FIG. 3 is a diagram showing an example of a conventional electrode structure.

[Explanation of symbols]

11, 21, 31 ... N-layer pattern (when the FET also has an n + layer, the outer circumference of the union of the n-layer and the n + layer is shown)
Or n layer 12, 22, 32 ... p layer pattern or p layer 13, 23, 33 ... gate electrode pattern or gate electrode 14, 24, 34 ... source electrode pattern or source electrode 15, 25, 35 ... drain electrode pattern or drain Electrode 26: Ohmic electrode on p layer

Claims (3)

(57) [Claims] 1. An active region layer of a first conductivity type and the first
Formed to cover the bottom and all sides of the conductivity type active region layer
A second conductive type buried structure layer and a source electrode, a gate electrode, and a drain electrode formed on these surfaces, at least one of the source electrode and the drain electrode is at least A semiconductor device comprising an electrode structure connected to a second conductive type buried structure layer. 2. The semiconductor device according to claim 1, wherein the electrode structure connected to the at least second conductivity type buried structure layer is partially connected to the first conductivity type active region layer. A semiconductor device having a structure. 3. The semiconductor device according to claim 1, wherein the electrode structure connected to at least the second conductive type buried structure layer is an electrode connected only to the second conductive type buried structure layer. A semiconductor device comprising a structure and a structure in which an electrode structure connected only to a first conductivity type active region layer is separated from each other.