JP2676990B2 - Wiring pattern inspection equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring pattern inspection apparatus for inspecting a wiring pattern of a printed circuit board or a photomask for defects.

2. Description of the Related Art Conventionally, inspection for defects of printed circuit boards and the like has relied on visual inspection by humans. However, as products become smaller and lighter, wiring patterns on printed circuit boards are becoming finer and more complex. Under such circumstances, it has become difficult for humans to maintain extremely high inspection accuracy and to maintain very fine wiring patterns for a long time.
Automation of inspection is strongly desired.

As a wiring pattern defect detection method,
See, Jorge LCSanz and A
nil K. Jain: “Machine-vision techniques for in spec
tion of printed wiring boards and thick−filem cir
cuits ", Opticl Society of America, Vol.3, No.9 / septem
ber, pp1465 ~ 1482, 1986) have introduced a number of methods, which can be mainly classified into two methods, the design rule method and the comparison method. However, these methods have advantages and disadvantages.

Among them, Jona.
Man Devil (Jonr. Mandevile: “Novelmethod for analy
sis of printed circuit images ".IBM J.Res.DEVELOP ..
VOL.29, NO.1.JANUARY.1985), which proposes a method of detecting defects in the wiring pattern by shrinking or expanding the binarized image data and then thinning it. This will be explained as an example.

FIG. 7 shows the flow of the process of defect detection. (A) ~
(D) shows detection of disconnection, and (e) to (h) show detection of short circuit.

FIG. 7 (a) shows a defect image in which points b and c are fatal defects such as abnormal line width and disconnection, and point a is not a defect. In the same figure (b) as the first step, an image contraction process (a process of removing each pixel from the periphery) is performed. By this processing, the defect b is disconnected.
In the same figure (c) as the second step, a thinning process (a process of removing each pixel from the periphery until one line is obtained) is performed. Thus, the wiring pattern becomes one line. Third
In step (d) of the same figure, a defect is detected while scanning a 3 × 3 logic mask and referring to an LUT (look-up table), and points b and c can be detected as a disconnection. Further, the connection point between the terminal portion and the wiring pattern is also detected.

Next, regarding the short circuit and the line abnormality, FIG.
A description will be given along the flow of the process (h).

Part (e) of the same figure shows a defect image in which points b and c are considered to be fatal defects due to abnormalities between lines and short circuits. In the same figure (f) as the first step, image expansion processing (expansion from the peripheral pixels pixel by pixel) is performed, whereby the point b becomes a short state. In the same figure (g) as the second step,
Perform thinning process to make one line. As the third step, in the same figure (h), the 3 × 3 logic mask is scanned and the LUT is scanned.
The defect is detected with reference to the (look-up table), and the points b and c can be detected as T branches, that is, as a short circuit. As described above, disconnection, line width abnormality, short circuit, and line-to-line abnormality can be detected.

The image processing methods such as the thinning process and the expansion process are described in detail in Shunji Mori and Tsukako Itakura: “Basics of Image Recognition [I]”, Ohmsha Co., Ltd., and thus detailed description thereof is omitted.

Problems to be Solved by the Invention Now, a method has been described in which a binarized image is shrunk or expanded, a defect is exaggerated, a thin line is formed, and a 3 × 3 logical mask is scanned to detect the defect. This method can be said to be a promising method that can reliably detect defects.

However, this method has a problem that it is not possible to distinguish between a short circuit and a design in the T branch. It has also been proposed that the coordinates of the T-branch be learned in advance with a good board, and the inspected board be compared with a good board to discriminate between a short circuit and a T-branch by design. However, although it depends on the mounting method of the substrate, the positional error of the wiring pattern between the substrates is said to be ± 0.3 to 0.6 mm, and alignment with a good substrate is also a major issue. Further, when the learning data is read, the characteristic information is not always stored in the order of occurrence, and it takes time to retrieve the next learning data.

In view of the above problems, the present invention provides a wiring pattern inspection apparatus having a simple configuration and capable of classifying and detecting abnormalities of various wiring patterns without complicated alignment.

Means for Solving the Problems To solve the above problems, the technical solution of the present invention is:
First, an image input unit for photoelectrically converting a wiring pattern formed on a printed circuit board, a binarization unit for converting a grayscale image from the image input unit into a binary image, and one pixel from the background of the wiring pattern. While shaving, the thinning process is repeatedly performed for all pixels a predetermined number of times to obtain a skeleton image. The skeleton image is scanned with n × m scanning windows and the lookup table is referred to. Feature extracting means for extracting features of the wiring pattern such as terminals, feature information extracted from the feature extracting means in advance on a non-defective printed circuit board, numbered in the order of extraction, and one or more as supplementary information of the feature information. Feature information storage means for adding and storing numbers of feature points in the vicinity,
A judgment processing means for outputting only the true defect while referring to the characteristic information read out from the characteristic information storage means based on the supplementary information from the printed circuit board to be inspected is provided.

Secondly, in addition to the first configuration, in the determination processing means,
The feature information from the printed circuit board to be inspected is compared with the feature information read based on the supplementary information from the feature information storage means, and only the true defect is output.

Operation In the present invention, first, a wiring pattern formed on a printed circuit board is photoelectrically converted, and the obtained grayscale image is converted into a binary image by a binarizing unit. By using the binary image, a thinning process (a skeleton image) is repeated n times such that a thinning process of removing one pixel at a time from the background of each pixel of the wiring pattern is repeated. When the target pixel is at the skeleton image position, n × m
Of the wiring pattern such as the terminal / T-branch of the wiring pattern and terminals by scanning the scanning window of No. 2 and referring to the look-up table The complex position correction is performed by reading from the feature information storage means based on the additional information of the feature information to which one or more neighboring feature point numbers are added, and outputting only the true defect while referring to the feature information. It is possible to facilitate the search of the learning data to be referred to, because the processing for is unnecessary.

Secondly, the judgment processing means compares the relative position of the characteristic information from the inspected printed circuit board with the characteristic information read based on the supplementary information from the characteristic information storage means and outputs only the true defect. Therefore, the mounting position of the substrate to be inspected can be easily adjusted.

First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

FIG. 1 is a block diagram showing an embodiment of a wiring pattern inspection device of the present invention. In FIG. 1, 101 is a printed circuit board, 102 is an image inputting device including a diffusion type illumination device 104 such as a ring-shaped light guide, and an image pickup device 103 such as a CCD camera, and 105 is a binary image of a grayscale image. To 106, a feature extraction unit 106 for extracting a feature of a wiring pattern from a skeleton image by performing a thinning process for shaving one pixel from a background using a binary image, and a feature storage unit 108 for storing feature information of a non-defective substrate. The characteristic information storage means 109 includes a CPU 107, an I / F 110 for notifying a defect, and the like, and is a determination processing means for determining a true defect from the characteristic information of the substrate to be inspected and the learning data of 108.

 The operation will be described below with reference to FIG.

The wiring pattern formed on the printed circuit board 101 is illuminated by a diffusion type illumination device 104 such as a ring-shaped light guide, and the image input means 102 is provided with an imaging device 103 such as a CCD camera (one-dimensional or two-dimensional). Enter as a grayscale image with. In the present embodiment, a raster scan image will be described later, and therefore an example in which a one-dimensional CCD camera is used as the image pickup apparatus will be shown. In order to separate the background and the wiring pattern from the grayscale image obtained by the image inputting means 102, the binarizing means 105 compares it with an arbitrary threshold value and converts it into a binary image. Next, the feature extracting means 106 uses the binary pixels from the binarizing means 105 to perform thinning processing for removing the wiring pattern by one pixel from the background side n times to obtain a thinned image (skeleton image). Then, the skeleton image is scanned by an n × m scanning window, and the end of the wiring pattern
Outputs characteristic information such as branches and terminals. Feature information storage
A reference numeral 108 designates the characteristic information from the characteristic extraction means 106 on the non-defective board in the order of occurrence, and additionally stores the number of one or more characteristic points in the vicinity as supplementary information of the characteristic information. Are read out based on the supplementary information of the feature information. The judgment processing means 109 judges the true defect by the CPU 107 while referring to the characteristic information such as the terminal / T branch of the wiring pattern and the terminal from the characteristic extraction means 106 and the characteristic information of the non-defective substrate from the characteristic information storage means 108. It is a thing. Further, the determination result is notified of the true defect type and coordinates via the I / F 110.

The front surface of the printed circuit board 101 can be inspected by repeating and sequentially performing the above operation. This series of operations is performed in synchronization with an appropriate signal.

Next, the feature extraction unit 106, the feature information storage unit 108, and the determination processing unit 109 will be described in more detail.

The thinning process is a process for obtaining a thinned image (skeleton image) by repeating a process of removing one pixel from the outside of the wiring pattern by n times.
This will be described below with reference to FIGS.

The binary image is scanned with a 3 × 3 scanning window as shown in FIG. 2B, and when the pixel of interest (the central pixel of the window) is 1, the neighboring 8 pixels d _{1 to} d ₈ are changed according to the state. , The pixel of interest is 0 (that is,
It is determined whether or not to convert to (cut) using a LUT, and the determination of erasure of the pixel of interest is performed in four steps. The reason for this is
This is to prevent erasure of even pixel width patterns,
Patterns to be cut from the top, bottom, left and right are respectively registered in LUT (A) to LUT (D) shown in FIGS. 2 (c) to (f).

From FIG. 2 (a), 1 from the background side of the wiring pattern
A detailed block diagram of the pixel thinning processing is shown and described below.

The binary image 201 from the binarization means 105 is input to the line memory 202 for 1-line delay and the 3 × 3 scanning window 203, and transferred while taking timing of the pixel synchronization signal, which is not shown in the figure. To go. The output of the 3 × 3 scanning window 203 is input to the LUT (A) 204, which is a lookup table, and it is determined whether or not the target pixel is to be deleted. The same thing is cascaded and repeated four times. A skeleton image with one pixel removed 21
5 is output, and a thinned image (skeleton image) can be obtained by performing the same processing for the desired number of pixels to be cut.

Next, FIG. 3 shows a detailed block diagram of the feature extraction processing, which will be described below.

The feature extraction process is to detect features such as the terminal, T-branch, and terminal of the wiring pattern by using the skeleton image from the thinning process 216, and scan the n × m scanning window to scan 8 pixels around the target pixel. It is detected from the state. In this embodiment, the description will be made on the assumption that the scanning window is 3 × 3. In the figure, the skeleton image 301 from the thinning processing 216 is input to the line memory 302 and the 3 × 3 scanning window 303, and the 3 × 3 scanning window is input.
The state of the pixel of interest and the surrounding 8 pixels from 303 is determined by the LUT, and the detected feature type 305 is output. The LUT can distinguish the end / T branch of the wiring pattern, the terminal, and the like by preparing a reference table as shown in FIGS. 3B to 3I, for example. By the feature extraction, the synchronizing signal 307 or the like is input, and the coordinate data generator 306 outputs the coordinate data 308 of the pixel of interest.

FIG. 4 shows an example of the obtained feature points. Wiring pattern
Above 400 is a skeleton 410 obtained by the thinning process. The feature points to be extracted are the connection points 401, 402, T-branches 404, 405, 407, 408 and the termination points 403, 40 with the part that could not be thinned.
6 Among them, short circuit 409 (T branch 404, 405) and disconnection 411 (termination 403, 406) are shown as wiring pattern defects. However, the T-branches 407 and 408 are designed to have no short circuit.

As shown in FIG. 1, the determination processing unit 109 refers to the characteristic information such as the terminal / T branch of the wiring pattern and the terminal from the characteristic extraction unit 106 and the characteristic information of the non-defective substrate from the characteristic information storage unit 108 to determine whether or not it is true. The defect is determined by the CPU 107 and will be described below.

The processing flow of the determination processing means 109 will be described with reference to FIG. (A) First, the coordinates and detection information of the inspection data from the feature extraction unit 106 and all the learning data indicating the supplementary information of the previous learning data from the feature information storage unit 108 are compared. (B) Next, if the compared results match, it is the feature information registered in the learning data and is not considered as a defect. (C) If the compared results do not match,
Report or register as a defect.

Based on FIG. 4, learning data, which is characteristic information obtained in advance by a non-defective wiring pattern, and inspection data obtained by inspection are shown in FIG. 6 and Table 1 below. In FIG.
The ⊚ marks 1 to 4 indicate the feature points that have been registered as learning data, and the ⊚ and ● marks indicate the feature points obtained by the inspection. In addition, ⊚-∘ indicates the relationship of incidental information.

Tables 1 and 2 show learning data and inspection data, and are composed of numbers, XY coordinates, detection information and incidental information. The learning data in Table 1 has additional information added, and it is confirmed that there are feature points 2 (x2, y2) and feature points 3 (x7, y7) around the feature point 1 (x1, y1). I mean.

The inspection data in Table 2 shows the characteristic information and the inspection result. The feature points are OK because the XY coordinates and the detection information match the learning data. Next, what is detected as the characteristic point is the characteristic point 2 or the characteristic point 3 described in the supplementary information, and the detected characteristic point is OK because the XY coordinates and the detection information match the learning data. The candidate feature point to be detected next is the feature point 3 or the feature point 4, and the detected feature point is also extracted as a defect because the XY coordinates and the detection information are also different. Similarly, the feature points to the feature points are compared with the next candidate feature point 3 or feature point 4, and the XY coordinates and the detection information do not match and are extracted as a defect. Furthermore, since the feature points and the feature points match the feature points 3 and 4 of the learning data, it becomes OK. Further, S and E of the supplementary information indicate a start point and an end point. That is, even if feature points are detected after the end point, it is possible to extract all of them as defects.

Next, a second embodiment will be described using the processing flow of FIG. 4 (b).

(A) First, the relative values of the coordinates of the inspection data from the feature extraction means 106 and all the learning data indicated by the supplementary information of the previous learning data from the characteristic information storage means 108 are calculated as in the following equation.

Relative value (Ax, Ay) = | (x2, y2)-(x1, y1) | (b) Next, the inspection data from the feature extraction means 106 and the supplementary information of the previous learning data from the feature information storage means 108. The relative values of the coordinates and the detection information are compared with all the learning data indicated by. (C) Next, if the compared results match, it is the characteristic information registered in the learning data and is not considered as a defect. (D) If the compared results do not match, the defect is notified or registered.

EFFECTS OF THE INVENTION As described above, the effect of the present invention is to reduce the process of removing one pixel from the background side of the wiring pattern by using a binary image.
The skeleton image is repeatedly obtained, the skeleton image is scanned with an n × m scanning window to extract characteristic information such as termination / T-branch and terminal and numbered in the order of extraction, and one or more as additional information of the characteristic information. Numbers of feature points in the vicinity of are added and stored in the feature information storage means. The learning data can be searched at high speed by outputting only the true defect while referring to the characteristic information read from the characteristic information from the printed circuit board to be inspected based on the supplementary information from the characteristic information storage means. It will be possible.

Secondly, in the judgment processing means, the relative position of the characteristic information from the inspected printed circuit board and the characteristic information read based on the supplementary information from the characteristic information storage means is compared with each other and only the true defect is output. This makes it possible to speed up the search of the learning data and facilitate the alignment of the board to be inspected.

[Brief description of the drawings]

FIG. 1 is a block connection diagram of a wiring pattern inspection device according to an embodiment of the present invention, FIG. 2 (a) is a detailed block connection diagram of a thinning processing means in the device, and FIG.
(F) is a diagram showing the state of thinning processing, FIG. 3 (a) is a detailed block connection diagram of the feature extracting means in the same apparatus, and FIGS. 3 (b) to (i) are the state of feature extraction. Figure 4
The figure shows the processing performed by the apparatus, and FIG.
(B) is a process flow chart of the determination processing means in the device,
FIG. 6 is a diagram showing the positional relationship of the characteristic points in FIG. 5, and FIGS. 7 (a) to 7 (h) are diagrams showing the processing state of the conventional wiring pattern inspection apparatus. 101 ... Printed circuit board, 102 ... Image input means, 103 ...
Imaging device, 105 ... Binarizing means, 106 ... Feature extracting means,
107 ... CPU, 108 ... Feature information storage means, 109 ... Judgment processing means, 202 ... Line memory, 203 ... 3 × 3 scanning window,
204 …… LUT.

Claims (2)

(57) [Claims] 1. An image input unit for photoelectrically converting a wiring pattern formed on a printed circuit board, a binarization unit for converting a grayscale image from the image input unit into a binary image, and a background of the wiring pattern. While shaving each pixel, a thinning process is repeatedly performed for all pixels a predetermined number of times to obtain a skeleton image. The skeleton image is scanned with an n × m scanning window and the lookup table is referred to, thereby terminating the wiring pattern. Feature extracting means for extracting features of wiring patterns such as branches and terminals, feature information extracted from the feature extracting means in advance on a non-defective printed circuit board, numbered in the order of extraction, and one as additional information of the feature information. The characteristic information storage means for adding and storing the numbers of the above-mentioned nearby characteristic points and the characteristic information from the printed circuit board to be inspected from the characteristic information storage means. Referring while true defect only output to determination processing unit and the wiring pattern inspecting apparatus having the feature information read out on the basis of the band information. 2. The judgment processing means compares the relative position of the characteristic information from the inspected printed circuit board with the characteristic information read based on the supplementary information from the characteristic information storage means, and outputs only the true defect. Claim 1 characterized by the above.
The wiring pattern inspection device described.