JP2676406B2 - Semiconductor storage circuit device - Google Patents

Description

The present invention relates to a semiconductor memory circuit device having a CMOS gate array, and more particularly to a semiconductor memory circuit device capable of forming a ratio type latch.

[Conventional technology]

FIG. 5 is a block diagram of a semiconductor memory circuit device provided with a gate array, in which 1 denotes a semiconductor chip. Input / output pads 2 are arranged on the periphery of the semiconductor chip 1,
A plurality of basic cell stages 3 are provided in the central portion.

FIG. 6 is a configuration diagram of one basic cell stage 3 in FIG. 5, and FIG. 7 is an equivalent circuit diagram of the basic cell stage 3 as well. Here, as an example of the basic cell stage 3,
The gate separation method is shown.

In the figure, 6a and 6b are P-channel transistors and N, respectively.
It is a channel transistor. Each P-channel transistor 6a (N-channel transistor 6b) has a gate 5a.
It has a (gate 5b), a source and a drain made of a P-type diffusion region 4a (N-type diffusion region 4b). The plurality of P-channel transistors and N-channel transistors are connected in series.

In the basic cell stage 3 having such a configuration, the transistor at the position to be separated is turned off to disconnect the series connection of the transistors, and the separated transistor is used to form a desired circuit.

By the way, when a ratio type latch is constructed in a semiconductor integrated circuit device, it is common to use a circuit as shown in FIG. In the figure, 6b is an N-channel transistor to which the input terminal 8 of the ratio type latch is connected, and 5b is its gate. The output terminal of the transistor 6b is connected to the input terminal of the inverter 7a.
The output terminal of 7a is connected to the input terminal of another inverter 7b, and the output terminal of the inverter 7b is connected to the input terminal of the inverter 7a. Here, the inverter 7b is composed of a transistor having a smaller driving capability than the inverter 7a.

The operation of the ratio type latch having such a configuration will be described.

If transistor 6b is off, inverter 7
A loop circuit composed of a and 7b is formed, and the loop circuit holds data. For example, when the input of the inverter 7a is 0 (1), the output of the inverter 7a is 1
(0), the input of the inverter 7b becomes 1 (0), and the output of the inverter 7b becomes 0 (1). Here, since the output of the inverter 7b is the input of the inverter 7a, the data is accurately held in this loop circuit.

When the transistor 6b is on, the data applied to the input terminal 8 overcomes the output of the inverter 7b and is input to the inverter 7a. As a result, in the same operation procedure, the data applied to the input terminal 8 is held in the loop circuit. Then, once held, this data continues to be held even if the transistor 6b is turned off.

As described above, in a normal semiconductor memory circuit device, a ratio type latch is configured by using two types of transistors having different driving capabilities.

[Problems to be solved by the invention]

Since the size of the gate array is constant for each of the N-channel transistor and the P-channel transistor, it is not possible to obtain a plurality of types of transistors having different driving capabilities, so that in the semiconductor memory circuit device including the gate array, There is a problem that the ratio type latch as described above cannot be constructed.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor memory circuit device capable of forming a ratio type latch in a gate array.

[Means for solving the problem]

A semiconductor memory circuit device according to a first aspect of the present invention is a semiconductor memory circuit device including a ratio type latch using a basic cell of a CMOS gate array, which comprises an input transistor and an input transistor.
A first inverter having an input terminal connected to the source or drain of the transistor, a second inverter having an input terminal connected to the output terminal of the first inverter, an output terminal of the second inverter, and And a resistance element provided between input terminals of the first inverter, wherein the resistance element is constituted by gate wirings of a P-channel transistor and an N-channel transistor.

A semiconductor memory circuit device of a second invention is a semiconductor memory circuit device comprising a ratio type latch using a basic cell of a CMOS gate array, wherein the first inverter has an input terminal connected to the source or drain of the transistor. A second inverter having an input terminal connected to the output terminal of the first inverter, and a resistance element provided between the output terminal of the second inverter and the input terminal of the first inverter. The gate voltage of the resistance element is set to be in an off state, and the resistance of the source or drain region of the two P-channel transistors sharing one of the source and the drain is in an off state. The gate voltage is set to the shared source or drain of two N-channel transistors sharing one of the source or drain. It is characterized in that it includes the resistance in the region of the voltage.

[Action]

In the semiconductor memory circuit device of the present invention, the resistance element is connected to the output terminal of the second inverter, and the resistance element is a gate wiring of both the P-channel transistor and the N-channel transistor, or a source or drain region. A ratio type latch using transistors having different driving capabilities can be obtained by using the resistors of FIG.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments.

FIG. 1 is a configuration diagram of a ratio type latch of a semiconductor memory circuit device according to the present invention, and FIG. 2 is an equivalent circuit diagram expressing the circuit shown in FIG. 1 at a transistor level. In the figure, the parts with the same numbers as in the conventional example (Figs. 5 to 7) show the same parts.

In FIG. 1, 10 and 11 are VDD wiring and GND wiring, respectively, and these VDD wiring 10, GND wiring 11, gates 5a and 5b, P-type diffusion region 4a, and N-type diffusion region 4b are connected to each other by a gate. Wirings 12 passing through contact holes 13 formed in 5a, 5b and diffusion regions 4a, 4b.

Further, in FIG. 2, reference numeral 5 is a resistance formed by connecting the resistances of the gates of six transistors in series. In this example, the resistances of the six gate wirings are connected in series to form a resistance having a large resistance value. However, the number of series connections may be adjusted according to the required resistance value.

In addition, 6b is an N-channel transistor for input, 5b is its gate, and 8 is an input terminal of a ratio type latch.

FIG. 3 is a configuration diagram of an embodiment using a resistance of a diffusion region of a transistor as a resistance element, and FIG. 4 is an equivalent circuit diagram of the configuration shown in FIG. In FIG. 4, reference numeral 4 is a resistance obtained by connecting the resistances of six diffusion regions 4a and 4b in series.

As shown in FIG. 3, the P-channel transistor and the N-channel transistor that form the resistance element have the gate 5a of the P-channel transistor connected to the VDD wiring 10 and the gate 5b of the N-channel transistor respectively connected to the voltage. Are connected to the GND wiring 11 in which is set so that they are always off.

The resistance element is the resistance of the source or drain region shared by the two P-channel transistors sharing one of the source and the drain, and the source or the resistance shared by the two N-channel transistors sharing one of the source or the drain. Including the resistance of the drain region.

In this example, the resistances of the diffusion regions at six locations are connected in series to form a resistance having a large resistance value, but the number of series connections may be adjusted according to the required resistance value.

In each of the above embodiments, the N-channel transistor 6b is used as the input transistor connected to the input terminal 8 of the ratio type latch, but the P-channel transistor 6a may be used.

Further, in the case of constructing a ratio-type latch with a plurality of inputs, it is sufficient to provide a plurality of input transistors as in the conventional case.

Further, although the gate isolation type basic cell stage is used in the present embodiment, an oxide film isolation type basic cell stage may be used instead.

〔The invention's effect〕

According to the first aspect of the present invention, by using the basic cell of the CMOS gate array, a resistance having no voltage dependence can be obtained, and a ratio type latch can be configured.

In the second invention, since the source or drain region of the transistor is densely spread in the gate array, particularly in the gate isolation type gate array, a high resistance can be easily obtained by series connection. .

[Brief description of the drawings]

1 and 3 are configuration diagrams showing an embodiment of a semiconductor memory circuit device according to the present invention, and FIGS. 2 and 4 are FIGS. 1 and 3, respectively.
FIG. 5 is an equivalent circuit diagram of FIG. 5, FIG. 5 is a configuration diagram of a semiconductor memory circuit device having a gate array, FIG. 6 is a configuration diagram of a basic cell stage, and FIG. 7 is an equivalent circuit diagram of the basic cell stage shown in FIG. , FIG. 8 is a circuit diagram showing a conventional ratio type latch. 1 ... semiconductor chip, 2 ... input / output pad, 3 ... basic cell stage, 4a ... P-type diffusion region, 4b ... N-type diffusion region, 4 ... resistor, 5a, 5b ... gate, 5 ... ... resistor, 6a ...
P-channel transistor, 6b N-channel transistor, 7a Inverter, 8 Input terminal, 9
Resistance element, 10 ... VDD wiring, 11 ... GND wiring, 12 ... Wiring, 13 ... Contact hole In the drawings, the same reference numerals indicate the same or corresponding portions.

Claims (2)

(57) [Claims] 1. A semiconductor memory circuit device comprising a ratio type latch using a basic cell of a CMOS gate array, wherein a transistor for input and a first inverter having an input terminal connected to the source or drain of the transistor. A second inverter having an input terminal connected to the output terminal of the first inverter, and a resistance element provided between the output terminal of the second inverter and the input terminal of the first inverter. The semiconductor memory circuit device is characterized in that the resistance element is composed of gate wirings of a P-channel transistor and an N-channel transistor. 2. A semiconductor memory circuit device comprising a ratio type latch using a basic cell of a CMOS gate array, wherein an input transistor and a first inverter having an input terminal connected to the source or drain of the transistor. A second inverter having an input terminal connected to the output terminal of the first inverter, and a resistance element provided between the output terminal of the second inverter and the input terminal of the first inverter. The gate voltage of the resistance element is set so that the resistance element is in an off state, and two P elements sharing one of a source and a drain are provided.
The resistance of a shared source or drain region of a channel transistor and the shared source or drain region of two N-channel transistors whose gate voltage is set to be in an off state and which shares one of the source or drain. A semiconductor memory circuit device comprising a resistor.