JP2672769B2 - Spread spectrum receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION This invention relates to improvements in spread spectrum receivers.

[0002]

2. Description of the Related Art In recent years, a code division multiple access (CDMA) system using direct spread spectrum spread (DS / SS) communication has been attracting attention in the field of mobile communication. D for mobile communication
When S / SS communication is applied, it is desirable to perform quasi-coherent detection in the receiver because it is difficult to reproduce the carrier wave.

When performing quasi-coherent detection, the error rate characteristic deteriorates if a frequency offset exists in the local carrier. Therefore, an AFC circuit that controls the frequency of the local carrier wave or compensates for the influence of the frequency offset is essential.

The prior art will be described below with reference to FIG. FIG. 6 is a block diagram showing the configuration of a conventional spread spectrum receiver. In the figure, 100 is a quasi-synchronous detection circuit / AFC circuit, 110 is a correlator, 120 is an absolute value square circuit, and 130 is initial acquisition / synchronization tracking. A circuit, 140 is a demodulation processing circuit. Next, the operation will be described. In FIG. 6, the received SS signal is quasi-coherently detected by the quasi-coherent detection / AFC circuit 100 and becomes a complex baseband signal. The complex baseband signal is input to the correlator 110 and received SS
Correlation calculation with the PN signal used for the spread spectrum of the signal is performed to form a complex correlation signal. The complex correlation signal is input to the absolute value squaring circuit 120, and the synchronization establishment signal having the squared value of the absolute value of the complex correlation signal is output. The initial acquisition / synchronization tracking circuit 130 uses the synchronization establishment signal to generate a symbol clock synchronized with the repetition period of the PN signal included in the received SS signal and a chip clock synchronized with the chip interval of the PN signal.

On the other hand, the complex correlation signal output from the correlator 110 is also input to the demodulation processing circuit 140, demodulated according to the primary modulation method, and demodulated data is output.

Next, the configuration and operation of the quasi-synchronous detection / AFC circuit 100 will be described. Figure 7 shows conventional quasi-synchronous detection and AFC
2 is a block diagram showing the configuration of the circuit 100, in which 210 and 220 are multipliers, 230 is a voltage controlled oscillator (VCO), 240 is a phase shifter, 250 and 260 are low-pass filters, and 270 and 280 are A / Ds. A converter, 290 is an error signal generation circuit, 300 is a multiplier, 310 is an integrator,
320 is a D / A converter. Next, the operation will be described. In FIG. 7, the received SS signal is multiplied by the local carrier wave output from the VCO 230 by the multiplier 210, the high frequency component is removed by the low pass filter 250, and further converted into digital data by the A / D converter 270, and the complex base It is the real component of the band signal. Similarly, the received SS signal is sent to the phase shifter 24 by the multiplier 220.
It is also multiplied by the local carrier that is phase-shifted by π / 2 by 0, through the low-pass filter 260 and the A / D converter 280,
It is the imaginary component of the complex baseband signal.

The complex baseband signal thus obtained becomes an output signal of the quasi-coherent detection / AFC circuit 100, and at the same time, is input to the error signal generation circuit 290.

Next, the structure and operation of the error signal generating circuit 290 will be described. FIG. 8 is a block diagram showing a configuration of a conventional error signal generation circuit 290. In the figure, 400 is a deviation signal generation circuit, 410 is a conjugate circuit, 420 and 430 are multipliers, 440 and 450 are complex correlators, and 460. , 470
Is an absolute value squaring circuit, 480 is a subtractor, and 490 is a latch. Hereinafter, a process in which the error signal generation circuit 290 generates an error signal will be described. Here, the primary modulation is BPSK
And the repetition period of the PN signal used for spread spectrum is M chips, and the chip period is T _c , m (m = 1, ..., M).
Let the value of the th PN signal be u _m ∋ {-1, 1}. In addition, the symbol period of the data is T _d = MT _c , time nT _d
The value of the transmission data in (n is an integer) is a _n ∋ {-1,
1} and the angular frequency of the transmission carrier wave is ω _C.

The receiver receives a _n u _{m at} time nT _d + mT _c.
A received SS signal having a value of cos [ω _C (nT _d + mT _c )] is received.

Now, assume that the angular frequency of the local carrier used for quasi-coherent detection is ω _C + Δω and its initial phase is φ, the sampling period of A / D conversion is equal to the chip period, and there is no quantization error. Then, time nT _d + mT
The value r _{nM + m} of the complex baseband signal at _c = (nM + m) T _c is given by the following equation.

R _{nM + m} = a _n u _m exp [−j {Δω (nM + m) T _c + φ}] (1-1) In the error signal generation circuit 290 shown in FIG. A signal of exp [jω ₀ t] is output by 400. This signal is converted by the conjugation circuit 410 into a signal of exp [-jω ₀ t] which is a complex conjugate number.

The complex baseband signal input to the error signal generation circuit 290 is output by the multiplier 420 to the exp
[−jω ₀ t] is multiplied to obtain a positive frequency deviation ω
₀ (ω ₀ > 0) is given and output as a “positive deviation baseband signal”. Further, the complex baseband signal is multiplied by the signal exp [jω ₀ t] output from the deviation signal generation circuit 400 by the multiplier 430 to give a negative frequency deviation −ω ₀ , and the “negative deviation baseband signal” is given. Signal ”.

The values of the positive deviation and negative deviation baseband signals at time (nM + m) T _c are r _{pnM + m} and r _pn , respectively.
_{Assuming nnM + m} , the following relationship holds.

R _{pnM + m} = a _n u _m exp [-j {(Δω + ω ₀ ) T _c + φ}] r _{nnM + m} = a _n u _m exp [−j {(Δω−ω ₀ ) T _c + φ} (1-2) The positive deviation and the negative deviation baseband signals are input to the complex correlators 440 and 450, respectively, and the correlation calculation with the PN signal is performed to obtain the “positive deviation correlation signal” and the “negative deviation correlation signal”.
Get. Transmission data a obtained every symbol period T _d
Assuming that the values of the positive deviation and negative deviation correlation signals corresponding to _n are c _pn and c _nn , respectively, c _pn and c _nn are given by the following expressions from Expression (1-2).

[0015]

(Equation 1) Further, the absolute value square circuits 460 and 470 obtain the “positive deviation error signal” and the “negative deviation error signal” which are the squares of the absolute values of the positive deviation and negative deviation correlation signals. Finally subtractor 4
A signal obtained by subtracting the negative deviation error signal from the positive deviation error signal by 80 is latched by the latch 490 at each symbol period T _d , thereby obtaining an error signal. That is, the error signal e _n corresponding to the transmission data a _n is given by the following equation.

E _n = | c _pn │ ² − | c _nn │ ² = {sin [(Δω + ω ₀ ) MT _c / 2] / (sin [(Δω + ω ₀ ) T _c / 2])} ² − {sin [(Δω−ω ₀ ) M T _c / 2] / (sin [(Δω−ω ₀ ) T _c / 2])} ² (2-4) The value of the given frequency deviation ω ₀ is 0 <ω ₀ ≦ 2π by setting the / T _d becomes range, the error signal e _n denotes the value corresponding to the frequency offset [Delta] [omega. In FIG. 9, M = 127,
The relationship between the phase rotation amount ΔωT _d for one symbol and the error signal e _n when ω ₀ = π / T _d is shown. In this case, | Δ
It can be seen that the error signal e _n is approximately proportional to the frequency offset Δω in the range of ωT _d | ≦ π. In this way, the error signal generation circuit 290 of FIG. 8 can obtain an error signal corresponding to the frequency deviation.

Hereinafter, referring again to FIG. 7, quasi-synchronous detection / AF
The configuration and operation of the C circuit 100 will be described. The error signal e _n obtained by the error signal generation circuit 290 as described above
Is multiplied by the gain α by the multiplier 300, and then the integrator 31
Integrate with 0. This integration improves the SN ratio of the error signal. The output signal of the integrator 310 is converted into the D / A converter 32.
By controlling the VCO 230 that oscillates a local carrier wave with a voltage signal obtained by converting it into an analog signal by 0, the AFC that always sets the frequency offset Δω to 0
The operation is performed.

[0018]

Since the conventional spread spectrum receiver is constructed as described above, the AFC of the AFC is separate from the correlator used for initial acquisition / tracking of PN signal synchronization and data demodulation. The error signal generation circuit also needs a correlator, which tends to complicate the configuration, and there is a problem that downsizing and low power consumption are not easy.

The present invention has been made to solve this problem, and the same correlator can perform all of the initial acquisition / tracking of PN signal synchronization, AFC and data demodulation, and therefore the configuration is The purpose of the present invention is to obtain a spread spectrum receiver that is simple, easy to miniaturize, and has low power consumption.

[0020]

In a spread spectrum receiver according to the present invention, a received spread spectrum (SS) signal spread by a pseudo noise (PN) signal is mixed with local carriers that are orthogonal to each other to form a complex base band. A quasi-synchronous detection circuit that obtains a signal and a partial correlation that divides the complex baseband signal obtained by the quasi-synchronous detection circuit into a plurality of partial data and calculates the correlation between each of these partial data and the corresponding partial PN signal. Calculating means, an absolute value square summing means for calculating a sum of squares of absolute values of the partial correlation signals obtained by the partial correlation calculating means, and a correlation absolute value square sum signal obtained by the absolute value square summing means. Based on the detection of the repetition period of the PN signal included in the received SS signal,
Initial capture / synchronization tracking means for outputting a timing signal synchronized with the repetition cycle.

The complex conjugate signals of the partial correlation signals obtained by the partial correlation calculating means and the partial correlation signals deviated by a predetermined period from the respective partial correlation signals are subjected to complex multiplication, and the obtained complex conjugates are obtained. A complex conjugate product summing means for calculating the sum of product signals, and an error signal based on the complex conjugate product summation signal obtained by the complex conjugate product summation means and the timing signal output from the initial acquisition / synchronization tracking means. Based on the error signal output from the error signal generating means, and the error signal output from the error signal generating means.
A correction unit for correcting the frequency offset of the local carrier wave with respect to the carrier wave frequency of the S signal is further provided.

The error signal generating means includes an imaginary part separating means for separating an imaginary part of the complex conjugate product summing signal obtained by the complex conjugate product summing means, and the imaginary part separating means. An error signal output timing control means for outputting the imaginary part of the complex conjugate sum product signal as an error signal and controlling the output timing based on the timing signal output from the initial acquisition / synchronization tracking means,
It is characterized by having.

The error signal generating means includes a declination extracting means for extracting a declination angle (phase angle) of the complex conjugate product summing signal obtained by the complex conjugate product summing means, and the declination extracting means. An error signal output timing control means for outputting the argument of the obtained complex conjugate product sum signal as an error signal, and controlling the output timing based on the timing signal output from the initial acquisition / synchronization tracking means, It is characterized by having.

Further, the partial correlation summing means for calculating the sum of the respective partial correlation signals obtained by the partial correlation calculating means, and the partial correlation summation signal obtained by the partial correlation summing means are output as a combined correlation signal, Based on the composite correlation signal output timing control means for controlling the output timing based on the timing signal output from the initial acquisition / synchronization tracking means, and the composite correlation signal output from the composite correlation signal output timing control means And demodulation data generation means for generating and outputting demodulation data.

[0025]

As described above, in the present invention, the received SS signal is divided into a plurality of parts, and the partial correlation which is the correlation signal with the divided PN signal is calculated. Then, by adding the partial correlation signals, the same correlation signal as that obtained by using a single correlator is obtained, and the data is demodulated from this.
In addition, the initial acquisition of the synchronization of the PN signal is performed using the sum of squared absolute values of the partial correlation signals. The absolute value sum of squares (that is, energy sum) of the partial correlation signal has a small decrease in the peak value even when the frequency offset (frequency shift) is large, so that the peak that appears in synchronization with the repetition period of the PN signal can be reliably obtained. Can be detected, and suitable initial acquisition and tracking of PN signal synchronization can be performed. Further, when there is a frequency offset between the partial correlation signals, a phase difference occurs. That is, since the phase difference between the two partial correlation signals corresponds to the frequency offset of the local carrier, a signal corresponding to the frequency offset can be generated from the complex conjugate product between the partial correlation signals. Can be corrected.

Thus, using the same partial correlator, it is possible to obtain a signal for demodulation, a signal capable of initially capturing and tracking the synchronization of the PN signal in a wide frequency range, and an error signal for AFC operation, The circuit configuration of the entire signal processing circuit becomes extremely simple, and miniaturization and low power consumption can be achieved.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the overall configuration of the embodiment. In the figure, 10 and 12 are multipliers, 14 is a VCO, 16 is a π / 2 phase shifter, 18 and 20 are low-pass filters, and 20 and 24 are A / D converters, 30 and 32 delay circuits, 34, 36 and 38 correlators, 40, 42 and 44 absolute value square circuits, 46, 52 and 68 adders, 50 initial acquisition / synchronization tracking circuit , 56 are demodulation processing circuits, 60, 6
Reference numerals 4 and 72 are multipliers, 62 and 66 are conjugate calculators, 69 is an imaginary part separation circuit, 74 is an integrator, and 76 is a D / A converter. Next, the operation will be described. The received SS signal that has been spread in spectrum by the PN signal has two multipliers 1.
It is input to 0 and 12. A local carrier from a VCO (voltage controlled oscillator) 14 is input to the multiplier 10, and a quadrature local carrier obtained by phase-shifting the local carrier from the VCO 14 by π / 2 by a π / 2 phase shifter 16 is input to the multiplier 12. Is entered. Therefore, the quasi-coherent detection is performed by the two orthogonal local carriers. Then, the outputs of the multipliers 10 and 12 are converted into digital signals in the A / D converters 22 and 24 after the high-frequency components are removed by the low-pass filters 18 and 20, respectively. In this process, since quasi-coherent detection is performed by two orthogonal local carriers, the signals obtained from the A / D converters 22 and 24 are the real part (Re) signal and the imaginary number of the complex baseband signal. Part (Im) signal.

Next, the complex baseband signal is input to the two delay circuits 30 and 32, and the signals before and after the delay circuits 30 and 32 are input to the three correlators 34, 36 and 38. Here, the two delay circuits 30 and 32 each delay the input signal by T _d / L. And T _d
Is the repetition period of the PN signal, which is a spread signal, L is the number of correlator divisions, that is, the number of signal divisions, and in this embodiment L = 3. Therefore, a delay of T _d / 3 is performed in these two delay circuits, and the delay time is 1 of the PN signal period.
A time-continuous complex baseband signal of / 3 minutes is simultaneously supplied to the correlators 34, 36 and 38, respectively. That is, the correlators 34, 36, and 38 have the PN signal 1
The complex baseband signal for a period is divided into three to calculate the correlation. Then, the correlators 34, 36, 38
The PN signal of one cycle is divided into three parts and stored in, and a leading part is stored in the correlator 38, an intermediate part is stored in the correlator 36, and an end part is stored in the correlator 34. .

For this reason, this circuit divides the complex baseband signal for one period of the PN signal into three, and between the three divided complex baseband signals and the PN signal divided into three. Will calculate the correlation.

Then, the outputs of the correlators 34, 36 and 38 are input to the absolute value squaring circuits 40, 42 and 44, respectively, and the squares of the absolute values are calculated. Is added. Therefore, from the adder 46, a part which is a correlation signal between the signal obtained by dividing the complex baseband signal for one period of the PN signal into three and the signal obtained by dividing the PN signal of one period into three. A signal indicating the total energy of the correlation signals will be obtained.
The output of the adder 46 is input to the initial acquisition / synchronization tracking circuit 50, the peak of the signal input here is detected, and a symbol clock synchronized with the period (symbol period) of the PN signal is generated. It That is, the adder 4
Since the peak of the signal output from 6 appears in synchronization with the cycle of the PN signal, it is possible to perform the initial capture of the synchronization of the PN signal by detecting this peak. Then, after the initial acquisition is achieved, the process shifts to the synchronous tracking operation, and the symbol clock that always follows the PN signal is generated.

Here, for the initial acquisition in the initial acquisition / synchronization tracking circuit 50, as shown in FIG. 2, an adder 50a for performing cyclic addition, a frame memory 50b for storing the addition result of one symbol period, and the addition result There is a method of using the peak detection circuit 50c that detects the peak of the signal. That is, according to this circuit, since the output of the frame memory 50b is the addition result of one symbol period before, the adder 50a performs cumulative addition (so-called cyclic addition) in one symbol period. Since a peak appears in the synchronization establishment signal input to the adder 50a in synchronization with the repetition period (that is, the symbol period) of the PN signal, cumulative addition of peaks is performed by this cyclic addition and the SN ratio is improved. , The peak detection becomes more reliable. Initial detection is performed by detecting a peak synchronized with this PN signal.

On the other hand, the outputs of the correlators 34, 36 and 38 are input to the adder 52 where they are added. Therefore, 3
The partial correlation signals calculated by dividing into two are added to obtain P
The signal is the same as the correlation signal for one cycle of the N signal. Then, this signal is input to the latch circuit 54 and latched based on the symbol clock from the initial acquisition / synchronization tracking circuit 50. That is, the correlation signal is latched at the point of highest energy, and the despread signal is output from the latch circuit 54.

The output signal of the latch circuit 54 is input to the demodulation processing circuit 56, where a temporary modulation method (for example,
Demodulation processing corresponding to (QPSK modulation, etc.) is performed, and demodulated data is obtained.

On the other hand, the output of the correlator 34 is input to the multiplier 60. The output of the correlator 36 is also input to the multiplier 60 via the conjugate calculator 62 that outputs the complex conjugate number, and the two input signals are multiplied. The output of the correlator 36 is input to the multiplier 64, and the multiplier 6
The output of the correlator 38 is also input to 4 via the conjugate calculator 66, and is multiplied by two input signals. In this way, in the multipliers 60 and 64, the complex conjugate product operation between the partial correlation signals from the adjacent partial correlators is performed.

The outputs of the multipliers 60 and 64 are input to the adder 66 and added there. The output of the adder 68 is inputted to the imaginary part separation circuit 69, this signal is input to the latch circuit 70 is latched in response to the symbol clock, the error signal e _n is obtained.

Therefore, the multiplier 72 multiplies the error signal e _n by a predetermined gain α, and the integrator 74 integrates the signals to average them, and the D / A converter 76 converts the analog signals into analog voltage signals. Supply. In this manner, VCO 14 is for correcting the oscillation frequency in response to the error signal e _n, the frequency offset of the local carrier is resolved for the carrier frequency of the received SS signal. in this way,
The receiver uses the same partial correlator for all initial acquisition and tracking of PN signal synchronization, AFC and data demodulation. Therefore, the circuit configuration is extremely simple, and downsizing and low power consumption are easy.

Characteristics of Correlation Signals by Partial Correlators Here, the partial correlation signals obtained from the partial correlators 34, 36 and 38 will be described. Here, the primary modulation is BPS
K, the repetition period of the PN signal used for spread spectrum is M chips, the chip period is T _c , and the m-th (m = 1,
, M), the value of the PN signal is u _m ∋ {-1, 1}.
Further, the symbol period of the data is T _d = MT _c , time nT
The value of the transmission data in _d (n is an integer) is a _n ∋ {-
1, 1} and the angular frequency of the transmission carrier wave is ω _c .

The receiver receives a _n u _{m at} time nT _d + mT _c.
A received SS signal of cos [ω _c (nT _d + mT _c )] is received, quasi-coherent detection and A / D conversion are performed, and a complex baseband signal is obtained. The sampling period of the A / D converter is equal to the chip period and there is no quantization error.

Assuming that the angular frequency of the local carrier used for the quasi-coherent detection is ω _c + Δω and its initial phase is φ, the value r of the complex baseband signal at time nT _d + mT _c = (nM + m) T _{c nM + m} is given by the following equation.

R _{nM + m} = a _n u _m exp [-j {Δω (nM + m) T _c + φ}] (2-1) In a normal DS / SS receiver, this complex baseband signal is complex The correlation signal is input to the correlator and the correlation calculation with one cycle of the PN signal is performed to obtain the correlation signal. When the value of the correlation signal corresponding to the transmission data a _n is c _n , c _n is given by the following equation.

[0041]

(Equation 2) Therefore, the energy E of the correlation ^{_{signal, E = | c n | 2}} = {sin [ΔωM T c / 2]} 2 / {sin [ΔωT c / 2]} becomes 2 (2-3). From this, it can be seen that the energy of the correlation signal obtained from a single correlator decreases according to the frequency offset Δω.

On the other hand, when the correlator is divided into L equal parts (L is a divisor of M), the value of the partial correlation signal output from the k-th (k = 1, ..., L) partial correlator is If you _say c _nk ,

(Equation 3) Becomes Clearly at this time

(Equation 4) It is. That is, the sum of the partial correlation signals output from each partial correlator is equal to the correlation signal obtained from a single correlator. Therefore, in FIG. 1 where the correlator division number L = 3, the output of the adder 52 is the same as the correlation signal obtained by a single correlator.

On the other hand, the total energy E _T of the partial correlation signal obtained from each partial correlator is

(Equation 5) Becomes

Here, comparing equations (2-3) and (2-6), the effect of frequency offset is 1 when a correlator divided into L equal parts is used as compared with a single correlator. It turns out that it becomes / L times.

FIG. 3 shows a graph in which the energy of the correlation signal obtained from a single correlator and a correlator that is divided into three equal parts in the case of M = 63 is normalized by the value of Δω = 0. From the figure, the output becomes 0 with a single correlator | Δω | = 2π
Also in the case of / T _d , it is found that the energy loss can be suppressed to a small extent by using the correlator divided into three parts.

Therefore, by using the sum of the squares of the absolute values of the partial correlation signals obtained from the partial correlators, the energy loss is large when a single correlator is used.
Initial acquisition is possible even in the presence of large frequency offsets that make initial acquisition of the N signal difficult.

That is, the correlator division number L = 3 in FIG.
, The partial correlations are respectively obtained by the correlators 34, 36 and 38, and the sum of the absolute value squares is calculated by the absolute value square circuit 4
By calculating at 0, 42, 44 and the adder 46, the signal shown in Expression (2-8) is obtained. Therefore, based on this signal, the initial acquisition / synchronization tracking circuit 50 performs initial acquisition and tracking of the synchronization of the PN signal, and a symbol clock is generated. Then, the latch 54 latches the output of the adder 52 (that is, the correlation signal for one cycle of the PN signal) in synchronization with the symbol clock, whereby a signal obtained by despreading the received SS signal is obtained.

By thus dividing and obtaining the correlation signal, not only normal data demodulation but also PN signal synchronization acquisition can be performed even when the frequency offset is large.

Generation of Error Signal Next, a method of generating an error signal according to the frequency offset in this embodiment will be described.

Equation (2-4) indicates that the phase difference between the partial correlation signals obtained from two adjacent partial correlators among the L equalized correlators is ΔωMT _c / L. . Therefore, by detecting this phase difference, the magnitude of the frequency offset can be obtained.

The principle of differential detection can be applied to the detection of the phase difference between the partial correlation signals. That is, the complex conjugate of the (k−1) th (k = 2, ..., L) partial correlator output and the kth
The th partial correlator output may be multiplied. If the value of this multiplication output is z _nk ,

(Equation 6) Becomes Here, “*” means complex conjugate. (L-1) multiplication outputs z _nk are simultaneously obtained for one symbol data. That is, in FIG. 1 in which the correlator division number L = 3, two multiplication outputs z _n2 and z _n3 are obtained in the multipliers 60 and 64. Then, in order to improve the SN ratio of the error signal, the adder 68 adds all these multiplication outputs.

Assuming that the value of the sum signal output from the adder 68 is Z _n ,

(Equation 7) It is.

Then, the imaginary part separating circuit 69 outputs the imaginary part of the sum signal Z _n as an error signal. That is, the value e _{n of the} error signal is given by the following equation.

E _n =-(L-1) sin [ΔωM T _c / L] · {sin [ΔωM T _c / (2L)]} ² / {sin [ΔωT _c / 2]} ² (3-3) In FIG. 4, L (L-1) / when M = 63 and L = 3
The graph of the error signal normalized by M is shown. From this, it can be seen that an error signal corresponding to the value of the frequency offset can be obtained by the above signal processing.

However, the error signal e _n is the symbol period T
Since it is obtained for each _d , the final error signal is obtained by latching the output of the imaginary part separation circuit 69 in the latch circuit 70 with the symbol clock output from the initial acquisition / synchronization tracking circuit 50.

In the above embodiment, the number of correlator divisions L = 3
Although the case is shown, L may be 2 or more. Further, although the case where BPSK modulation is used as the primary modulation method is shown, other modulation methods (for example, QPSK) may be used.

Further, the sampling period for A / D conversion may be an integral fraction of the chip interval.

Modified Example The same effect can be obtained by using the phase angle of the total sum signal Z _n as an error signal. FIG. 5 shows an example of the configuration when the number of correlator divisions L = 3. In FIG. 5, the imaginary part separation circuit 69 of FIG.
Instead, a phase angle detector 80 is adopted. The phase angle detector 80 extracts and outputs a deviation angle (that is, a phase angle) of the sum signal Z _n . Therefore, the value of the output of the phase angle detector 80 becomes _{arg Z n = -ΔωM T c /} L. That is, since the error signal according to the value of the frequency offset Δω can be obtained also with the configuration of FIG. 5, the same effect as the configuration of FIG. 1 can be obtained.

[0059]

As described above, according to the present invention,
By using the partial correlator, it is possible to perform all the synchronous acquisition / tracking of the PN signal, the AFC and the data demodulation by the output of the same partial correlator. That is, the correlator for data demodulation and PN signal synchronization acquisition / tracking can be used as the AFC correlator. Therefore, since the receiver does not need a correlator dedicated to AFC, the circuit configuration is extremely simple,
Therefore, it is easy to reduce the size and power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment.

2 is a block diagram showing a configuration example of an initial acquisition unit in an initial acquisition / synchronization tracking circuit 50. FIG.

FIG. 3 is a diagram showing frequency offset characteristics of correlation signal energy.

FIG. 4 is a diagram showing characteristics of an error signal generated from a partial correlator.

FIG. 5 is a block diagram showing an overall configuration of a modified example.

FIG. 6 is a block diagram showing an overall configuration of a conventional spread spectrum receiver.

FIG. 7 is a block diagram showing a configuration of a conventional quasi-synchronous detection / AFC circuit 100.

FIG. 8 is a block diagram showing a configuration of a conventional error signal generation circuit 290.

FIG. 9 is a characteristic diagram showing a characteristic of a conventional error signal.

[Explanation of symbols]

 10, 12 Multiplier 14 VCO 16 π / 2 Phase shifter 18, 20 Low-pass filter 20, 24 A / D converter 30, 32 Delay circuit 34, 36, 38 Correlator 40, 42, 44 Absolute square circuit 46, 52, 68 Adder 50 Initial acquisition / synchronization tracking circuit 56 Demodulation processing circuit 60, 64, 72 Multiplier 62, 66 Conjugate calculator 69 Imaginary part separation circuit 74 Integrator 76 D / A converter 80 Phase angle detector

Claims (5)

(57) [Claims] 1. A quasi-synchronous detection circuit which obtains a complex baseband signal by mixing local spread carriers which are orthogonal to each other to a received spread spectrum (SS) signal which is spread spectrum by a pseudo noise (PN) signal, and the quasi-synchronous detection circuit. The complex baseband signal obtained by dividing the complex baseband signal into a plurality of partial data, and calculating the correlation between each of the partial data and the corresponding partial PN signal, and each of the partial correlation calculating means. Repetition of the PN signal included in the received SS signal based on the absolute value square sum means for calculating the sum of the squares of the absolute values of the partial correlation signals and the correlation absolute value square sum signal obtained by the absolute value square sum operation means. Spread spectrum characterized by including an initial acquisition / synchronization tracking means for detecting a cycle and outputting a timing signal synchronized with the repetition cycle. Receiving machine. 2. A quasi-synchronous detection circuit for obtaining a complex baseband signal by mixing local spread carriers which are orthogonal to each other to a received spread spectrum (SS) signal which is spread spectrum by a pseudo noise (PN) signal, and the quasi-synchronous detection circuit. The complex baseband signal obtained by dividing the complex baseband signal into a plurality of partial data, and calculating the correlation between each of the partial data and the corresponding partial PN signal, and the partial correlation calculating means. Absolute value sum of squares means for calculating the sum of the squares of the absolute values of the partial correlation signals, and based on the correlation absolute value sum of squares signals obtained by the absolute value sum of squares means, of the PN signals included in the received SS signal It is obtained by the initial acquisition / synchronization tracking means for detecting the repetition period and outputting the timing signal synchronized with the repetition period, and the partial correlation calculation means. A complex conjugate product summation means for performing a complex multiplication of a complex conjugate signal of the partial correlation signals and a partial correlation signal deviated from each of the partial correlation signals by a predetermined period, and calculating a sum of the obtained complex conjugate product signals; An error signal generating unit for generating and outputting an error signal based on the complex conjugate product summing signal obtained by the complex conjugate summing unit and the timing signal outputted from the initial acquisition / synchronization tracking unit, and the error signal generating unit. A spread spectrum receiver comprising: a correction unit that corrects a frequency offset of the local carrier with respect to a carrier frequency of the received SS signal based on the output error signal. 3. The error signal generating means includes an imaginary part separating means for separating an imaginary part of the complex conjugate product summing signal obtained by the complex conjugate product summing means, and the imaginary part separating means. An error signal output timing control means for outputting the imaginary part of the complex conjugate product sum signal as an error signal and controlling the output timing based on the timing signal output from the initial acquisition / synchronization tracking means. The spread spectrum receiver according to claim 2, wherein 4. The error signal generating means includes a declination extracting means for extracting a declination angle (phase angle) of the complex conjugate product summing signal obtained by the complex conjugate product summing means, and the declination extracting means. An error signal output timing control means for outputting the argument of the obtained complex conjugate product sum signal as an error signal, and controlling the output timing based on the timing signal output from the initial acquisition / synchronization tracking means, The spread spectrum receiver according to claim 2, further comprising: 5. A quasi-synchronous detection circuit for obtaining a complex baseband signal by mixing a received spread spectrum (SS) signal spread by a pseudo noise (PN) signal with local carriers orthogonal to each other, and the quasi-synchronous detection circuit. The complex baseband signal obtained by dividing the complex baseband signal into a plurality of partial data, and calculating the correlation between each of the partial data and the corresponding partial PN signal, and each of the partial correlation calculating means. Absolute value sum of squares means for calculating the sum of squared absolute values of the partial correlation signals, and repetition of the PN signal included in the received SS signal based on the correlation absolute value sum of squares signal obtained by the absolute value square summation means. An initial acquisition / synchronization tracking means for detecting a cycle and outputting a timing signal synchronized with the repetition cycle, and each part obtained by the partial correlation calculation means. A complex conjugate product summation means for performing a complex multiplication of a complex conjugate signal of the correlation signal and a partial correlation signal shifted by a predetermined period from each of the partial correlation signals, and calculating the sum of the obtained respective complex conjugate product signals; An error signal generating means for generating and outputting an error signal based on the complex conjugate product summing signal obtained by the conjugate product summing means and the timing signal outputted from the initial acquisition / synchronization tracking means; and the error signal generating means based on the error signal output, a correction means for correcting the frequency offset of the local carrier relative to the carrier frequency of the received SS signals, calculates the sum of the partial phase No. SekiShin obtained by the partial correlation operation means The partial correlation summing means and the partial correlation summation signal obtained by the partial correlation summing means are output as a combined correlation signal, and the output timing thereof is the above-mentioned first. Synthetic correlation signal output timing means for controlling based on the timing signal output from the acquisition / synchronization tracking means, and generating and outputting demodulation data based on the synthetic correlation signal output from the synthetic correlation signal output timing control means And a demodulation data generating means for performing the same.