JP2669296B2 - Sample hold circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a high speed and high precision sample and hold circuit.

[0002]

2. Description of the Related Art As a conventional high-speed sample-and-hold circuit, a diode bridge type circuit shown in FIG. 8 has been used.

An input terminal is connected to a node N1 of a diode bridge.
1, the contact N12 is commonly connected to the input end of the voltage follower 12 and the other end of the hold capacitor 11, one end of which is connected to the low power supply terminal GND, and the output end of the voltage follower 12 is the output terminal of the level shift circuit. And A PNP-type bipolar transistor (hereinafter, referred to as a PNP transistor) 14 and an NPN-type bipolar transistor (hereinafter, referred to as a PNP transistor)
An NPN transistor) 12 and a node N15 of the diode bridge are commonly connected. Further, the PNP transistor 15, the NPN transistor 13, and the node N16 of the diode bridge are commonly connected. The emitter terminals of the PNP transistor 14 and the PNP transistor 15 are commonly connected,
Further, a low current source 17 is connected to the higher power supply terminal Vcc. PNP transistor 12 and NPN transistor 13
Commonly connected to the emitter terminals of the
A low current source 18 is connected between Level shift circuits 22 and 24 are connected in series between the base terminals of the PNP transistor 14 and the PNP transistor 12, and level shift circuits 23 and 25 are connected in series between the base terminals of the PNP transistor 15 and the NPN transistor 13, respectively. The node N13 of the level shift circuits 22 and 24 is connected to the level shift circuits 23 and 25 via the input buffer 20 and the inverter 21.
The node N14 is configured to receive the sampling clock signal CLK via the input buffer 20.

In this circuit, in the timing chart of FIG. 7 , when the sampling clock signal CLK becomes high level, the node N13 becomes low level, the node N14 becomes high level, the PNP transistor 14 and the NPN transistor 13 become conductive, and the node N15 becomes high level. , Node N1
6 becomes low level. As a result, the diodes 16 to 19
Is biased in the forward direction, and the input level (node N11) and node N12 are clamped by diodes 16 and 17 to the same voltage level, and the hold capacitor 11 is charged and discharged. After that, when the sampling clock signal CLK becomes low level, the node N13 becomes high level, the node N14 becomes low level, the NPN transistor 12 and the PNP transistor 15 are turned on, and the contact N15.
At a low level and the node N16 at a high level. As a result, all diode bridges 16-19 are reverse biased, and the input level and node N12 are isolated. Therefore, the node 14 holds the potential at the time of sampling by the charge charged in the hold capacitor 11, and the potential is output via an output buffer such as the voltage follower 12.

[0005]

[SUMMARY OF THE INVENTION] In the conventional method using the above-mentioned diode bridge, NP 8 during holding
There is a problem in that the N bipolar transistor 12 and the PNP bipolar transistor 15 are saturated, and the time for shifting to the sampling mode (acquisition time) is increased. Furthermore the current at the time of sampling flow through the PNP transistor 14 and NPN transistor 13 shown in FIG. 8,
The current is shunted to the two paths of the diode bridge (the paths of the diodes 16 and 18 and the paths of the diodes 17 and 19 shown in FIG. 8 ), and the hold capacitor 11 cannot be charged and discharged at high speed. When the current is increased for fast charging, the diodes 16, 1
The current flowing through 8 also increases, resulting in an increase in power consumption. In addition, when the sampling mode is changed to the hold mode, the voltage changes at the nodes 15 and 16 are caused by the diode 1
Output node N via the coupling of the junction capacitances 7 and 19
12 (feedthrough). In this conventional example, as shown in FIG. 7 , the node N15 changes to a constant low level, and the node N16 changes to a constant high level. Therefore, the amount of change in the voltage level of the nodes N15 and N16 differs depending on the level of the data to be sampled. As a result, different feedthroughs occur depending on the level of the sampling data, and the accuracy of the sampling voltage becomes low.

A diode bridge type circuit shown in FIG. 9 has also been used as a high-speed sample-and-hold circuit (transistor technology, SPECIAL NO. 16, page 103). In this circuit, when both CLKA and CLKB are low level inputs, the transistors 35 and 38 are turned on and the transistors 36 and 37 are turned off, so that the diode arrays 31 to 34 are forward biased and the hold capacitor 39 is supplied with the same voltage as VIN. Is applied, data can be sampled, and at the time of high level input to both CLKA and CLKB, the transistors 35 and 38 are turned off, and the transistors 36 and 37 are turned on. Therefore, the diode string is reverse biased and the input VIN and the hold capacitor. Are separated, the potential of the hold capacitor is maintained, and data can be held. However, this method has a drawback in that the bias current (currents of the constant current sources 41 and 42) is shunted to the diode bridge arrays 31, 33 and 32, 34, so that the charging and discharging of the hold capacitor 39 is delayed.

This diode bridge type improved system is I
SSCC'92 (ISSCC DIGEST OF T
ECHNICAL PAPERS, PP200-20
1, Feb. 1992). This circuit has the configuration shown in FIG. In this case CLKA
When a high level input is input to transistors, transistors 52 and 50
N, the transistors 53 and 51 are turned off, so that the diode bridge rows 55 and 54 are forward-biased, and the diode bridge rows 56 and 57 are reverse-biased. Accordingly, if the forward voltage of the EB junction of the transistor 50 (hereinafter referred to as “VF”) and the forward voltage of the diode 54 are the same, VIN is applied to the hold capacitor 58.
Is applied. On the other hand, hold capacitor 59
The side is separated from the input VIN, and data is held. Also, when a low level input is input to CLKA, the transistors 52 and 50 are turned off, and the transistors 53 and 51 are
Is turned ON, the diode rows 56 and 57 are forward-biased, and the diodes 54 and 55 are reverse-biased.
Contrary to the previous example, VIN on the hold capacitor 59
And the hold capacitor 58 is connected to V
Separated from IN. In this circuit system, the problem of shunting of the current to the diode bridge row, which has been a problem in the conventional example described above, is avoided. However, the current for charging and discharging the hold capacitor is determined by the bias current IC, and only a maximum of 2 IC / 3 can be supplied.
Therefore, it is necessary to increase the bias current in order to increase the charging / discharging speed, and there is a problem that power consumption increases.

[0008]

A feature of the present invention is that in a sample and hold circuit for accumulating electric charge in a hold capacitor and holding a potential, a base of a first PNP type bipolar transistor having a collector terminal connected to a lower power supply terminal. The terminal and the base terminal of the first NPN bipolar transistor whose collector terminal is connected to the high-potential power terminal are connected to serve as an input terminal for a sample hold signal, and the emitter terminal of the first PNP bipolar transistor is a collector terminal. Is the second NPN connected to the higher power supply terminal.
PN having a collector terminal connected to a lower power supply terminal and an emitter terminal of the first NPN bipolar transistor connected to a base terminal of the first bipolar transistor.
A hold capacitor which is connected to the base terminal of a P-type bipolar transistor, and whose one end is connected to the emitter terminal of the second PNP-type bipolar transistor and the emitter terminal of the second NPN-type bipolar transistor. End and the input terminal of the voltage follower are commonly connected, the output of the voltage follower is used as the output terminal of the sample hold signal, and the collector terminal is connected to the low power supply terminal. The base terminal of the third PNP bipolar transistor. And a collector terminal connected to the base terminal of a third NPN bipolar transistor whose high-potential power supply terminal is connected, and the emitter terminal of the third NPN bipolar transistor is connected to the first constant current source for pulling down and Connect to the base terminal of the second NPN bipolar transistor Then, the emitter terminal of the third PNP type bipolar transistor is connected to the second constant current source for pull-up and the base terminal of the second PNP type bipolar transistor, and the emitter terminal of the first NPN type bipolar transistor is connected. A third constant current source that pulls down only at the time of sampling is connected to the emitter terminal, and the first P
A fourth constant current source that pulls up only at the time of sampling is connected to the emitter terminal of the NP-type bipolar transistor.

The third constant current source, which is connected to the emitter terminal of the first NPN bipolar transistor and pulls down only at the time of sampling, has fourth and fifth emitter terminals commonly connected to a fifth constant current source. A first sampling clock composed of an NPN bipolar transistor, the collector terminal of the fourth NPN bipolar transistor is connected to the emitter terminal of the first NPN bipolar transistor, and the base terminal has a high level only when sampling. A signal, a collector terminal of a fifth NPN-type bipolar transistor is connected to a higher power supply terminal, and a constant voltage at an intermediate level of the first sampling clock signal is input to a base terminal as a reference signal. Emi of the first PNP bipolar transistor It is connected to the data terminal, and the fourth and fifth emitter terminal of said fourth constant current source to pull up only the sampling period is commonly connected to a constant current source 6
Second PNP bipolar transistor, the collector terminal of the fourth PNP bipolar transistor is connected to the emitter terminal of the first PNP bipolar transistor, and the base terminal has a second sampling level that is a constant level only during sampling. A clock signal is input, a collector terminal of the fifth PNP-type bipolar transistor is connected to a lower power supply terminal, and a constant voltage at an intermediate level of the second sampling clock signal is input to a base terminal as a reference signal. it can.

A plurality of sample and hold circuits,
At least one circuit is a sample-and-hold circuit configured to always perform a sampling operation, and includes a fifth NPN-type bipolar transistor, a fifth PNP-type bipolar transistor, a fifth constant current source, and a sixth constant current source. It can be shared by a plurality of sample and hold circuits.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a timing chart of the circuit operation.

An input terminal is connected to the base terminals of the first PNP transistor 6 and the second NPN transistor 1.
The collector terminal of the first PNP transistor 6 is commonly connected to the lower power supply terminal GND, and the emitter terminal is commonly connected to the fourth constant current source I4 and the base terminal of the second NPN transistor 2 (node N1). The collector terminal of the first PNP transistor 1 is connected to the lower power supply terminal GND, and the emitter terminal is commonly connected to the third constant current source I3 and the base terminal of the second PNP transistor 7 (node N2). The collector terminal of the second NPN transistor 2 is connected to the high potential power supply terminal Vcc
The collector terminals of the PNP transistors 7 are connected to the low-potential power supply terminal GND, and the respective emitter terminals are connected to the other end of the hold capacitor 11 whose one end is connected to the low-potential power supply terminal GND and the input end of the voltage follower 12 ( Node N3). The output terminal of the voltage follower 12 is commonly connected to the output terminal of the level shift circuit and the base terminals of the third PNP transistor 10 and the third NPN transistor 5 (node N4).

The emitter terminal of the third PNP transistor 10 is connected to the second constant current source I2 connected to the high potential power supply terminal Vcc and the node N2, and the third NP is connected.
The emitter terminal of the N transistor 5 is connected to the lower power supply terminal GND.
Are connected to a first constant current source I1 and a node N1. Further, the third constant current source I3 includes a third NPN transistor 3 for inputting a sampling clock signal CLK to a base terminal and a fifth NPN transistor 4 for inputting a constant voltage VR2 at an intermediate level of the sampling clock signal CLK. A fifth constant current source I5 connected between the emitter terminal and the lower power supply terminal GND is commonly connected, and a collector terminal of the fifth NPN transistor 4 is connected to the higher power supply terminal Vcc.
The fourth constant current source I4 has an emitter of a fourth PNP transistor 8 for inputting an inverted sampling clock signal CLK to a base terminal and an emitter of a fifth PNP transistor 9 for inputting a constant voltage VR1 at an intermediate level of the inverted sampling clock signal CLK. The sixth constant current source I6 connected between the terminal and the high-potential power supply terminal Vcc is commonly connected, and the collector terminal of the fifth PNP transistor 9 is connected to the low-potential power supply terminal GND.

When the sampling clock signal CLK is input (CLK: high level, inverted CLK: low level) NP
N transistor 3 and PNP transistor 8 are ON
The node N1 is connected from the input level (DIN) to the forward voltage between the base and the emitter of the PNP transistor 6 (hereinafter "V
It is pulled up to a level higher by "F"), and the node N2 is pulled down from the input level to a level lowered by the VF of the NPN transistor 1. At the same time, the node N3 is lower than the node N1 by the VF of the NPN transistor 2. And at the same time, it is clamped from the node N2 to a level higher by VF of the PNP transistor 7.
VF of P transistors 6 and 7 and NPN transistor 1
By setting VF of 2 to the same value, the holding capacitor 11 is charged and discharged by the currents of the NPN transistor 2 and the PNP transistor 7 until the node N3 becomes the same potential as the input level (DIN). The level of the node N3 becomes the output of the sample hold signal via the output buffer such as the voltage follower 12 and at the same time becomes the base input of the NPN transistor 5 and the PNP transistor 10.

Here, the potential of the emitter terminal (N2) of the PNP transistor 10 is lower than the base potential, and
Since the potential of the emitter terminal (N1) of the N-transistor 5 is higher than the base potential, both transistors become non-conductive, and the constant current sources I1 and I2 connected to the respective emitter terminals are from the constant current sources I5 and I6 side. It is supplied via the PNP transistor 8 and the NPN transistor 3. On the other hand, when the sampling clock signal CLK is turned off (CLK; low level, inversion CLK; high level), the node N1 is cut off from the constant current source I6, and from the held level of the node N3 (node N4) by the constant current source I1. The voltage is lowered to a level lower by the VF of the NPN transistor 5. After that, the constant current source I1 is supplied with current from the NPN transistor 5 side. Similarly, the node N2 is disconnected from the constant current source I5, and is pulled up from the node N3 to a level higher by VF of the PNP transistor 10 by the constant current source I2;
2 and the emitter and base of the PNP transistor 7 are reverse-biased, the node N3 is isolated from the input terminal, and the node N3 is the charge accumulated in the hold capacitor 11 and holds the potential at the time of sampling. can do. The potential is output via a voltage follower 12 having a high input impedance.

The PNP transistor 9 and the NPN transistor 4 guarantee that all the sample and hold circuits are not operating when the sampling clock signal CLK is not input to any of the sample and hold circuits. , The base terminal of the NPN transistor 4 needs to be supplied with an intermediate voltage level between the high level and the low level of the inverted sampling clock signal CLK, and the base terminal of the NPN transistor 4 must have a voltage level between the low level and the intermediate level of the sampling clock signal CLK There is. However, since this is not directly related to the operation of the sample hold itself, it is provided as necessary.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

The level shift circuit has n blocks (n
Indicates a case where one or more natural numbers are used. N level shift circuits are connected in parallel between the fourth constant current source I6 and the third constant current source I5, and are connected to the fourth constant current source I6 and the fifth constant current source I5. The fifth PNP transistor 9 and the fifth NPN transistor 4 are configured to share one each as a whole.

The second embodiment has the same basic operation principle as that of the first embodiment, so the description thereof will be omitted. However, there are a plurality of sample hold circuits, each of which receives an output signal from a shift register or the like. , If it works sequentially,
Since only one circuit block is performing the sampling operation, the current source I6 and the current I5 for pulling up and pulling down the node N1 and the node N2 are made common, and the current consumption of the entire block of the sample hold circuit is reduced. Has the effect of reducing

FIG. 4 is a circuit diagram showing a third embodiment of the present invention.

In FIG. 4, NPN transistors 1, 2
And PNP transistors 8 and 9 form a current amplifier. As a current source of the current amplifier circuit, a current switch circuit including NPN transistors 3 and 4 and a constant current source 18 and PNP transistors 10 and 11 and a constant current source 20 The output of the current amplifier circuit (node N3) in which the current switch circuit is used is connected to the input of the hold capacitor 14 and the voltage follower 15, and the output of the voltage follower 15 becomes the output of the sample hold circuit. , 10 forming a feedback circuit consisting of an emitter follower
Input to the base terminal of. Transistors 5, 10
Are connected to the base terminals of transistors 2 and 8, respectively, to perform a feedback operation. On the other hand, the current source of each feedback circuit is a transistor 6.7.
And a current switch composed of transistors 12 and 13 and a constant current source 21.

[0022] The high-level, during holding at the time of service down pull the CLKA enter the sampling clock signal goes low, the VRA to enter the intermediate level of the constant voltage of CLKA. On the other hand, CLKB has a low level when sampled,
At the time of holding, a sampling clock signal which becomes a high level is inputted, and a constant voltage of an intermediate level of CLKB is inputted to VRB.

At the time of sampling, the transistors 3 and 10 in the current source circuit for current amplifier are turned on and the transistors 4 and 11 are turned off, so that the currents of the constant current sources 18 and 20 flow through the transistors 3 and 10, respectively, and the current amplifier Operate. Transistors 1, 2, which form a current amplifier
If the VFs of 8 and 9 are set to be the same, when VIN is input, the nodes N1 and N2 become VIN + VF and V
IN-VF, and the output N3 of the current amplifier becomes VIN. Here, the resistors 16 and 17 show another embodiment of the present invention, and have a function of suppressing a DC-like through current flowing through the transistors 2 and 8 due to variations in VF and oscillation in a transient period. The push-pull circuit composed of the transistors 2 and 8 can charge and discharge the hold capacitor 14 at high speed. The voltage of the hold capacitor is output via the voltage follower 15. In the current source circuit of the feedback circuit, the transistors 6 and 12 are OFF and the transistors 7 and 13 are ON, so that the transistors 5 and
Since no current is supplied to the node 10, the EB junctions of the transistors 5 and 10 are reverse-biased, and the nodes N1 and N
It does not affect the potential of 2.

At the time of hold, the transistors 3 and 10 in the current amplifier power supply circuit are turned off, and the transistors 4 and 1
Since 1 is turned on, the currents of the constant current sources 18 and 20 flow through the transistors 4 and 11, respectively, and the current amplifier does not operate. Therefore, the input and the hold capacitor are separated. In the current source circuit of the feedback circuit, the transistors 6 and 12 are ON and the transistors 7 and 13 are OFF.
Since the current is supplied to the transistors 10, the transistors 5 and 10 operate as emitter followers,
The emitter terminals of 0 are N3-VF and N3 + VF, respectively. Therefore, node N1 = N3-VF, N2 = N3 + V
F, the EB junction of the transistors 2 and 8 in the current amplifier is reverse-biased, and the effect of data through can be eliminated.

In the first embodiment, in order to shorten the hold mode settling time, it is necessary to increase the current values of the constant current sources 19 and 21 in the figure. However, if this current value is increased, transistors 2 and
The currents of the current sources 21 and 19 are shunted from the currents of the current sources 18 and 20, respectively, which are the currents supplied to the transistor 8, and the effective current supplied to the transistors 2 and 8 becomes small, so that the sampling acquisition time becomes long. However, in this embodiment, the current sources 19 and 21 of the feedback circuit are not supplied from the constant current sources 18 and 20 because the current sources 19 and 21 of the feedback circuit are supplied directly from the power supply or GND via the transistors 7 and 13 at the time of sampling. As a result, the high-speed hold and the high-speed sampling, which are problems in the conventional circuit, can be controlled independently, so that the performance of the sample-and-hold circuit can be easily improved.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention. This embodiment is an embodiment applicable to a case where a plurality of sample circuits as shown in the third embodiment are provided and further these receive the output of the shift register and continuously sample the data. is there. In the present embodiment, the current sources 18, 19, 20, 21 forming the current source circuit for the current amplifier and the feedback circuit in the fourth embodiment, and the reference side transistor 4 of the current switch,
7, 11, and 13 are shared by a plurality of sample and hold circuits. According to this embodiment, by sharing the current source, there is an effect that the current can be greatly reduced as compared with the case where the current sources are individually provided.

[0027]

As described above, in the sample and hold circuit of the present invention, the charging and discharging of the hold capacitor 11 is performed by N
Since the operation is performed by the push-pull circuit formed by the PN transistor 2 and the PNP transistor 7, there is an effect that the speed can be increased. During hold, the NPN transistor 2 and the PNP
The base-emitter diode of transistor 7 is just V
It will be reverse biased by F, but the nodes N1, N
The change of 2 is constant regardless of the data level.
Therefore, by making the capacitances of the base-emitter junctions of the NPN transistor 2 and the PNP transistor 7 substantially the same, the influence of feedthrough to the node N3 due to the potential change of the nodes N1 and N2 can be suppressed.

Even if the base-emitter junction capacitances of the NPN transistor 2 and the PNP transistor 7 are different, the amount of feedthrough is constant regardless of the level of the input data. It will be easy. Also, once NPN transistor 2 and PNP transistor 7 are turned off, node N3
Is completely isolated, the effect of data through is completely eliminated, and there is also an effect that the voltage can be held with high accuracy.

Further, the current source of the current amplifier that operates at the time of sampling and the constant current source of the feedback circuit that operates at the time of holding are formed by current switches that operate in opposite phases, so that the current of the current amplifier that determines the speed of the sampling operation is obtained. The value of the current source of the feedback circuit that determines the source and the speed of the hold operation can be set independently, and a higher-speed sample and hold circuit can be realized.

Therefore, the use of the present invention has an effect that a high-speed and high-accuracy sample-and-hold circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a sample hold circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment of the sample hold circuit of the present invention.

FIG. 3 is a circuit diagram showing a second embodiment of the sample hold circuit of the present invention.

FIG. 4 is a circuit diagram showing a third embodiment of the sample hold circuit of the present invention.

FIG. 5 is a timing chart showing a third embodiment of the sample hold circuit of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the sample hold circuit of the present invention.

FIG. 7 is a timing chart showing the circuit operation of the first conventional example.
It is a chart.

FIG. 8 shows a first example of a conventional sample hold circuit.
It is a circuit diagram.

FIG. 9 is a circuit diagram showing a second example of a conventional sample hold circuit.

FIG. 10 is a circuit diagram showing a third example of a conventional sample hold circuit.

Claims (4)

(57) [Claims] An electric charge is stored in a hold capacitor and a potential is stored in the hold capacitor.
In the sample-hold circuit that holds the
A first PNP-type bipolar transistor whose
The base and collector terminals of the
A first NPN bipolar transistor connected to a source terminal
Connected to the base terminal of the
The first PNP bipolar transistor as an input terminal;
The collector terminal is connected to the high power supply terminal.
The base of the second NPN bipolar transistor connected
To the first NPN bipolar transistor.
The emitter terminal of the transistor is used as the collector terminal for the lower power supply terminal.
Connected second PNP-type bipolar transistor base
Source terminal, and the second PNP-type bipolar
The emitter terminal of the transistor and the second NPN type
The power supply is connected to the emitter terminal of the polar transistor at one end.
The other end of the hold capacitor connected to the terminal and the voltage
Commonly connected to the input terminal of the
And the output terminal of the
In addition, a third terminal in which the collector terminal is connected to the lower power supply terminal
Base terminal and collector of PNP type bipolar transistor
A third NPN-type device whose data terminal is connected to the higher power supply terminal
Connected to the base terminal of the polar transistor,
Emitter terminal of third NPN bipolar transistor
The base of the second NPN-type bipolar transistor
1st constant current for pull down
A third NPN bipolar transistor connected to a source
Is always biased, and the third PNP bipolar transistor
The emitter terminal of the transistor to the second PNP-type bipolar
Connected to the base terminal of the transistor and pull
The third PNP connected to a second constant current source for
The bipolar transistor is always biased and the first
The emitter terminal of the NPN bipolar transistor is
Connects a third constant current source that pulls down only when sampling
Of the first PNP-type bipolar transistor.
4th pull-up to the mitter terminal only during sampling
And a constant current source . 2. The third constant current source has an emitter terminal.
Fourth and fifth NPN types commonly connected to the constant current source 5
Is composed of a bipolar transistor, said fourth NPN
Terminal of the first bipolar transistor is connected to the first terminal.
Connected to emitter terminal of NPN type bipolar transistor
And the base terminal goes high only during sampling
A first sampling clock signal is input, and a fifth
Higher collector terminal of NPN type bipolar transistor
Connect to the power supply terminal, and the base terminal
The intermediate level of the first sampling clock signal
And the fourth constant current source is
Fourth and fourth emitter terminals are commonly connected to a sixth constant current source.
And a fifth PNP bipolar transistor.
The collector end of the fourth PNP type bipolar transistor
Of the first PNP type bipolar transistor.
Connected to the monitor terminal and the base terminal only when sampling.
Input the second sampling clock signal which becomes low level
And the fifth PNP type bipolar transistor
Connector terminal to the lower power supply terminal and the base terminal to the
The second sampling clock signal as an alarm signal.
The sample-hold circuit according to claim 1, wherein a constant voltage of an intermediate level of the signal is input . 3. A sample and hold circuit comprising a seventh constant current source, an eighth constant current source, and a plurality of circuit blocks each having a sample and hold input terminal and a sample and hold output terminal. In each of the many circuit blocks, the collector terminal is the lower power supply terminal and the emitter is
Via the first switch to the first current supply terminal respectively
Connected first PNP bipolar transistor base
Source terminal and collector terminal
Respectively to the second current supply terminal via the second switch.
Of the connected and connected first NPN bipolar transistor
Connect to the base terminal and input the sample hold signal
Of the first PNP-type bipolar transistor
The emitter terminal and the collector terminal are connected to the high-level power supply terminal.
Base terminal of the second NPN-type bipolar transistor
And the first NPN-type bipolar transistor
Connect the emitter terminal of the
Base of a second PNP-type bipolar transistor
And the second PNP-type bipolar transistor.
An emitter terminal of a transistor and the second NPN bipolar transistor
One end of the emitter terminal of the transistor and the lower power supply terminal
The other end of the connected hold capacitor and the voltage
And the output of the voltage follower.
Force as the sample and hold signal output terminal,
A third PNP having a collector terminal connected to the lower power supply terminal
Type bipolar transistor base and collector terminals
NPN type bipolar connected to a high power supply terminal
Connected to the base terminal of the transistor,
The emitter terminal of the NPN bipolar transistor is
To the base terminal of the second NPN bipolar transistor
Connect and also a first constant current for pull-down
A third NPN bipolar transistor connected to a source
Always biases the third PNP-type bipolar tiger.
The emitter terminal of the transistor is connected to the second PNP-type bipolar transistor.
Connected to the base terminal of the
Connected to a second constant current source for pull-up
Always bias the PNP bipolar transistor,
A seventh constant current source is provided in each of the plurality of circuit blocks.
The eighth current, which is commonly connected to the first current supply terminal,
A source is the second current source of each of the plurality of circuit blocks.
Commonly connected to the supply terminal, each of the plurality of circuit blocks
Summing the first and second switches in each
The first PNP-type bipolar transistor is turned on during ringing.
Transistor and the first NPN bipolar transistor
A sample hold circuit for making an emitter terminal of a star conductive . 4. The second NPN bipolar transistor.
The emitter terminal and one end of the star are connected to the lower power supply terminal.
A first resistor is connected to the other end of the hold capacitor.
And further, the second PNP-type bipolar transistor
And the other terminal of the hold capacitor
Have a second resistor with the same value as the first resistor
4. The sample and hold circuit according to claim 1, wherein