JP2664721B2 - Video synthesizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a video capable of combining and displaying a plurality of types of image information having different video frequencies and refresh timings into one image. It relates to a synthesizer.

(Prior Art) In recent years, personal computers and workstations have been remarkably popularized, and the use of a plurality of types of computers and workstations at the same time has been increasing along with the cost reduction. In such a case, each computer is operated while displaying the processing data (image information or the like) by a display exclusively connected to each computer, but it is necessary to see many displays at once. There is a defect such as.

Therefore, it has been considered to combine and display image information from a plurality of computers on one display. However, the image information from each computer often has a video frequency and a refresh timing according to the system specifications. Due to the difference in the video frequency and the refresh timing between these pieces of image information, the image synthesis can be effectively performed. There are problems such as difficulty in performing. Also, due to the difference in the size and resolution of the display screen in each system and the difference in the size of the image information handled in each system, when combining multiple types of image information, the image information on the synthesized image Problems such as difficulty in viewing were also likely to occur.

(Problems to be Solved by the Invention) As described above, when combining image information handled by a plurality of types of computers into a single image and displaying the combined image, conventionally, when the video frequency of each image information differs, Due to the difference in the refresh timing, the difference in the size of the image, the difference in the resolution, and the like, there is a problem that it is difficult to effectively obtain an easy-to-view synthesized image from which the image information can be accurately grasped.

The present invention has been made in view of such circumstances,
Its purpose is to provide a simple configuration that enables a plurality of types of image information having different video frequencies and refresh timings to be combined into a single image and displayed in a state where the information contents can be easily understood. A video synthesizing device is provided.

[Structure of the Invention] (Means for Solving the Problems) A video synthesizing device according to the present invention stores first image information having a first video frequency and a first refresh timing. Receiving means for receiving second image information having a second video frequency and a second refresh timing different from the first video frequency and the first refresh timing of the first image information; Serial / parallel conversion means for converting the second image information received by the means from serial data to parallel data, and second storage means for storing the second image information of the parallel data converted by the serial / parallel conversion means Generating address data sequentially in synchronization with a first video frequency of the first image information and a first refresh timing; and Generating means for generating address data for each same address according to the size conversion rate in the direct direction, a blanking signal obtained by a first refresh timing of the first image information stored in the first storage means, or A first synthesized signal for specifying a vertical video synthesis area by counting the vertical synchronization signal and multiplying the counted value by a vertical size conversion ratio;
By counting a video clock based on a first video frequency of the first image information stored in the first storage means, a logic with a second synthesized signal for specifying a horizontal video synthesis area is calculated. Generating means for generating a read signal by a product operation, a read signal generated by the generating means and a video clock based on a first video frequency of first image information stored in the first storage means; Reading means for reading out the second image information from the second storage means based on the address data from the generating means at a timing based on the second image information, and converting the second image information read by the reading means into a horizontal size Parallel / serial conversion means for converting parallel data into serial data in accordance with a rate, and serial / serial data converted by the parallel / serial conversion means. Second image information data and the first
And output means for combining and outputting the first image information stored in the storage means.

(Operation) According to the present invention, the first image information having the first video frequency and the first refresh timing is stored in the first storage means, and the first video frequency of the first image information is stored. And second image information having a second video frequency different from the first refresh timing and a second refresh timing, and converting the received second image information from serial data to parallel data. The second image information of the converted parallel data is stored in the second storage means, and the address data is sequentially stored in synchronization with the first video frequency of the first image information and the first refresh timing. Generating means for sequentially generating the same address data for each address in accordance with the vertical size conversion rate, and storing the first image stored in the first storage means; A first synthesized signal for specifying a vertical video synthesis area by counting a blanking signal or a vertical synchronization signal obtained at a first refresh timing of information and multiplying the counted value by a vertical size conversion ratio. And a second synthesized signal that specifies a horizontal video synthesis area by counting a video clock based on the first video frequency of the first image information stored in the first storage unit. A read signal is generated by a logical AND operation of the above, and at a timing based on the generated read signal and a video clock based on the first video frequency of the first image information stored in the first storage means. Reading the second image information from the second storage means based on the address data from the generating means, and reading the read second image information in the horizontal direction. Is converted from parallel data to serial data in accordance with the size conversion ratio of the above, and the second image information of the converted serial data is combined with the first image information stored in the first storage means. This is a display output.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic configuration diagram of a video synthesizing apparatus according to an embodiment, and 1 is a storage device that stores first image information DPDT to be synthesized. The first data stored in the storage device 1
The second image information to be combined with the image information DPDT is input to the scan converter 2 via the interface unit 3. The scan converter 2 converts the video frequency and refresh timing of the second image information into the video frequency and refresh timing of the first image information DPDT, and synchronizes with the first image information DPDT. By this scan conversion, the video frequency and the refresh timing of the first image information DPDT and the second image information DPDT2 are matched, and the synchronization is achieved.

The enlargement device 4 as an image size conversion means enlarges the second image information DPDT2 scan-converted as described above, and enlarges the size of the second image information DPDT3.
Is generated. The second image information DPDT3 that has been subjected to such scan conversion and enlargement conversion in multiple stages is provided to the synthesizing device 5, and is synthesized with the first image information DPDT read from the storage device 1. Then, the synthesized image obtained by the synthesizing device 5 is displayed on the display device 6.

Here, although the image size conversion is described in terms of enlargement processing, it is of course possible to perform reduction processing, and to perform size conversion processing on the second image information before performing the above-described scan conversion processing. Of course, it is also possible to scan-convert the second image subjected to the size conversion processing.

Now, a storage device 1 for storing the first image information DPDT
Is configured, for example, as shown in FIG. The frame buffer 10 stores the first image information DPDT for one frame, and the writing and reading of the image data are performed according to the address data sequentially generated from the address generating unit 11, and are controlled by the memory selecting unit 14. Done. The display control unit 13 controls the first image information DP stored in the frame buffer 10.
Under the control of the display control 13, the address selection unit 12 selects the address data generated by the address generation unit 11 and controls the access to the frame buffer 10.

The first image information is written into the frame buffer 10 by the access control and the control by the memory selection unit 14, and the first image information is read from the frame buffer 10. Then, the first image information read from the frame buffer 10 is output as serial data via a parallel / serial (P / S) converter 15.

FIG. 3 shows an access operation of the frame buffer 10 in the storage device 2 configured as described above. Briefly describing this access operation, the reading and writing of the image information are controlled in response to the read request signal RDRQ and the write request signal WTRQ from the system, and the read cycle and the read cycle are controlled.
This is performed by setting a write cycle. Then, a control signal such as a RAS signal or a CAS signal is provided from the memory control unit 14 to the frame buffer 10, and address data from the address generation unit 11 is provided from the address selection unit 12 to the frame buffer 10. .

On the other hand, the display request signal DSPRQ1 output once during one horizontal period during image synthesis is given to the storage device 1 in preference to the read request signal RDRQ and the write request signal WTRQ, and the display read signal DSPRQ1 is displayed in accordance with the display request signal DSPRQ1. The cycle is set. As a result, the address selection signal MUXSC1 is supplied to the address selection unit 12, and the address from the display control unit 13 is selected. At this time, the row address is given to the frame buffer 10 in the address selection unit 12, and the address selection unit 12 receives the RAS signal and the CAS signal from the memory control unit 14 and switches to the column address. By this address switching, the first register for one line is stored in the shift register in the frame buffer 10.
Are read out according to the clock SC at the timing shown in FIG. 4, and are output via the P / S converter 15.

On the other hand, the first
For the image information DPDT, the second image information to be combined with the first image information is processed by the scan converter 2 and the enlargement device 4 as follows.

FIG. 5 shows an example of the configuration of the scan conversion unit 2 including a part of the functions of the enlargement device 4. Reference numeral 20 denotes an S / P conversion unit 21.
Is a frame memory for storing the second image information input via the CPU over one frame. The writing of the image data into the frame memory 20 is performed by accessing the frame memory 20 by selecting the address data generated by the write address generating unit 22 through the selector 24 under the writing control by the memory control unit 25. Done. Reading of the image data written in the frame memory 20 is performed as follows.
Under the read control of the memory controller 25, the address data generated by the read address generator 23 is selected via the selector 24 to access the frame memory 20.

Note that writing and reading of image data to and from the frame memory 20 are performed only for the designated image area under the control of the area designating unit 26. Then, the second image information read from the frame memory 20 is converted into serial data via the P / S converter 27 and output. In this case, the P / S converter 27 is constituted by a shift register as shown in FIG. 6, and outputs the image data read out in parallel from the frame memory 20 every four pixels, repeatedly by two times. Is stored twice as large.

FIG. 7 shows the signal timing of the second image information input to the scanning conversion unit 2 configured as described above. The vertical synchronization signal VSYNC20 and the horizontal synchronization signal HSYNC20 are added.
It is provided as video data VDT2 synchronized with the video clock VCLK2 during the section of the blanking signal BLANK. Here, a description will be given by taking a digitized video signal as an example,
The same applies to analog video signals.
In this case, an A / D converter may be incorporated in the interface unit 3.

By the way, the second image information provided in this manner generally has a video frequency and a refresh timing different from those of the first image information read from the storage device 1 in many cases. The scan converter 2 scan-converts the second image information in the following manner, adjusts its video frequency and refresh timing to the video frequency and refresh timing of the first image information, and establishes the synchronization thereof. doing. At this time, image enlargement processing is also performed at the same time.

That is, the frame memory 20 of the scan converter 2 has a dual-port memory configuration, and the write cycle and the read cycle are alternately set as shown in the operation timing of FIG. Perform reading.

The writing of the image data into the frame memory 20 is synchronized with the horizontal synchronization signal HSYNC20 in the above-described write cycle, and is supplied from the memory control unit 25 in accordance with the address signal output from the write address generation unit 22 as the video clock VCLK2. The frame memory 20 is accessed according to the control signals RASO, CASO, WEO, etc.
This is performed by writing T2 into the frame memory 20.

On the other hand, as described above, the reading of the second image information written in the frame memory 20 is performed by accessing the frame memory 20 at the address generated by the read generation unit 23 in the above read cycle, and setting the area designation unit 26 This is performed by controlling the timing of reading from the frame memory 20 by the memory control unit 25 that operates under the control of.

FIG. 9 (a) stored in the storage device 1
In the first image information shown in FIG. 9, an instruction is given to which image position the second image information as shown in FIG. 9B stored in the scan conversion unit 2 (frame memory 20) is to be combined. The combination position (DX1, DY1) is specified, for example, as shown in FIG. The position is specified by a CPU or the like. At this time, the size of the second image information to be combined with the first image information is instructed. As shown in the figure, the video synthesis area is obtained.

The control of the video composition area is performed by examining the timing at which the first image information is refreshed and examining whether the position is within the video composition area specified by the position information (DX1, DY1). Thus, reading of image information from the frame memory 20 by the memory control unit 25 is controlled.

Specifically, assuming that the second image information is doubled and combined with the first image information, the area setting unit 26 performs the blanking signal of the first image information as shown in FIG. BLANKO
Alternatively, a refresh position in the vertical (Y) direction is obtained from a counter that counts the vertical synchronization signal VSYNCO, and a combined signal YMIXEN for specifying a video combining area in the Y direction is generated. In the horizontal (X) direction, a video signal VCLK is counted, so that a synthesized signal for specifying a video synthesis area in the X direction is obtained.
XMIXEN is generated. Here, the second image information is 2
Since the image is magnified twice and synthesized with the first image information, the blanking signal BLANK is calculated as (Y2) for the synthesized signal YMIXEN.
X Set as the period counted twice.

The synthesized signals YMIXEN and XMIXEN generated in this way are logically processed as shown in FIG. 13, and a synthesized enable signal MIXEN described later is generated as shown in FIG.

When receiving the display request signal DSPRQ1 from the storage device 1, the memory control unit 25 switches its operation mode to the display read cycle. And a memory control unit according to the timing signal of the first image information provided from the storage device 1.
25 and the read address generating section 23, the image data is read out from the frame memory 20 in synchronization with the first image information and at the same video frequency and refresh timing as shown in FIG. .

In this case, as described above, in order to double the second image information and combine it with the first image information, the same address data is read from the read address generation unit 23 in the Y direction as shown in FIG. Is repeatedly applied to the frame memory 20 over the line. By reading the image data at a timing different from the time of writing the image data into the frame memory 20, that is, at the timing of the first image information, the video frequency and the refresh timing of the second image information are obtained. Is converted to be equal to the first image information. The image data scanned and converted and read out from the frame memory 20 is P /
X is repeatedly output twice by the S conversion unit 27,
In this case, the image is enlarged twice in the direction, and the image is subjected to a conversion process of the size of the image together with the above-described enlargement in the Y direction, and is output.

That is, basically, the second image information written in the frame memory 20 is read out at the signal timing of the first image information and over the period indicated by the composite enable signal MIXEN. The scan conversion is performed,
The video frequency and the refresh timing are matched. Here, at the same time as this scan conversion, an enlargement process is performed on the image.

The second, which has been subjected to scan conversion and enlargement processing as described above,
Is given to a synthesizing device configured as shown in FIG. 16, and the image is synthesized. Then, a composite image as shown in FIG. 11 is obtained.

In the embodiment, when the display read cycle is executed by the display request signal DSPRQ1, the next write cycle is stopped, and the display read cycle is executed with priority. Such control is performed in consideration of the fact that the display image is disturbed when the display read cycle is executed during the display period, and that normal image information cannot be obtained if the display read cycle is delayed.
At this time, the image information in the write cycle is not written in the frame memory 20, and the image information written in the previous write cycle is read and displayed. However, the video signal subjected to scan conversion is normally refreshed at least 60 times per second in the case of non-interlace and 30 times in the case of interlace, so that 1/30, 1/60
After a few seconds, the image information is rewritten. Therefore, it is possible to obtain a composite image which has no problem for human eyes and has no display disorder.

Thus, according to the present apparatus, even when a plurality of types of image information having different video frequencies and refresh timings are provided, the video signals and refresh timings are matched by the above-described scan conversion processing, and Change the size of the image information
It is possible to generate a composite image and display the image. In particular, in the case of a plurality of types of image information having different video frequencies and the like, the size of the image itself often differs due to the resolution and the like. For this reason, when a plurality of types of images are synthesized only by scan conversion, the second image information is reluctantly reduced as shown in FIG. 10 by the scan conversion as compared with the first image information, It may be difficult to grasp (understand) the content of the image information. In this regard, according to the present apparatus, the size of the image of the second image information to be synthesized is variably controlled before being provided to the synthesis processing.
It is possible to combine images with an appropriate size. Therefore, it is possible to obtain an effect that a problem such as difficulty in understanding the image content is not caused.

Note that the present invention is not limited to the above-described embodiment. Here, an example in which the second image information is enlarged to double the size and combined with the first image information has been described, but it is of course possible to enlarge the image at another magnification. Of course, this enlargement process can be performed before the scan conversion. In this case, the image is stored in the frame memory 20 after the enlargement process is performed.

In addition to enlarging the second image information, the image can be appropriately reduced and combined with the first image information. In this case, it is possible to prevent such a problem that the second image is undesirably greatly enlarged by the scan conversion, and only a part of the second image cannot be synthesized with the first image information. In addition, it is of course possible to combine not only two types of images but also three or more types of images. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[Effects of the Invention] As described above, according to the present invention, image information to be combined is scan-converted and its video frequency and refresh timing are made to match the video frequency and refresh timing of the image information to be combined. And the image information is variably controlled so as to be synthesized with the image information to be synthesized, so that the image information in the synthesized image is undesirably reduced, or undesirably enlarged and partially expanded. In this way, it is possible to effectively combine and display a plurality of types of image information with a size (resolution) that makes it easy to understand the information content. As a result, even when various computers are gathered in one place and predetermined processing is performed, those images can be effectively combined and displayed using one image display device, and the processing load is increased. This has a great effect in practical use, for example, in that it is possible to significantly reduce the amount of light. Further, according to the video synthesizing apparatus according to the present invention, images can be synthesized with a simple hardware circuit configuration and with relatively simple control.

[Brief description of the drawings]

FIG. 1 shows a video synthesizing apparatus according to an embodiment of the present invention. FIG. 1 is an overall configuration diagram of the apparatus, FIG. 2 is a diagram showing an example of the configuration of a storage device, and FIGS. FIG. 5 is a diagram illustrating an operation timing of the apparatus, FIG. 5 is a diagram illustrating a configuration example of a scan conversion unit including a function of an enlargement device, FIG. 6 is a diagram illustrating a configuration example of a P / S converter in the scan conversion unit, FIG. FIG. 8 and FIG. 8 are diagrams showing the operation timing of the scan conversion unit, and FIG.
FIG. 11 is a diagram showing an example of processed image information, FIG. 12 is a diagram showing signal timings of the image information in FIG. 2, FIG. 13 is a diagram showing a configuration example of a circuit for generating a composite enable signal,
FIG. 14 is a diagram showing a synthesis enable signal, FIG. 15 is a timing diagram showing an example of an image enlargement process, and FIG. 16 is a diagram showing a configuration example of a synthesis device. DESCRIPTION OF SYMBOLS 1 ... Storage device (1st image information), 2 ... Scan conversion part (2nd image information), 4 ... Enlargement device, 5 ... Synthesizing device, 6 ... Display device, 10 ... Frame buffer (First image information), 20 ... frame memory (second image information), 22 ... write address generator, 23 ... read address generator, 25 ... memory controller, 26 ... area designation unit ,
27 …… P / S converter.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location G09G 5/18 G09G 5/18 H04N 5/265 H04N 5/265 5/45 5/45

Claims (1)

(57) [Claims] A first storage unit for storing first image information having a first video frequency and a first refresh timing; and a first video frequency and a first video frequency of the first image information. Receiving means for receiving second image information having a second video frequency different from the refresh timing and a second refresh timing; and converting the second image information received by the receiving means from serial data to parallel data Serial / parallel conversion means, second storage means for storing second image information of parallel data converted by the serial / parallel conversion means, first video frequency of the first image information, Address data is sequentially generated in synchronization with the refresh timing of No. 1 and the same address for each address according to the vertical size conversion rate. A blanking signal or a vertical synchronizing signal obtained by a first refresh timing of the first image information stored in the first storage means. Multiplying the size conversion rate to obtain a first synthesized signal that specifies a video synthesis area in the vertical direction;
Counting the video clock based on the first video frequency of the first image information stored in the storage means, and performing a logical product operation with the second composite signal specifying the horizontal video composite area Generating means for generating a read signal; timing based on the read signal generated by the generating means and a video clock based on a first video frequency of first image information stored in the first storage means Reading means for reading the second image information from the second storage means based on the address data from the generating means; and a horizontal size conversion ratio for the second image information read by the reading means. Parallel / serial conversion means for converting parallel data into serial data in accordance with the serial data, and serial data converted by the parallel / serial conversion means. Video synthesizing apparatus characterized and output means for displaying and outputting the first image information stored synthesized and in the second image information and the first storage means, by comprising a.