JP2661327B2 - Channel route search method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel route search method, and more particularly, to a channel route search method in a time division multiplexing device that performs automatic detour of a channel path when a failure occurs in a multiplex line or the like. .

[Conventional technology]

Conventionally, in this type of channel route search method, a search is performed by sequentially accessing nodes serving as routes from a control terminal that manages a time division multiplexing device that forms a network.

[Problems to be solved by the invention]

This conventional channel route search method has a problem that when a channel route is relayed by several nodes, all the relayed nodes must be accessed sequentially, which takes a long search time. there were.

[Means for solving the problem]

According to the present invention, a plurality of channel interface units for transmitting and receiving channel data of a data communication channel, a plurality of line interface units for transmitting and receiving data multiplexed with a plurality of channel data to and from a line, respectively, And a switch circuit unit connected to the line interface unit, receiving data from both interface units, performing switching for exchanging time slots, and transmitting data to both interface units. The channel interface unit for transmitting and receiving the channel data by allocating a channel data time slot and a channel path information time slot for each channel as a generalized time slot receives the channel data. A channel data receiving circuit, a flag transmitting circuit for transmitting a flag to the channel path information time slot, and the switch circuit for multiplexing the channel data from the channel data receiving circuit and the flag from the flag transmitting circuit. A first multiplexing circuit for transmitting the data from the switch circuit unit to channel data and channel path information; and receiving and transmitting the channel data separated by the separation circuit. A data transmission circuit, a first flag detection circuit for detecting the flag from the channel path information separated by the separation circuit, and a first flag storage for storing the channel path information based on a signal from the flag detection circuit.
A switch circuit unit, wherein the switch circuit unit detects a flag from the channel path information time slot of data from the channel interface unit and the line interface unit, and a second flag detection circuit; A second buffer circuit for storing the node number of the own device, a node number transmitting circuit for transmitting the node number of the own device, and the self-address transmitted from the node number transmitting circuit to the channel path information stored in the second buffer circuit. A second multiplexing circuit for adding a device node number and multiplexing the time slot for the channel path information, and a switch for exchanging the time slot and transmitting data to the channel interface unit and the line interface unit Channel search method characterized by comprising a circuit Obtained.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a channel route search system according to the present invention, and FIGS. 2 and 3 are circuit block diagrams showing examples of a channel interface unit and a switch circuit unit in FIG. 1, respectively.

In FIG. 1, time division multiplexing devices (hereinafter, TDM) 1a, 1b and 1c are installed in nodes A, B and C, respectively.
TDMs 1a and 1c, which are terminal nodes, have channel interface units (hereinafter CIF) 2a and 2c, switch circuit units (hereinafter SWE) 3a and 3c, and line interface units (hereinafter LIF) 4a and 4c, respectively. The TDM 1b of a certain Node B includes LIFs 4ab and 4bc that interface with the TDMs 1a and 1c through lines, respectively, and the SWE 3b.

Each CIF2a, 2b and 2c, as shown in CIF2 in FIG.
A data receiving circuit (hereinafter, DTR) 5, a flag sending circuit (hereinafter, FLG) 6, a multiplexing circuit (hereinafter, MUX) 7, a data transmitting circuit (hereinafter, DTS) 8, and a separating circuit (hereinafter, DMX) 9 respectively.
And a flag detection circuit (hereinafter DET) 10 and a buffer circuit (hereinafter BUF) 11.

In addition, SWE3a, 3c and 2 installed between CIF and LIF
The SWE3b installed between the two LIFs includes a DET 12, a BUF 13, a node number transmission circuit (hereinafter, NOS) 14, a MUX 15, and a switch circuit (hereinafter, SW) as shown in SWE3 of FIG.
It consists of 16 and.

Next, the operation of this embodiment will be described with reference to FIGS.

In the CIF 2a in the TDM 1a of the node A, the MUX 7 multiplexes the data received by the DTR 5 and the two flags sent from the FLG 6 into a data time slot and a channel path information time slot, respectively, and sends them to the SWE3. DET12 in SWE3a
After detecting the flag on the channel path information time slot, taking this flag into BUF13, and multiplexing the node number "A" of its own device sent from NOS14 by MUX15 so that it becomes the node number after the first flag Then, the time slots are exchanged by SW16 and output from LIF4a to the line. In the node B, the data received by the LIF 4ab of the TDM 1b is sent to the SWE 3b, and the DET 12 detects the flag of the channel path information time slot similarly to the node A, and the flag from the node A, the node number “A”, the flag BUF13
The MUX 15 adds the node number “B” from the NOS 14 between the flag and the node number “A” and sends it out.
Output to the line via LIF4bc. Node C of terminal node
Similarly, SWE3c adds its own node number “C” next to the first flag of the channel route information time slot, and
c, the CIF2c separates the data time slot and the channel route information time slot by DMX9,
Transmitted from DTS8, the channel path information detects a flag at DET10, and stores the node number following the flag in BUF11. In this way, the channel paths A, B, and C are stored in the BUF11. Channel routes C, B, and A are similarly transferred from the node C to the node B. Therefore, the channel path can be searched only by accessing either the node A or the BUF11 of the node C at both ends.

〔The invention's effect〕

As described above, the present invention has a plurality of channel interface units for transmitting and receiving channel data of a data communication channel, and a plurality of line interface units for transmitting and receiving data multiplexed with a plurality of channel data, respectively, to a line. In a multiplexing apparatus, the multiplexing apparatus is connected to a channel interface unit and a line interface unit, and receives data from both interface units, performs switching for exchanging time slots, and transmits data to both interface units. The channel interface section that transmits and receives channel data by allocating a channel data time slot and a channel path information time slot to each channel as a generalized time slot is a channel data receiving channel data. A receiving circuit, a flag transmission circuit for sending a flag to the channel path information for time slot,
A first multiplexing circuit for multiplexing the channel data from the channel data receiving circuit and the flag from the flag transmitting circuit and transmitting the multiplexed data to the switch circuit unit; and separating the data from the switch circuit unit into channel data and channel path information. Separating circuit, a data transmitting circuit for receiving and transmitting the channel data separated by the separating circuit, a first flag detecting circuit for detecting a flag from the channel path information separated by the separating circuit, and a flag detecting circuit A first buffer circuit for storing channel path information based on a signal from the circuit, wherein the switch circuit section detects a flag from a channel path information time slot of data from the channel interface section and the line interface section. A detection circuit, a second buffer circuit for storing channel path information, A node number transmitting circuit for transmitting the node number of the device, and a node number of the own device transmitted from the node number transmitting circuit added to the channel route information stored in the second buffer circuit to a channel route information time slot. By providing a second multiplexing circuit for multiplexing and a switch circuit for exchanging time slots and sending data to the channel interface unit and the line interface unit, one of both ends can be accessed without accessing the relay node. Since the channel path can be searched only by accessing the channel section of the node, the search can be performed in a short time. Further, when a flake cannot be received by the channel interface unit, it indicates that a failure has occurred in the channel path, so that it is also possible to use it for path failure detection.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a channel route search system according to the present invention, and FIGS. 2 and 3 are circuit block diagrams showing examples of a channel interface unit and a switch circuit unit in FIG. 1, respectively. 1a, 1b, 1c: time division multiplexer (TDM), 2, 2a, 2c: channel interface unit (CIF), 3, 3a, 3b, 3c ... switch circuit unit (SWE), 4a, 4ab, 4bc, 4c: Line interface (LIF), 5: Data receiving circuit (DTR), 6:
... Flag sending circuit (FLG), 7,15 ... Multiplexing circuit (MU
X), 8 ... Data transmission circuit (DTS), 9 ... Separation circuit (DMX), 10, 12 ... Flag detection circuit (DET), 11, 13 ...
Buffer circuit (BUF), 14 ... Node number sending circuit (NO
S), 16 ... Switch circuit (SW).

Claims (1)

(57) [Claims] 1. A plurality of channel interface units for transmitting and receiving channel data of a data communication channel, a plurality of line interface units for transmitting and receiving data multiplexed with a plurality of channel data to and from a line, respectively, and the channel interface unit And a switch circuit unit connected to the line interface unit, receiving data from both interface units, performing switching for exchanging time slots, and transmitting data to both interface units. The channel interface unit that transmits and receives the channel data by allocating a channel data time slot and a channel path information time slot to each channel as a time slot is a channel that receives the channel data. A channel data receiving circuit, a flag transmitting circuit for transmitting a flag to the channel path information time slot, and the switch circuit by multiplexing the channel data from the channel data receiving circuit and the flag from the flag transmitting circuit. A first multiplexing circuit for transmitting the data from the switch circuit unit to channel data and channel path information; and receiving and transmitting the channel data separated by the separation circuit. A data transmission circuit, a first flag detection circuit for detecting the flag from the channel path information separated by the separation circuit, and a first buffer circuit for storing the channel path information based on a signal from the flag detection circuit Wherein the switch circuit section includes the channel interface section and the line interface. A second flag detection circuit for detecting the flag from the channel path information time slot of the data from the interface unit, a second buffer circuit for storing the channel path information, and a node for transmitting the node number of the own device. A number transmitting circuit, and adding the node number of the own device transmitted from the node number transmitting circuit to the channel path information stored in the second buffer circuit, and multiplexing the channel path information into the channel path information time slot. A channel route search method comprising: a second multiplexing circuit; and a switch circuit that exchanges the time slots and sends data to the channel interface unit and the line interface unit.