JP2655076B2 - Driving method of plasma display panel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called dot matrix type memory type AC plasma display panel for use in personal computers and office workstations, which are making remarkable progress in recent years, and wall-mounted televisions, which are expected to develop in the future. It relates to a driving method.

[0002]

2. Description of the Related Art The general operation principle of a conventional AC plasma display panel is described in Kyoritsu Shuppan Publishing Co., Ltd., "Plasma Display" published on 1983.11, pp. 20-39. Referring to FIG. 8 showing the structure of the plasma display, FIG. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along line xx ′ of FIG. This plasma display panel has a first insulating substrate 1 made of glass.
1. A second insulating substrate 12, also made of glass, a transparent sustain electrode 13a, a transparent scan electrode 13b, a metal electrode 13c for supplying a sufficient current to the transparent sustain electrode 13a and the transparent scan electrode 13b, and a column electrode. 14, a discharge gas space 15 filled with a discharge gas such as He or Xe, a partition wall 16 for securing a discharge gas space and separating pixels, a phosphor 17 for converting ultraviolet light generated by discharge of the discharge gas into visible light, An insulating layer 18a covering the electrodes 13a and the scanning electrodes 13b, an insulating layer 18b covering the column electrodes 14, and a protective layer 1 made of MgO or the like for protecting the insulating layer 18a from electric discharge.
9.

In FIG. 8A, a section surrounded by vertical and horizontal partitions is a pixel 20, and a scanning electrode S _i (i =
, M) and the column electrode D _j (j = 1, 2,..., N)
The pixel at the intersection of is denoted by a _ij . If the phosphor 17 shown in FIG. 8B is painted in three colors for each pixel, a color display plasma display can be obtained. The display direction of the display can be either the upper surface or the lower surface of FIG. 8B, but in this case, the lower surface is more preferable.

An example of such a driving method of the plasma display panel is described in Japanese Patent Application Laid-Open No. Hei 4-195188. The configuration diagram described in the publication is shown corresponding to the configuration of the present invention, and referring to FIG. 9, which focuses only on the electrode arrangement of the plasma display panel, a plasma display panel 10, a first insulating substrate 11, and a second insulating substrate A sealing portion 21 for sealing a gas tightly by sealing a discharge gas inside the portion where the electrodes 12 are bonded, and a sustain electrode 13a (C ₁ ,
C ₂ ,..., C _m ), scanning electrodes 13 b (S ₁ , S ₂ ,.
S _m ), column electrode 14 (D ₁ , D ₂ ,..., D _n−1 , D _n )
Having.

Next, consider a case where gradation display is performed using such a plasma display panel. Referring to FIG. 10 which shows an explanatory diagram of the subfield method in which scanning and sustaining are separated, the horizontal axis represents time, the vertical axis represents scanning electrodes, and one field is divided into k subfields (see FIG. 10). In the case of 10, the pixel is divided into eight subfields (SF1 to SF8), and the number of times of light emission of each pixel in each subfield is weighted by 2 ⁿ to express the luminance gradation as follows.

[0006]

A _n is a variable having a value of 1 or 0.
FIG. 10 shows the case where k = 8, and 2 ⁸ = 256 gradations can be expressed. If k = 1, one field = 1 subfield, and two gradations (on or off) can be displayed.

FIG. 11 is a diagram showing an example of a driving voltage waveform and an emission waveform in one subfield of the plasma display panel shown in FIGS.

The waveform (A) shows C _{1 of the} sustain electrode 13a,
C _2, ..., the voltage waveform applied to C _m, waveform (B) is the voltage waveform applied to the S ₁ scan electrode 13b, the waveform (C) is the voltage waveform applied to the S ₂ scan electrodes 13b, waveform (D ) is the voltage waveform applied to S _m of the scanning electrodes 13b, the waveform (E)
Shows the voltage waveform applied to D ₁ of the column electrodes 14, waveform (F) is the voltage waveform applied to the D ₂ of column electrode 14, the waveform (G) is the light emission waveform of a ₁₁ pixel 20, respectively.

The hatched pulses in waveforms (E) and (F) indicate that the presence or absence of the pulse is determined according to the presence or absence of data to be written. FIG. 11 shows a case where data is written to the pixels a ₁₁ and a ₂₂ as a data voltage waveform. For the pixels in the third and subsequent rows, display is performed depending on the presence or absence of data. That is, the data pulses to be written in response to the scanning pulse 33 for scanning electrodes S ₁ of a waveform (E) shows a first pulse a ₁₁ waveform (E), the scan pulse of the scan electrode S ₂ of the waveform (C) data pulses to be written in response to 33 (the first space) second waveform (F) shows a pulse a ₂₂ in. C ₁ , C ₂ ,... Of the sustain electrode 13a of the waveform (A)
The C _m, and applies the sustain pulse 31 and the preliminary discharge pulse 36. In addition, S of the scanning electrode 13b of the waveforms (B) to (D)
₁ , S ₂ ,..., S _m include, in addition to the sustain pulse 32, the erase pulse 35, and the preliminary discharge erase pulse 37 common to these electrodes, a scan pulse 33 at a timing independent of each scan electrode. To supply. Each column electrode D _j (j =
If light emission data exists in (1, 2,..., N), the data pulse 34 is supplied in synchronization with the scanning pulse 33.

Referring again to the plasma display panel having the configuration shown in FIGS. 8 and 9, first, the pixel 20 that has emitted light in the immediately preceding subfield is erased by the erase pulse 35. Next, all the pixels 20 are forcibly discharged once by the preliminary discharge pulse 36, and the preliminary discharge is erased by the preliminary discharge erasing pulse 37. This allows
The writing discharge by the next supplied scanning pulse is easily caused.

After erasing the preliminary discharge 36, the scan electrodes S _{1 to} S
_{When the} scan pulse 33 and the data pulse 34 are supplied at the same timing between _m and the column electrodes D ₁ and D ₂ to cause a write discharge, then the sustain pulse is applied between the adjacent sustain electrode 13 a and scan electrode 13 b. The sustain discharge is sustained by the sustain pulse 31 and the sustain pulse 32. Such a function is called a memory function. The light emission luminance of each subfield is controlled by the number of sustain discharges.

Next, another example of a different driving method of the plasma display panel is described in JP-A-4-42289. Referring to FIG. 12 showing the configuration of the subfield based on the driving method described in the publication, the erase timing of the sustain discharge (narrow hatch line) is also scanned together with the write discharge timing (thick oblique line). The preliminary discharge is performed once in one field. Scan electrodes S _{1 to} S
One field period is divided into sections T _{1 to} T ₆ and a preliminary discharge section corresponding to _m , and 32L, 16
L, 8L, 4L, 2L and L indicate the light emission time, and other blank sections indicate the non-light emission time.

FIG. 13 shows a driving waveform of one subfield corresponding to FIG. Unlike the driving waveform shown in FIG. 11, the sustain pulse is continuously applied. Further, three scan pulses are applied in one sustain pulse period, and a data pulse is applied in synchronization with the three scan pulses. The data pulse does not overlap with the sustain pulse or the erase pulse. The erasing pulse is simultaneously applied to three scanning electrodes corresponding to the three scanning pulses, and scanning is performed as a set.

[0015]

However, in the conventional driving method, unless the data pulse voltage is sufficiently high,
In some cases, writing discharge did not occur reliably. However, when the data voltage is increased, there is a problem that power consumption required for writing data increases. That is, there are capacitances between the column electrodes to which the data pulse is supplied, between the column electrodes, between the column electrodes and the scanning electrodes, and between the column electrodes and the sustaining electrodes. When a data pulse having a voltage of V is supplied to the column electrode, charging and discharging of these capacitances C occur. As a result of this charge / discharge, a current flows through the column electrodes and power is consumed. This power is a magnitude of the CV ^2, the data pulse voltage is the power consumption increases rapidly increased.

In order to surely cause a write discharge,
It is also conceivable to increase the scanning pulse voltage. However, if the scan pulse voltage is increased unnecessarily with respect to the sustain pulse voltage, erroneous discharge may occur. Further, there is an upper limit at which the scan pulse voltage can be increased due to the restriction of the operation voltage of the drive circuit that generates the scan pulse voltage.

An object of the present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a method of driving a plasma display panel capable of reducing power consumption even when a data pulse voltage is set to a high value at which writing discharge is reliably caused. Is to make it happen.

[0018]

The driving method of the plasma display panel according to the present invention comprises at least a plurality of parallel column electrodes, a plurality of scanning electrodes orthogonal to and parallel to the column electrodes, and a matrix of these electrodes. When driving an AC memory type plasma display panel having cells disposed at each point, the cells are discharged by a write pulse at the time of address, the discharge of each cell is maintained by a sustain pulse, and the discharge is erased. In the method for driving a plasma display panel to be extinguished by a pulse, at least two or more consecutive data pulses are commonly superimposed on database pulses of the same polarity as these data pulses, respectively, and the column electrode and the scan electrode are Between the column electrode and the scan electrode in the write discharge. Discharge start voltage to be equal to or less than,
The voltage of the database pulse is set.

When one field is divided into n (n is an integer of 1 or more) subfields, and when information of one surface is written and displayed in each of these subfields, the database pulse is at most 1 in length. The period is set in a subfield period, and has a period in which the data berth pulse stops during the one subfield period and the column electrode returns to a potential of a predetermined reference voltage. A pulse, at least one of the preliminary discharge pulse and the preliminary discharge erase pulse may be included.

Furthermore, the database pulse may be supplied at a timing other than the supply timing of the erase pulse and the sustain pulse.

Still further, the longest period of the database pulse includes a period within the one subfield and a period during which the sustain pulse is continuously supplied to the sustain electrode and the scan electrode. it can.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS. 2 (a) and 2 (b) showing the principle of the method of driving a plasma display panel according to the present invention, a plurality of data pulses 4 are supplied with a database pulse 8 in common. I made it. In this case, the voltage of the data pulse can be lower than in the conventional case, so that the charge / discharge power for writing data can be reduced.

At this time, when the database pulse rises from low level to high level and falls from high level to low level, the pulse also has charging / discharging power. However, as can be seen from FIGS. Since the pulse 8 is common to the plurality of data pulses 4, the number of rising and falling of the database pulse is far less than the number of rising and falling of the data pulse. Therefore, the power required for charging and discharging the capacitance C can be reduced.

Referring to FIG. 3 showing the setting of the voltage of the database pulse, the database pulse 8 may be set lower than the voltage V _D1 . At this time, it can be seen that the voltage of the data pulse 4 can be set lower than the data pulse voltage in the conventional example by an amount corresponding to the database pulse voltage.

As can be seen from FIG. 8B of the prior art, the column electrode 14 is covered with the phosphor 17 and the insulating layer 18b and operates with an alternating current. A period for returning to the reference voltage (often the ground level) is required. During this period, it is necessary that ions and electrons generated by the discharge adhere to the surface of the phosphor 17 to be ready for scanning. For this reason, it is necessary that this period include at least one of an erasing pulse, a pre-discharge pulse, and a pre-discharge erasing pulse that generate a discharge on the surface discharge side.

Another effect obtained when the database pulse is used is an effect of suppressing secondary discharge. The secondary discharge is a discharge that occurs when the application of the pulse is removed. The data pulse alone causes this secondary discharge when the data pulse voltage increases. As a result, the surface charge accumulated on the surface discharge side by the write discharge disappears,
The discharge at the time of writing may not be continued to the sustain discharge. When the database pulse of the present invention is provided, the voltage of the data pulse can be made lower than in the conventional case, so that this secondary discharge can be effectively suppressed. As a result, the transition from the write discharge to the sustain discharge can be ensured.

As the plasma display panel for carrying out the present invention, the one shown in FIGS. 8 and 9 described above was used. Therefore, description will be made with reference to FIGS. 8A, 8B and 9 again.

[0028] S ₁ scan electrodes _{13b, S 2, ..., S} m is 480, the sustain electrodes _{13a C 1, C 2, ...} , C m is 4
The number of D ₁ , D ₂ ,..., D _n−1 , D _n of the column electrodes 14 is 1920. The pitch of each pixel is 0.
35 mm, and the distance between the scanning electrodes is 1.05 mm. The distance between the scanning electrode and the column electrode is 0.2 mm. FIG.
3B, the first insulating substrate 11 is soda glass having a thickness of 3 mm, the second insulating substrate 12 is soda glass having a thickness of 3 mm, the sustaining electrode 13a is a transparent Nesa film, and the scanning electrode 13b.
Is also a transparent Nesa film, the metal electrode 13c is a silver thick film, the column electrode 14 is a silver thick film electrode, and the discharge gas space 15 is 4
7 to 3 He and N mixed with 3% Xe at 00 Torr
e, and the partition 16 is sandwiched between the first insulating substrate 11 and the second insulating substrate 12 so that each pixel 2
The film was formed by a thick film process dividing the interval between 0. The phosphor 17 is made of Zn ₂ SiO ₄ : Mn for converting ultraviolet light generated by the discharge of the discharge gas into visible light, and the insulating layer 18 a is made of the row electrode 1.
3, the insulating layer 18b is also made of a thick white glaze that also covers the column electrode 14, and the protective layer 19 is 2 μm thick MgO that protects the insulating layer 18a from gas discharge. .

The subfields constituting one field are the same as in the prior art shown in FIG.
8, the sustain pulse in the subfield SF1 having the lowest luminance is four times including one scan pulse, and the sustain pulses in the upper subfields SF2 to SF8 thereafter are each one scan pulse. 2 out of 4 times, including
^{The number} was multiplied by ⁿ . Therefore, SF2 is eight times, SF3
Are 16 times,..., And the number of sustain pulses in the subfield SF8 giving the highest luminance is 5 including one scan pulse.
12 times.

FIG. 1 shows a driving waveform according to the first embodiment of the present invention. Referring to FIG. 1, waveform (A) shows sustain electrode 13a.
C _1, C ₂ of, ..., the voltage waveform applied to C _m, waveform (B) is the voltage waveform applied to the S ₁ of the first scanning electrode 13b, the waveform (C) in the S ₂ of the next scan electrodes 13b the applied voltage waveform, waveform (D) is the voltage waveform applied to S _m of the last scan electrodes 13b, waveform (E) is a voltage waveform supplied to the D ₁ of the column electrodes 14, waveform (F) is the column electrodes 14 shows the voltage waveform supplied to the D ₂ respectively.

The shaded pulse of the waveform (E) or the waveform (F) indicates that the presence or absence of the pulse is determined according to the presence or absence of data to be written. For example, FIG. 1 shows a case where data is written to pixels a ₁₁ and a ₂₂ as a data voltage waveform. For the pixels after the third row,
This indicates that display is performed depending on the presence or absence of data.
That is, the data pulses to be written in response to the scan pulse of the waveform (B) shows a first pulse a ₁₁ waveform (E), the data pulses to be written in response to the scan pulse of the waveform (C) is a waveform ( the second F) (1 th indicates a pulse of a ₂₂ for blank) without data.

C ₁ of the sustain electrode 13 a of the waveform (A),
C ₂ ,..., C _m have sustain pulse 1 (pulse width 2 μm).
Second, the cycle is 6 μs, and the voltage is -150 V).
Further, S ₁ , S ₂ ,..., S _m of the scanning electrode 13b have sustain pulses 2 (pulse width, period,
In addition to the voltage of the sustain pulse 1, the scan pulse 3 (with a pulse width of 3 μs,
(-150 V) are supplied line-sequentially. The data pulse 4 has the same pulse width as the scan pulse 3 and a voltage of 60 V,
The erase pulse 5 has a pulse width of 5 μs and a voltage of sustain pulse 1
The same as above, the preliminary discharge pulse 6 has a pulse width of 10 μsec and a voltage of −300 V, and the preliminary discharge erase pulse has a pulse width of 10 μs.
The voltage was set to -30 V in seconds.

The database pulse 8 of the present invention has a pulse width of 1.5 milliseconds and a voltage of 60V. This voltage value was set so that the voltage difference between the column electrode and the scan electrode was equal to or lower than the discharge starting voltage between the column electrode and the scan electrode in the write discharge.

Conventionally, 80 V was used as the data pulse voltage due to the limitation of the driving IC. Thus the scanning electrode for the power P1 column electrodes and between the column electrodes at this time, the capacitance between sustain electrode is C, the ^{P1 = CV 2 = C × 80} × 80 = 6400C. On the other hand, the power consumption P2 when the database pulse 8 is used is P2 = C × 60 × 60 = 3600C because the data voltage is 60V. Therefore, the power required to write the data 4 was greatly reduced to 56% of the conventional power. At this time, the power consumption by the database pulse 8 is about 1/100 or less of the data pulse in the case of normal television image display and can be ignored.

It should be noted that the database pulse 8 is not a pulse, but a direct current as the bias voltage.
Does not have the above effect, and a value of 120 V is required as the data pulse. Further, as can be seen from the result, the reference voltage in FIG. 3 is normally a ground potential of 0 V, but a DC voltage may be supplied without being necessarily limited to this.

Although the database pulse 8 is different from that shown in FIG. 1, the same effect as that shown in FIG. 1 can be obtained even if the database pulse 8 is extended to a period in which the sustain pulse 1 and the sustain pulse 2 are continuously applied.

Next, referring to FIG. 4, which shows the data voltage waveform of the second embodiment of the present invention in comparison with the conventional data voltage waveform, FIG.
Is the same as In addition, since the voltage waveforms of the sustain electrodes and the scan electrodes are the same as in FIG. 13, the description is omitted here. In this example, while the first embodiment continuously writes and discharges data to all the scan electrodes, the scan electrodes S _{1 to} S ₃ and S ₄
An example for intermittently write discharge data every three scanning electrodes like a to S _6. After the sustain pulse is supplied four times, the erase pulse is supplied and rewritten with the next data. The database pulse 8 is not supplied at the timing when the sustain pulse or the erase pulse is applied. When the circuit is configured such that the database pulse 8 can be controlled for each scan electrode, the database pulse 8 is stopped only during the period during which the erase pulse is supplied and during the preliminary discharge period, and during other periods, the database pulse 8 is stopped.
May be continuously supplied.

The waveforms shown in FIGS. 1 and 4 can be produced by using a commercially available IC or individual transistors. The example is shown in FIGS.

Referring to FIG. 5A showing an example of a drive circuit used in the drive method of the present invention, FETs Q1 and Q2 are connected in series between terminals TM1 and TM2, and the connection point between the series connection point and terminal TM3. FET Q3 in between
And the FET Q4 are connected in series, and the series connection point is connected to the terminal TM4. One set of this circuit is connected to one scanning electrode 13b. The terminal TM1 is at the level of the reference voltage, and the terminal TM2 is at the database pulse 8
The terminal TM3 is connected to a DC power supply for providing the sum of the voltage values of the database pulse 8 and the data pulse 4, and the terminal TM4 is connected to each scanning electrode 13a.

FIG. 5B shows ON and OFF states of each FET.
The relationship between the OFF timing and the output voltage appearing at the terminal TM4 is shown. Hereinafter, it is assumed that FETs other than those not specified are turned off.

In the period T1, the FET Q2 and the FET Q
4 is turned on, and the voltage of the terminal TM4 is
Equal to the reference voltage supplied to

In the period T2, the FETs Q1 and Q4 are turned on, and the voltage at the terminal TM4 becomes equal to the DC voltage value V2 of the database pulse 8 supplied to the terminal TM2. At this time, since the current flows through the parasitic diode of the FET Q4, the FET Q4 may be turned off. This is shown in FIG.
This is indicated by a broken line A in (b).

In the period T3, the FET Q1 and the FET Q3 are on, and the voltage at the terminal TM4 becomes equal to the DC voltage value V3 of the sum of the database pulse voltage and the data pulse voltage supplied to the terminal TM3. At this time, the FET Q1 may be off. This state is shown by a broken line B.

In the period T4, the FETs Q1 and Q4 are turned on, and the voltage at the terminal TM4 becomes equal to the database voltage value V2 supplied to the terminal TM2. At this time, the current flows through the parasitic diode of the FET Q1.
ETQ1 may be off. This is indicated by the broken line C in FIG. Thus, the drive waveforms shown in FIGS. 1 and 4 can be produced.

It should be noted that the P-channel FET Q1 and the N-channel FET Q3 may be common to a circuit for driving a plurality of scan electrodes. This case is shown in FIG. Referring to FIG. 6 showing another example of the driving circuit used in the driving method of the present invention, the FET Q is connected between the terminal TM12 and the terminal TM11.
11 and FET Q12 are connected in series, and FET Q13 and FET Q12 are connected between the series connection point and terminal TM13.
14 series connected circuits and FET Q15 and FET Q16
Is connected in parallel with the series direct connection circuit of
The drain of the FET 14 is connected to the terminal TM14, and the drain of the FET Q15 is connected to the terminal TM15. The terminals in FIG. 5 are TM1, TM11, T
M2 and TM12, TM3 and TM13, TM4 and TM14
Or TM15 respectively.

The terminal TM11 is at the level of the reference voltage, the terminal TM12 is a DC power supply for supplying the voltage of the database pulse, the terminal TM13 is a DC power supply for supplying the sum of the voltage values of the database pulse and the data pulse, and the terminals TM14 and TM15 are It is connected to each scanning electrode. The operation is the same as that of the circuit of FIG.

In order to generate the waveforms shown in FIGS. 1 and 4, the circuit shown in FIG. 7 can be used. FIG. 7 shows still another example of the drive circuit in the drive method of the present invention.
Referring to (a), the FET Q21 and the diode D21
And D22 and FET Q24 are connected in series and FET Q
The other ends of 21 and Q24 are commonly connected to terminal TM22. The series connection point of the diodes D21 and D22 is connected to the FE connected in series between the terminal TM23 and the terminal TM21.
Terminal T together with the drains of TQ23 and FET Q22
It is configured to be commonly connected to M24. The terminals in FIG. 5 are TM1 and TM21, TM2 and TM22,
TM3 and TM23 correspond to TM4 and TM24, respectively. One set of this circuit is connected to one scanning electrode. The terminal TM21 is connected to a reference voltage level, the terminal TM22 is connected to a DC power supply for supplying a voltage of a database pulse, and the terminal TM2 is connected to a terminal TM2.
Reference numeral 3 denotes a DC power supply for providing a sum of voltage values of the database pulse and the data pulse, and a terminal TM24 is connected to each scan electrode.

FIG. 7B shows that each FET is turned on,
The relationship between the OFF timing and the output voltage appearing at the terminal TM24 is shown. Hereinafter, it is assumed that FETs other than those not specified are turned off.

In the period T21, the FET Q22 is on, and the voltage at the terminal TM24 is equal to the reference voltage supplied to the terminal TM21. At this time, the FET Q24 may be on. This is indicated by a broken line A in FIG.

In the period T22, the FET Q21 is turned on, and the voltage of the terminal TM24 becomes equal to the value V2 of the DC database pulse voltage supplied to the terminal TM22.
At this time, the FET Q24 may be turned on. This is indicated by a broken line B in FIG.

In the period T23, while the FET Q23 is in the ON state, the voltage of the terminal TM24 becomes equal to the DC voltage value V3 of the sum of the database pulse voltage and the data pulse voltage supplied to the terminal TM23. At this time, the FET Q21 may be turned on. This state is shown by a broken line C.

In the period T24, the FET Q24 is turned on, and the voltage of the terminal TM24 becomes equal to the database voltage value V2 supplied to the terminal TM22. At this time, FET
Q21 may be on. This is indicated by the dashed line D. Thus, the drive waveforms shown in FIGS. 1 and 4 can be produced.

The circuit elements described above include:
Any element that has a switch function, such as a bipolar transistor, may be used instead of the FET.

The numerical values given in the above embodiments are given to explain the effects of the present invention in accordance with actual examples. Therefore, these numerical values do not limit the applicable range of the present invention. Needless to say, there is nothing. Particularly, the value of the database pulse 8 naturally changes depending on the structural dimensions of the panel, the discharge gas and the protective layer. In addition, even though these conditions are the same, there are variations depending on individual panels, so that they are set in accordance with them.

The case where the driving method of the present invention is applied to a so-called three-electrode type AC memory surface discharge type plasma display panel as shown in FIGS. 8 and 9 has been described. However, the present invention is not limited to this, and it is needless to say that the present invention can be applied to driving of an AC memory type plasma display panel having another panel structure, such as an opposed two-electrode type AC memory type plasma display panel.

[0056]

As described above, according to the driving method of the plasma display panel of the present invention, by superimposing a database pulse on a plurality of data pulses in common, a pulse for writing data to be supplied to the data electrode is provided. The voltage can be set to a high value at which the write discharge reliably occurs. Thereby, while causing a reliable write discharge,
Power consumption for data pulses can be greatly reduced. In addition, the number of database pulse charging / discharging can be much smaller than the number of data pulses.
In addition, the power consumption required for writing data, including the database pulse, can be greatly reduced as compared with the related art. As a result, a method for driving a plasma display panel that can reduce the overall power consumption can be obtained, energy resources can be saved, and this is industrially very useful.

Further, by using the database pulse, the voltage of the data pulse can be set lower than before, and the secondary discharge during data writing can be suppressed. As a result, the transition from the write discharge to the sustain discharge can be assured, and image display with high display quality can be performed, and the driving characteristics of the plasma display panel can be greatly improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing voltage waveforms in a first embodiment of the driving method of the present invention.

FIG. 2A is a principle diagram of a driving method according to the present invention.
(B) Another principle diagram of the driving method of the present invention.

FIG. 3 is a diagram showing a voltage setting of a database pulse in the driving method of the present invention.

FIG. 4 is a diagram showing a second embodiment of the driving method of the present invention.

FIG. 5 is a diagram showing an example of a driving circuit used in the driving method of the present invention.

FIG. 6 is a circuit diagram showing another example of the driving circuit used in the driving method of the present invention.

FIG. 7 is a circuit diagram showing still another example of the drive circuit used in the drive method of the present invention.

FIG. 8A is a plan view of a plasma display panel. FIG. 9B is a cross-sectional view of the plasma display panel shown in FIG.

FIG. 9 is a configuration diagram of a plasma display panel focusing on electrode arrangement.

FIG. 10 is a diagram for explaining a subfield method in which scanning and sustaining are separated.

11 is a diagram showing the detailed drive voltage waveform and light emission waveform of FIG.

FIG. 12 is an explanatory diagram of a subfield in which scanning and sustain are mixed.

FIG. 13 is a detailed drive voltage waveform diagram of FIG.

[Explanation of symbols]

1,2,31,32 Sustain pulse 3,33 Scan pulse 4,34 Data pulse 5,35 Erase pulse 6,36 Predischarge pulse 7,37 Predischarge erase pulse 8 Database pulse 10 Plasma display panel 11 First insulating substrate 12 the second insulating substrate _{13a, C 1, C 2,} ..., C m sustain electrodes _{13b, S 1, S 2,} ..., S m scanning electrodes 13c metal electrodes _{14, D 1, D 2,} ..., D n-1, D _n column electrode 15 Discharge gas space 16 Partition wall 17 Phosphor 18a, 18b Insulating layer 19 Protective layer 20 Pixel 21 Seal part

Claims (4)

(57) [Claims] 1. At least a plurality of parallel column electrodes,
When driving an AC memory type plasma display panel having a plurality of scanning electrodes orthogonal to and parallel to the column electrodes and cells arranged at each point of a matrix of these electrodes, a write pulse is applied to the cells at an address. , A discharge of each cell is maintained by a sustain pulse, and the discharge is extinguished by an erase pulse. At least two or more consecutive data pulses have the same polarity as these data pulses. While being superimposed on each of the database pulses in common, the voltage difference between the column electrode and the scan electrode is less than or equal to the discharge start voltage between the column electrode and the scan electrode in the write discharge. A plasma display panel, wherein a voltage of the database pulse is set. Method of driving a. 2. One field is defined as n (n is an integer of 1 or more).
When dividing into the above-described subfields and writing and displaying information on one surface in each of these subfields, the database pulse is set within a period of at most one subfield, and is set within a period of at most one subfield. A period in which the data berth pulse stops and the column electrode returns to a potential of a predetermined reference voltage, and at least one of the erase pulse, the preliminary discharge pulse, and the preliminary discharge erase pulse is included in the period; The method of driving a plasma display panel according to claim 1, wherein: 3. The method according to claim 1, wherein the database pulse is supplied at a timing other than the supply timing of the erase pulse and the sustain pulse. 4. The longest period of the database pulse,
2. The method of driving a plasma display panel according to claim 1, further comprising a period in which the sustain pulse is continuously supplied to the sustain electrode and the scan electrode within a period of the one subfield.