JP2644201B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a transistor having a polycrystalline silicon emitter electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device of this type and a method of manufacturing the same will be described with reference to FIGS.

For example, in the case of an NPN transistor, FIG.
As shown in (a), a silicon oxide film 3 having a thickness of 60 to 70 nm is formed on the surface of an N-type silicon substrate 1, and the P-type base regions 2-1, P-2 and P-3 are selectively formed by selectively implanting boron ions.
A P ⁺ -type graft base region 2-2 is formed in a part of the mold base region 2-1. Next, a silicon nitride film 4 having a thickness of 150 nm is deposited, a desired opening 5 is selectively formed in the photoresist film 16 for forming a contact region, and a first opening is formed in the silicon nitride film 4 by isotropic etching. Is formed.

Next, as shown in FIG. 3B, a photoresist film 12 is used to form an emitter region so as to avoid the occurrence of defects on the surface of the P-type base region 2-1 on the underlying substrate. The second opening 13 is formed by etching the silicon oxide film 3 by wet etching with hydrofluoric acid or the like without using dry etching.

Here, in order to form the second opening 13 reliably, it is necessary to perform overetching, so that an overhang structure in which a silicon nitride film protrudes in an eaves shape around the second opening is obtained.

[0006] In order to remove the photoresist film 12 and form an emitter region, a polycrystalline silicon film is grown on the entire surface, and then ion implantation of phosphorus or phosphorus is performed, and then heat treatment is performed. As shown in FIG. 5, an N ⁺ -type emitter region 15 is formed on the surface of the P-type base region 2-1. Next, the polycrystalline silicon film is patterned to form an N ⁺ type polycrystalline silicon emitter electrode 14. Next, as shown in FIG. 3D, the P ⁺ type graft base region 2-
After the opening 16 is provided in the silicon oxide film 3 on the substrate 2, an aluminum film or the like is deposited and patterned,
A base electrode 17B and a metal emitter electrode 17E are formed.

The silicon nitride film 4 is formed of a silicon nitride film 4 to improve reliability such as moisture resistance.
It is used to relieve stress between the silicon substrate.

[0008]

In the above-described conventional semiconductor device and the method of manufacturing the same, when the second opening is formed in the silicon oxide film by wet etching, over-etching is performed.
Since the etching is performed, an overhang structure in which the silicon nitride film protrudes is obtained.

Therefore, in the subsequent growth of the polycrystalline silicon film, the polycrystalline silicon wraps between the silicon nitride film having the overhang structure and the silicon substrate.
By the subsequent heat treatment, stress of the silicon nitride film is applied to the surface of the base region via the polycrystalline silicon. As a result, dislocations occur in the base region. Accordingly, the electrical characteristics of the transistor are adversely affected, and in particular, impurities for forming the emitter region diffuse along the dislocation. The derived diffusion region based on the dislocation not only lowers the withstand voltage between the emitter and the base, but also seriously causes a short circuit between the collector and the emitter.

It is an object of the present invention to provide a semiconductor device having a transistor capable of avoiding such deterioration of electrical characteristics due to dislocation, in particular, reduction in withstand voltage and short-circuit, and a method for manufacturing the same.

[0011]

[0012]

According to a method of manufacturing a semiconductor device of the present invention, a second conductivity type base region and a surface provided in a first conductivity type region of a surface portion are sequentially formed of a silicon oxide film and a silicon nitride film. Preparing a semiconductor substrate covered with, a resist film having an opening on the second conductivity type base region, performing isotropic etching using the resist film as a mask, and forming the resist film on the silicon nitride film. Forming a first opening larger than the opening of FIG. 1, phosphorus ions are implanted into the silicon oxide film in a direction perpendicular to the surface of the semiconductor substrate using the resist film as a mask, and wet etching is performed using the silicon nitride film having the first opening as a mask. A contour penetrating the silicon nitride film and the silicon oxide film by performing etching to form a second opening in the silicon oxide film Forming a first conductive type emitter region on the surface of the second conductive type base region by joining the emitter electrode made of the first conductive type polycrystalline silicon film and the second conductive type base region. It is doing.

Instead of implanting phosphorus ions after forming the first opening, the first opening can be formed in the silicon nitride film after phosphorus ions are implanted into the silicon oxide film.

The semiconductor substrate is a silicon substrate, and wet etching can be performed with buffered hydrofluoric acid.

[0015]

By implanting phosphorus ions into a silicon oxide film using a resist film for forming a first opening in a silicon nitride film as a mask, a region having a higher etching rate than a portion where phosphorus ions are not implanted is formed in the first opening. Can be formed within. Therefore, the bottom of the second opening can be made smaller than the bottom of the second opening, so that the silicon oxide film exists between the silicon nitride film and the semiconductor substrate immediately below the contact hole around the contact hole. it can. Since the silicon oxide film can be interposed between the polycrystalline silicon that has entered the lower portion of the silicon nitride film and the semiconductor substrate, the silicon oxide film acts as a stress relaxation layer,
Dislocation is prevented from being generated in the semiconductor substrate.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIGS. 1 (a), (b), (c) and (d)
FIG. 6 is a process order sectional view for explaining the example of the present invention.

First, as shown in FIG. 1A, a thin silicon oxide film 3 having a thickness of 60 to 70 nm is formed on the surface of an N-type silicon substrate 1 and N-type silicon lithography is performed using a known photolithography technique.
A photoresist film having a predetermined shape for forming a base region of the PN transistor is formed, and a P-type base region 2-1 occupying a rectangular plane is formed by using boron ion implantation. Similarly, a P ⁺ type graft base region 2-2 is formed in the P type base region 2-1. Thereafter, a silicon nitride film 4 having a thickness of 150 nm is
It is formed by the VD method. Next, an opening 6 for forming a base contact hole is formed in the silicon nitride film 4 using the photoresist film 7 having the opening 5 on the graft base region 2-2 as a mask. After the photoresist film 7 is peeled off, FIG.
As shown in (b), an opening 9- is formed on the P-type base region 2-1.
The first opening 9-2, which is larger than the opening 9-1, is formed by forming a photoresist film 8 having a 1 and using the mask as a mask to remove the silicon nitride film 4 by isotropic etching using H ₃ PO ₄ or the like. To form Next, using the photoresist film 8 as a mask, phosphorus ions are implanted at an acceleration voltage of 40 to 60 keV, at a dose of 1 × 10 ¹⁴ / cm ² , and at an implantation angle of 0 °. An implantation region 10 is formed. At this time, phosphorus may be slightly implanted into the silicon substrate.
Next, the photoresist film 8 is peeled off, and as shown in FIG. 1C, a photoresist film 12 having a larger opening 11 is formed on the first opening 9-2, and buffered hydrofluoric acid is used. The silicon oxide film 3 is etched. Since the ion-implanted region 10 is etched about three times faster than the surrounding silicon oxide film, when the ion-implanted region 10 is completely removed, the silicon oxide film remains around it. The second opening 13A having a bottom surface narrower than the bottom surface of the opening 9-2 can be formed.

Next, after growing a polycrystalline silicon film having a thickness of 150 nm over the entire surface, arsenic is implanted at an acceleration voltage of 70 keV and a dose of 1 × 10 ¹⁶ / cm ² , and a heat treatment is performed at 750 ° C. for 50 minutes to form a P-type film. An N ⁺ -type emitter region 15 is formed on the surface of the base region 2-1. Next, the polysilicon film is patterned to form an N ⁺ -type polysilicon emitter electrode 14.
And After that, it is the same as the conventional one.

The bottom of the second opening 13A is connected to the first opening 9-
Therefore, even if a polycrystalline silicon film enters between the silicon nitride film 4 and the silicon oxide film 3, the thickness of the polycrystalline silicon film is smaller than that of the conventional example, and the silicon oxide film is located under the penetrated portion. Is present, which acts as a stress relieving layer and prevents dislocations from occurring in the silicon substrate. Accordingly, arsenic does not diffuse along the dislocations, thereby avoiding the problems of the prior art such as a decrease in breakdown voltage and the occurrence of short-circuit failure. It goes without saying that an N-type impurity such as phosphorus may be implanted in addition to arsenic.

FIGS. 2A to 2D are sectional views in the order of steps for explaining a modification of the present embodiment.

As shown in FIG. 2A, a P-type base region 2-1, a P ⁺ -type graft base region 2-1, a silicon oxide film 3, a silicon nitride film 4, The steps up to the point where the openings 6 and the photoresist film 8 are formed are exactly the same as those of the embodiment. Next, phosphorus ions are accelerated at an accelerating voltage of 140 to 170 keV and a dose of 1 × 10 ¹⁴ / cm.
^2. Inject at an injection angle of 0 °. Phosphorus ions penetrate the silicon nitride film 4 and are implanted into the silicon oxide film 3 to form an ion implanted region 10A. Next, as shown in FIG. 2B, an opening 9-2 larger than the opening 9-1 of the photoresist film 8 by isotropic etching using H ₃ PO ₄ or the like.
To form Hereinafter, in the same manner as in the embodiment, FIG.
As shown in FIG. 2, a second opening 13B is formed, and as shown in FIG. 4D, an N ⁺ type emitter region 15 and an N ⁺ type polycrystalline silicon emitter electrode 14 are formed. In this way,
The same effects as in the embodiment can be obtained. Phosphorus ions may be implanted into the silicon oxide film 3 either before or after forming the first opening in the silicon nitride film 4.

While the above description has been made with reference to an NPN transistor as an example, the present invention is also applicable to a PNP transistor. When phosphorus ions are implanted into the silicon oxide film, no problem occurs even if phosphorus is implanted to some extent into the N-type base region, as long as the concentration can be canceled by the concentration at which the B ⁺ -type emitter region is formed.

[0024]

As described above, the present invention has a laminated film of a silicon oxide film and a silicon nitride film on the surface of a semiconductor substrate, and a polycrystalline silicon emitter electrode in a contact hole formed in the laminated film. In order to form a transistor having a polycrystalline silicon film, a first opening is formed in the silicon nitride film and a second opening narrower than the first opening is formed in the silicon oxide film. The presence of the silicon oxide film between the polycrystalline silicon film and the semiconductor substrate that enters immediately below the silicon nitride film alleviates the stress caused by the silicon nitride film, thereby avoiding the generation of dislocations in the base region.

Therefore, the electrical characteristics deteriorate due to the dislocation,
In particular, there is an effect that a semiconductor device having a transistor with almost no breakdown voltage failure or short-circuit failure can be realized.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views in the order of steps for explaining one embodiment of the present invention.

FIG. 2A is a diagram illustrating a modification of the embodiment;
FIGS. 4A to 4D are cross-sectional views in the order of steps, which are separately illustrated.

FIG. 3A to FIG. 3D for explaining a conventional technique.
It is a process order sectional view divided and shown to (d).

[Explanation of symbols]

Reference Signs List 1 N-type silicon substrate 2-1 P-type base region 2-2 P ⁺ -type base region 3 silicon oxide film 4 silicon nitride film 5 opening 6 opening 7 photoresist film 8 photoresist film 9-1 opening 9, 9-2 1 opening 10, 10A ion implantation region 11 opening 12 photoresist film 13, 13A, 13B second opening 14 N ⁺ type polysilicon emitter electrode 15 N ⁺ type emitter region 16 opening 17B base electrode 17E metal emitter electrode

Claims (3)

(57) [Claims] A step of preparing a semiconductor substrate in which a second conductivity type base region provided in a first conductivity type region of a surface portion and a surface are sequentially coated with a silicon oxide film and a silicon nitride film; Forming a resist film having an opening on the two-conductivity type base region, performing isotropic etching using the resist film as a mask to form a first opening larger than the opening of the resist film in the silicon nitride film; Using the film as a mask, phosphorus ions are implanted into the silicon oxide film in a direction perpendicular to the surface of the semiconductor substrate, and wet etching is performed using the silicon nitride film having the first opening as a mask to form a second opening in the silicon oxide film. Forming a contact hole that penetrates the silicon nitride film and the silicon oxide film, and a first conductivity type polycrystalline silicon. Forming a first-conductivity-type emitter region on the surface of the second-conductivity-type base region by joining the emitter electrode with a film. 2. The method according to claim 1 , wherein the first opening is formed in the silicon nitride film after phosphorus ions are implanted into the silicon oxide film. Wherein the semiconductor substrate is a silicon substrate, a method of manufacturing a semiconductor device according to claim 1 or 2 wherein the buffered hydrofluoric acid performing wet etching.