JP2643908B2 - Ferroelectric memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory using a ferroelectric material.

[0002]

2. Description of the Related Art A metal-ferroelectric (Ferroelectric) using a gate insulating film as a ferroelectric material.
c) —Semiconductor A field effect transistor (MFSFET) has a structure similar to a MOSFET as shown in FIG. That is, it is composed of two diffusion layers 71 formed separately on a semiconductor substrate (usually a silicon substrate) 95, a gate insulating film 61 provided on the substrate surface between the two diffusion layers, and a gate electrode 35 thereon. . The gate insulating film 61 is a silicon oxide film in a normal MOSFET, and a ferroelectric thin film is used in an MFSFET.

In the MFSFET, changes in the threshold values Vt1 and Vt2 of the transistor due to the polarization inversion of the ferroelectric which is the gate insulating film 61 are used as binary information. That is, as shown in FIG. 4, when a certain gate voltage Vg1 is applied, binary information is determined based on the difference in the magnitude of the drain current 85 flowing through the transistor. The polarization inversion of the gate insulating film is realized by applying a positive or negative voltage between the gate electrode 35 and the semiconductor substrate 95.

When this MFSFET is applied to a memory device, it is necessary to arrange a large number of MFSFETs in a matrix. FIG. 5 is a circuit diagram showing this arrangement.

A large number of MFSFETs are arranged in one well region 2, and the gate electrodes of the FETs are connected to word lines 31, 32,
33, one of the source and the drain is connected to the bit lines 41, 42, 43,..., And the other is grounded (5).
I do. The substrate area is connected to a constant potential.

FIG. 6 shows a layout pattern of the memory cell. The element regions 10 are regularly arranged in the well region 2, and word lines 31, 32, 33,.
・ Form FIG. 7 shows the cross-sectional structure of FIG. FIG.
6A is a cross section taken along line A1-A2 in FIG. 6, and FIG. 7B is a cross section taken along line B1-B2 in FIG. Elements are separated from each other by forming element isolation regions in the same manner as in a normal LSI.

[0007]

However, the MFSFETs arranged in a matrix are arranged in the same well region 2 and the same word line, for example, the word line 31 and the well are connected to apply a voltage between the gate electrode and the substrate. When a voltage is applied to the region 2, there is a problem that data is simultaneously written to a plurality of memory cells connected on the word line 31.

In order to prevent this, a conventional element isolation structure, that is, a LOCOS element isolation structure is used to separate wells on the same word line, so that the PN isolation width becomes large and the chip size becomes large. There was a problem.

In the arrangement in which the memory cell arrays are arranged in the same well as described above, it is impossible to write / erase one information in one memory cell. It is an object of the present invention to solve such a problem and enable data to be independently written and erased in each memory cell.

[0010]

According to the present invention, there is provided a metal-ferroelectric-semiconductor field-effect transistor in which a plurality of word lines and bit lines intersect and at which intersections a gate insulating film is a ferroelectric material. In a memory cell array in which configured memory cells are arranged, a plurality of memory cells connected to one bit line are separated by one well.

The first element isolation method is used for element isolation in the bit line direction, and the second element isolation thinner than the element isolation thickness obtained by the first element isolation method is used for element isolation in the word line direction. And a well shallower than the first element isolation depth and deeper than the second element isolation depth.

Further, when a voltage is applied to the well and the word line to perform writing / erasing, the bit line potential is set to be the same as the well potential.

[0013]

When the MFSFET structure is used as a memory cell, by applying a voltage between the gate electrode and the substrate region, the polarization inversion of the ferroelectric material as the gate insulating film occurs, and the MF
The threshold voltage of the SFET changes. This is stored as information.

At this time, in order to store one piece of information in each of the memory cells constituting the memory cell array, the gate electrodes of a plurality of MFSFETs connected to a word line and a plurality of MFSFETs separated by wells are used. The substrate areas need to intersect at only one point. This is realized by limiting the well area.

Each memory cell included in the memory cell array performs electrical isolation by element isolation shallower than the well depth. On the other hand, by using element isolation deeper than the well depth for element isolation in the bit line direction, the wells of the memory cell group connected to each bit line can be electrically isolated from each other.

Further, at the time of writing, the depletion layer capacitance can be prevented from being generated on the surface of the substrate region below the gate insulating film by making the potential of the bit line connected to the memory cell to be written equal to the well potential. An electric field can be effectively applied between the gate electrode and the well.

[0017]

FIG. 1 is a circuit diagram of a memory cell array showing the structure of the present invention. FIG. 2A is a layout diagram of a cell array realizing the circuit of FIG. Further, FIG.
(C) shows two positions C1-C2 and D1- shown in FIG.
The device cross section at D2 is schematically shown.

As shown in FIG. 1, the bit lines 41, 4
The MFSFETs connected to 2 and 43, respectively, are located in 21, 22, and 23 in each well region. That is, MFSFETs connected to different bit lines do not exist in the same well. Further, the MFSFETs connected to the same word line do not exist in the same well. At this time, the MFSFE connected to the same bit line
Since T is located in the same well, the substrate potential can be determined by applying a voltage to the same well terminal, for example, 221, 222, 223.

The diffusion layer of the MFSFET that is not connected to the bit line is connected to the common ground terminal 5 including all the MFSFETs located in different well regions. When writing data to a desired cell, between the word line and the well that define the position of the desired cell,
A voltage higher than the coercive electric field of the ferroelectric material serving as the gate insulating film is applied to cause polarization inversion.

Hereinafter, a method of manufacturing the ferroelectric memory will be described with reference to FIG.

A p-well is formed on an n-type Si substrate, element isolation regions having two different depths are formed, and then an MFSFET is manufactured.

The element isolation method will be described in detail. Before forming the element isolation, p is added to the region where the memory cell array is formed.
Form a type conduction region, ie, a p-well. At this time,
The depth of the well is, for example, about 300 nm.

Thereafter, the MF connected to the same bit line
In order to electrically isolate the SFETs, an element isolation region 8 having an element isolation depth smaller than the well depth is formed in parallel with the word line. Specifically, LOCOS (Local
Oxidation of Si) The isolation depth is set to about 200 nm by using an element isolation method or a trench isolation method.

Next, the MFS connected to the same word line
An element isolation 9 for isolating between FETs is formed. It is important that the element isolation depth is formed to be deeper than the well depth of 300 nm. In this embodiment, a trench isolation method is used.

First, a photoresist pattern having an opening in a portion to be the deep element isolation region 9 is formed. Then, by dry etching, the Si substrate is etched,
A groove having a depth of about 400 nm corresponding to the deep element isolation 9 is formed. This groove needs to be deeper than the well depth of 300 nm.

Next, the photoresist is removed, a Si oxide film is deposited on the front surface of the well, and a trench for deep isolation 9 is buried. Then, only the Si oxide film in the groove is left by using an etch-back method or a chemical mechanical polishing method so that the Si oxide film does not remain in the element region 10 where the element is manufactured. Thereafter, an MFSFET is manufactured by the above-described method.

After the completion of element isolation, a ferroelectric material Pb (Zr, Ti) O ₃ (hereinafter abbreviated as PZT) is used as the gate insulating film 6.
Is formed by a sol-gel method or a sputtering method. Thereafter, after forming a polysilicon film, an exposure step and an etching step are performed to form a gate electrode of the MFSFET, that is, a word line 3. In addition, As ion implantation is used.
Elements are implanted into a silicon substrate to form diffusion layers 7 serving as source / drain regions. Thereafter, an aluminum alloy-based wiring is formed, and the fabrication of the memory element is completed.

In this embodiment, PZT is used as the ferroelectric material. However, other materials such as MgBaF ₄ and SrBiT are used.
a ₂ O ₉ or the like may be used.

Although the LOCOS method and the trench method are used as the element isolation method, other methods such as a shield plate method may be used as long as the element isolation methods have different isolation depths.

Next, an embodiment of the operation method according to the third aspect will be described.

At the time of writing data to the MFSFET memory cell 11, the ferroelectric material is applied between the word line 31 and the well 221 by applying a coercive electric field of approximately twice the coercive electric field of the ferroelectric material forming the gate insulating film. The polarization direction can be changed.

At this time, the bit line potential is changed to the well potential 22.
Same as 1. As a result, a depletion layer generated in the channel portion of the MFSFET can be controlled, and the word line-
Almost the voltage applied between the wells can be applied to the ferroelectric gate insulating film.

[0033]

The present invention configured as described above has the following effects.

MFSFETs connected to the same bit line are located in the same well, and MFSFETs connected to the same word line are connected.
Since all FSFETs are located in different wells, one memory cell to be written can be selected only by selecting a word line and a well.

Further, by using two element isolation regions having different element isolation depths and adjusting the well depth to a depth between these isolation depths, MFSFETs connected to different bit lines can be formed. Can be set to the minimum separation width.

Furthermore, by making the potentials of the bit line and the well the same, it is possible to prevent the generation of a depletion layer in the channel region of the MFSFET.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a layout diagram and a schematic cross-sectional view showing an embodiment of the present invention.

FIG. 3 is a configuration diagram of a general MFSFET.

FIG. 4 is a hysteresis characteristic diagram of a general MFSFET.

FIG. 5 is a circuit diagram showing a conventional example.

FIG. 6 is a layout diagram showing a conventional example.

FIG. 7 is a schematic sectional view showing a conventional example.

[Explanation of symbols]

 21, 22, 23 well regions 221, 222, 223 wells 3, 31, 32, 33 word lines 41, 42, 43 bit lines 5 ground 6, 61 gate insulating film 7 diffusion layer 8 shallow device isolation 9 deep device isolation 10 device Region 85 drain current 35 gate electrode 95 semiconductor substrate

Claims (3)

(57) [Claims] 1. A metal having a gate insulating film as a ferroelectric material.
In a ferroelectric memory in which a ferroelectric-semiconductor field-effect transistor is formed in a well at the intersection of a word line and a bit line, one well is connected to one bit line. A ferroelectric memory, wherein a plurality of memory cells are provided. 2. The element isolation depth in the bit line direction is deeper than the element isolation in the word line direction, and the depth of the well is smaller than the element isolation in the bit line direction, and is smaller than the element isolation depth in the word line direction. 2. The ferroelectric memory according to claim 1, wherein said ferroelectric memory is deeper. 3. The ferroelectric memory according to claim 1, wherein, when a voltage is applied to the well and the word line to perform writing / erasing, the bit line potential is made equal to the well potential.