JP2643210B2 - Title image generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A. Industrial application fields B. Summary of the invention C. Conventional technology D. Problems to be solved by the invention E. Means to solve the problems F. Function G. Examples (G1-1) The present invention Configuration of 8mm VTR with integrated camera (Figs. 2 and 3) (G1-2) Configuration of Titler circuit (Fig. 1) (G1-3) Operation of Titler circuit (G1-3-1) Registration operation ( (Fig. 1, Fig. 4) (G1-3-2) Insertion operation (Fig. 1, Fig. 5, Fig. 6) (G2) Application H. Effect of the invention A. Industrial application field More particularly, the present invention relates to a title image generating apparatus for forming a title image signal to be inserted into a video signal, and to a title image generating apparatus used for a so-called titler, telop, or the like.

B. Summary of the Invention The present invention stores a plurality of image data formed by digitizing an input video signal in a memory means, and forms a title image signal to be inserted into a video signal from the image data read from the memory means. In the title image generating device, a selection process of superimposition on a plurality of image data read from the memory means and a color designation process for each image are performed, and each image data is subjected to the color designation process. By forming an image signal of a title image obtained by superimposing images from the image data, it is possible to form image signals of various title images.

C. Conventional Art Conventionally, a so-called titler or telopper, which forms an image signal of a title image such as title information and telop information according to the content of an image to be reproduced from a video signal and inserts the video signal into the video signal, has been used in a video tape recorder. (VTR)
Known as peripheral devices.

These titlers, telops, and the like include a character generator or the like that stores various character patterns as a title image generator that forms a title image signal,
The title image signal formed by the character generator is inserted (so-called superimposed) into an input video signal supplied from a reproduction side VTR, an imaging device, or the like.

In addition, in a camera-integrated VTR including an imaging unit that captures a subject image and a recording unit that records a video signal formed from an imaging output obtained by the imaging unit, a video of the image captured by the imaging unit is provided. A device incorporating a title image generation device for writing image data obtained by digitizing a signal into a memory and forming a title image signal from the image data read from the memory,
It is proposed and used in the specification and drawings of Japanese Patent Application No. 62-094682.

The camera-integrated VTR is capable of inserting a title image signal formed by the title image generation device into a video signal of a subject image obtained by the imaging unit, thereby enabling an image captured by the imaging unit to be inserted into a title. The information and the telop information are stored in a memory so that the title information and the telop information can be read out from the memory as needed and easily recorded during video shooting.

D. Problems to be Solved by the Invention By the way, in the title image generating device built in the above-mentioned camera-integrated VTR, image data of a plurality of title images is stored in a memory, and selectively stored as necessary. A method of reading out each image data from the memory and forming a title image signal to be inserted into a video signal has been considered.

In such a title image generating device, image data of a plurality of title images stored in the memory is read out, and a color designation process is performed for each image. If the image signal of the title image in which is superimposed can be formed, image signals of various title images can be formed, and a more practical title image generating device can be realized.

In view of the above-described problems, an object of the present invention is to provide a title image generating apparatus having a novel configuration capable of forming image signals of various title images.

E. Means for Solving the Problems The present invention provides a means for digitizing an input video signal to form image data, and a memory means for storing a plurality of types of the image data in order to solve the problems as described above. A plurality of types of image data read out from the memory means, a combination priority is determined, and then combined, and a color of each of the overlapped image data is designated; and an image output from the processing means is provided. Means for forming an image signal of a title image from the data from the data.

F. Function In the title image generating apparatus according to the present invention, a process of combining a plurality of types of image data read from the memory means in accordance with the priority of superposition and designating a combination of three primary color signals of each superimposed image data is performed. Then, an image signal of a title image is formed based on the image data on which the processing has been performed.

G. Examples Hereinafter, examples of the present invention will be described in detail with reference to the drawings.

(G1-1) Configuration of Camera-Integrated 8 mm VTR to which the Present Invention is Applied (FIGS. 2 and 3) FIGS. 2 and 3 show an imaging unit 10 for photographing a subject image.
And a recording unit 20 for recording a video signal obtained by the imaging unit 10 in a predetermined format of 8 mm video.
This figure shows an NTSC camera-integrated 8 mm VTR with a built-in title image generator that is provided integrally with the camera.

As shown in the external perspective view of FIG. 3, the apparatus main body 30 is provided with an imaging lens 35 for guiding imaging light to the solid-state imager 1 of the imaging unit 10, and the imaging unit 10 captures an image. Electronic viewfinder 40 for monitoring the image of the subject, etc., and operation switches 31, 32, 33, 34a, 34b
Etc. are provided.

Further, as shown in the block diagram of FIG. 2, the imaging unit 10 includes a solid-state imager 1 formed by a charge-coupled device (CCD). The solid-state imager 1 is driven by a CCD drive circuit 3 that operates based on the above-mentioned operation, and supplies an imaging output of a subject image obtained by the solid-state imager 1 to an imaging processing signal circuit 4.

The imaging signal processing circuit 4 forms a luminance signal (Y) indicating an object image and color difference signals (RY) and (BY) from the imaging output of the solid-state imager 1. The luminance signal (Y) and the color difference signals (RY) and (BY) formed by the imaging signal processing circuit 4 are respectively converted into an imposition circuit 5,
The signal is supplied to the NTSC encoder 8 via the channels 6 and 7.

The NTSC encoder 8 forms an NTSC video signal representing a subject image from the luminance signal (Y) and the color difference signals (RY) and (BY). The video signal formed by the NTSC encoder 8 is supplied to a 1-bit analog-to-digital (A / D) conversion circuit 11, and performs a recording operation in a predetermined format of 8 mm video with the electronic viewfinder 40. The data is supplied to the recording unit 20.

The 1-bit A / D conversion circuit 11 is composed of a level comparator that compares a luminance signal (Y) of the video signal supplied from the NTSC encoder 8 with a predetermined signal level, and converts the luminance signal (Y). When the level is lower than the predetermined signal level, it is indicated by “1”, and when the level is higher, “0”
Is formed. The image data formed by the A / D conversion circuit 11 is written to the memory 13 via the titler circuit 12.

The memory 13 is composed of two-chip static RAMs 13a and 13b capable of storing one image data formed by the A / D conversion circuit 11, respectively. The memory 13 is supplied with backup power from a lithium battery 14 so that data is not lost even when the main power is shut off. This lithium battery 14
This voltage drop is monitored by a voltage drop detection circuit (not shown), and a warning is displayed in the electronic viewfinder 40 before the backup function of the memory 13 is lost.

The titler circuit 12 is supplied with a synchronizing signal from the synchronizing signal generating circuit 2, forms write / read address data of the memory 13 based on the synchronizing signal, and writes the image data into the memory 13. Performs read control. The titler circuit 12 supplies the three primary color signals (R, G, B) serving as a title image to the conversion circuit 15, and the respective impose circuits 5, 6 according to the image data read from the memory 13. , 7 are controlled.

The conversion circuit 15 converts the primary color signals (R, G, B) supplied from the titler circuit 12 into a luminance signal (Y) and color difference signals (RY), (BY). The signals are supplied to the imposition circuits 5, 6, 7.

(G1-2) Configuration of Titler Circuit (FIG. 1) FIG. 1 is a circuit diagram showing a configuration of the titler circuit 12. As shown in FIG.

In FIG. 1, the titler circuit 12 includes three shift registers 51, 55a and 55b, an image selection circuit 60, a color designation circuit 70, an H address counter 53, and a V address counter 54.
And the like.

The three shift registers 51, 55a, and 55b are formed of shift registers having a predetermined number of bits. The shift register 51 is a shift register for writing data, and has a serial input terminal connected to an image data input terminal 81.
It is connected to the. Further, each of the shift registers 55a, 55
b denotes a shift register for reading. Each parallel input terminal is connected to the output terminal of each of the latch circuits 52a and 52b, and each serial output terminal is connected to the image selection circuit 60. The parallel output terminal of the shift register 51 and the input terminals of the latch circuits 52a and 52b are connected to the memory 13 via a data input / output terminal group 82.

The image selection circuit 60 includes a NAND circuit 62b to which the serial output terminal of the shift register 55a is connected, and an AND circuit
A NAND circuit 62a and an AND circuit 63b to which a serial output terminal of the shift register 55b is connected; a NOT circuit 64 whose output terminal is connected to the NAND circuit 62a;
An OR circuit 65 whose output terminal is connected to the circuit 63a, and the AND circuit 65
It comprises a NAND circuit 66 whose output terminal is connected to the circuit 63b. The output terminals of the NAND circuits 62a and 62b are connected to the AND circuits 63a and 63b, respectively. The output terminals of the AND circuits 63a and 63b are connected to the color designating circuit 70. Furthermore, the above NAND circuit
62b, the NOT circuit 64, the OR circuit 65, and the NAND circuit 66
Are connected to a first image designation input terminal 91 connected to a system controller (not shown). A second image designation input terminal 92 connected to the system controller is connected to the other input terminals of the OR circuit 65 and the NAND circuit 66. It should be noted that this system controller provides image designation data to the first and second image designation input terminals 91 and 92 in response to the operation of a third operation switch 33 provided on the apparatus main body 30. Has become.

The color specifying circuit 70 is connected to one of the ANs of the image selecting circuit 60.
Three AND circuits 71R, 71G, 71B connected to the D circuit 63a
And three AND circuits 7 connected to the other AND circuit 63b
2R, 72G, 72B and the output terminals of the AND circuits 71R, 71G, 71B are connected to one input terminal, respectively, and
The output terminals of the D circuits 72R, 72G, 72B are composed of three OR circuits 73R, 73G, 73B connected to the other input terminals, respectively. Of these, color designation data is given to the other input terminals of the AND circuits 71R, 71G, and 71B from a system controller (not shown) in accordance with the operation of a fourth operation switch 34a provided in the apparatus main body 30. Each color specification input terminal 94R, 94
G and 94B are connected respectively. In addition, the above AND circuit
The other input terminals of 72R, 72G, and 72B have respective color designation input terminals 95R, to which color designation data is given from a system controller (not shown) in response to the operation of a fifth operation switch 34b provided in the apparatus main body 30. 95G and 95B are connected respectively. Furthermore, the output terminals of the OR circuits 73R, 73G, and 73B are connected to the color signal output terminals 96R, 96G, and 96B, respectively, and are also connected to the imposition control signal generation circuit 80. This impose control signal generation circuit 80
It is connected to each of the above-mentioned imposition circuits 5, 6, 7 via an impose control signal output terminal 99.

The H address counter 53 is formed by a counter of a predetermined bit, and its clock input terminal is connected to a clock input terminal 97, its reset input terminal is connected to a horizontal synchronization input terminal 98H, and A parallel output terminal of data is connected to the memory 13 via an address data output terminal group 83. The V address counter 54 is formed by a counter of a predetermined bit, and its clock input terminal is connected to the horizontal synchronization input terminal 98H.
And the reset input is connected to the vertical sync input
98V, and a parallel output terminal of vertical address data is connected to the memory 13 via an address data output terminal group 84. Note that the above clock input terminal
97 is supplied with a clock signal having a predetermined frequency.

Further, the titler circuit 12 has a registration operation designation input terminal 87 to which the first operation switch 31 provided on the apparatus main body 30 is connected, and an insertion terminal to which the second operation switch 32 is connected. An operation designation input terminal 88 is provided to receive an operation of the first operation switch 31 to perform a registration operation described later, and to execute a second operation switch
32 operations are received to perform an insertion operation described later.

Further, the titler circuit 12 includes the memory
A control terminal group 86 for controlling writing and reading of the memory 13 including a chip select terminal 85 for outputting selection data of the two static RAMs 13a and 13b constituting the memory 13.
Are provided, and an input terminal 89 and a ground terminal 90 of the driving power supply are provided.

(G1-3) Operation of Titler Circuit The titler circuit 12 performs a registration operation of writing image data of a title image into the memory 13 by operating a first operation switch 31 provided in the apparatus main body 30.
By operating the second operation switch 32, the memory 13
Is performed to read out the image data stored in the image data and output it as a title image signal.

In this insertion operation, the titler circuit 12 selects the title image signal formed from the image data of the title image stored in the memory 13 by operating the third operation switch 33. By operating the fourth and fifth operation switches 34a and 34b, the color of the title image signal is designated.

 Hereinafter, these operations will be described in detail.

(G1-3-1) Registration operation (FIGS. 1 and 4) The titler circuit 12 is connected to the first operation switch 31.
When the operation is received, a registration operation of writing the image data supplied from the A / D conversion circuit 11 into the memory 13 is performed.

That is, when a registration operation is designated by operating the first operation switch 31 while an image arbitrarily drawn on the panel 100 is captured by the imaging unit 10, the titler circuit 12
Stores control data for write control in the memory
In addition to supplying to the memory 13, selection data for selecting one of the two static RAMs 13 a and 13 b to which image data is to be written is supplied to the memory 13 by operating an operation switch (not shown).

The write data shift register 51 converts image data of an image captured by the imaging unit 10 serially input from the A / D conversion circuit 11 through the image data input terminal 81 into parallel data. From the data input / output terminal group 82 to the memory 13.

Here, the H address counter 53 receives 1 by a horizontal synchronization signal supplied through the horizontal synchronization input terminal 98H.
The horizontal address data is formed by counting clock pulses supplied via the clock input terminal 97 while resetting each horizontal scanning period. The horizontal address data is supplied from the address data output terminal group 83 to the address terminals of the memory 13 via the address bus. The V address counter 54 resets the vertical synchronizing signal supplied through the vertical synchronizing input terminal 98V every one vertical scanning period, while the horizontal synchronizing signal supplied through the horizontal synchronizing input terminal 98H. To form vertical address data. The vertical address data is supplied from the address data output terminal group 84 to the address terminals of the memory 13 via the address bus.

Therefore, the memory 13 has the chip select terminal
The image output from the write data shift register 51 to the address specified by the horizontal address data and the vertical address data of the static RAM specified by the selection data of each of the static RAMs 13a and 13b supplied from 85. Data is written. Note that, in this embodiment, the registration operation is performed in accordance with 2 shown in FIGS. 4A and 4B.
The following description will be made assuming that the image data of the title images a and b are written one by one in each of the static RAMs 13a and 13b constituting the memory 13.

(G1-3-2) Insertion operation (FIGS. 1, 5, and 6) The titler circuit 12 is connected to the second operation switch 32.
When the above operation is received, an insertion operation of reading out the image data written in the memory 13 by the above-mentioned registration operation and outputting it as a title image signal is performed. At this time, the title image output from the titler circuit 12 is supplied with the data D1 given to the first image designation input terminal 91 and the second image designation input terminal 92 by operating the third operation switch 33. Is selected from the four title images shown in Table 1 by the data D2 given to
4. The color is designated by operating the fifth operation switch.

That is, upon receiving the operation of the operation switch 32, the titler circuit 12 supplies a read signal to the memory 13, supplies horizontal address data from the H address counter 53, and supplies vertical address data from the V address counter 54. give. Further, the titler circuit 12 supplies each of the static signals supplied from the chip select terminal 85 to the memory 13 at twice the timing of the clock pulse supplied to the H address counter 53 via the clock input terminal 97. By switching the selection data of RAM13a, 13b, these static RAM1
Image data stored at the same addresses 3a and 13b are alternately read. Then, the image data of the title image a read from the one static RAM 13a is supplied to the read data shift register 55a via the latch circuit 52a, and the read data shift register 55a outputs the serial data a1. And supplied to the image selection circuit 60. The image data of the title image b read from the other static RAM 13b is supplied to the read data shift register 55b via the latch circuit 52b, and the read data shift register 55b outputs the serial data b1. And is supplied to the image selection circuit 60.

When writing and reading of image data to and from the memory 13 are performed by serial data, as shown in FIG. 5, the selection data of each of the static RAMs 13a and 13b is switched at twice the timing of the clock pulse. Thereby, during a period equal to the cycle period of the A / D conversion circuit 11 forming the image data written to the memory 13,
The image data stored at the same address of each of the static RAMs 13a and 13b is alternately read, and the image data of the title image a read from the one static RAM 13a is set as serial data a1, and the image data of the title RAM a is read from the other static RAM 13b. What is necessary is just to supply the read image data of the title image b to the image selection circuit 60 as serial data b1.

Here, an image selection circuit composed of the above-described logic elements
Table 2 shows the truth values of the 60 input / output data. In Table 2, a2 is data output from the one AND circuit 63a, and b2 is data output from the other AND circuit 63b.

That is, when the image selection circuit 60 supplies “0” as the data D1 to the first image designation input terminal 92, the image selection circuit 60 outputs “0” as the data D2 to the second image designation input terminal 92.
Is supplied, the one AND circuit 63a outputs "0" as the data a2, and the other AND circuit 63b outputs the image data b1 of the title image b as the data b2.

When “0” is supplied as data D1 to the first image designation input terminal 91 and “1” is supplied as data D2 to the second image designation input terminal 92, AND circuit 63a outputs image data a1 of the title image a as data a2, and outputs the other AND circuit 6
3b is image data b1 of the title image b as data b2
When both the data a1 and b1 are "1", only the other AND circuit 63b outputs the image data b1 of the title image b as the data b2.

Further, data is input to the first image designation input terminal 91.
When "1" is supplied as D1 and "0" is supplied as data D2 to the second image designation input terminal 92, the one AND circuit 63a is used as the data a2 of the title image a. Outputs image data a1 and outputs the other AND
The circuit 63b outputs the image data b1 of the title image b as the data b2. When the data a1 and b1 are both "1", only the one AND circuit 63A is the image of the title image a as the data a2. Output data a1.

When “1” is supplied as data D1 to the first image designation input terminal 92 and “1” is supplied as data D2 to the second image designation input terminal 92, AND circuit 63a outputs image data a1 of the title image a as data a2, and outputs the other AND circuit 6
3b outputs "0" as data b2. Therefore, based on the image designation data D1 and D2 given through the input terminals 91 and 92, the image selection circuit 60 determines the priority of the superposition of the image data as shown in Table 1 above. The image data can be synthesized.

The data a2 output from the one AND circuit 63a is supplied to one end of three AND circuits 71R, 71G, and 71B of the color specifying circuit 70, and the color specifying input terminals 94R, 94G, The color is designated by the color designation data supplied from 94B to the other ends of the AND circuits 71R, 71G, and 71B.
It becomes a primary color signal (R, G, B) and is supplied to one end of each of the OR circuits 73R, 73G, 73B as an image signal of the title image a. Similarly, the data b2 output from the other AND circuit 63b is connected to the three AND circuits 72R and 72R of the color specifying circuit 70.
2G, 72B, and is designated by the color designation data supplied from the color designation input terminals 95R, 95G, 95B to the other ends of the AND circuits 72R, 72G, 72B by operating the operation switch 34b. The three primary color signals (R, G, B) are obtained as the image signals of the title image b.
R, 73G, and 73B are supplied to the other ends. Then, the image signals of the title images a and b are ORed by the OR circuits 73R, 73G and 73B, and output from the color signal output terminals 96R, 96G and 96B as title image signals.

Accordingly, the titler circuit 12 reads the title image a read from one of the static RAMs 13a constituting the memory 13 by operating the third operation switch 33.
The image signal of the title image c shown in FIG. 6A formed from the image data of FIG. 6 and the title image shown in FIG. 6B formed from the image data of the title image b read from the other static RAM 13b constituting the memory 13. The image signal of d, the image signal of the title image e shown in FIG. 6C in which the title image a is superimposed on the title image b, or the image signal of the title image b is superimposed on the title image a with priority on the title image b. Any one of the image signals of the title image f shown in FIG. 6D can be formed and output.

Further, the above-described imposition control signal generation circuit 80
An impose control signal (BLK) is generated from the logical sum of the output data of the OR circuits 73R, 73G, and 73B, and the respective impose circuits 5,
The title image signals output from the respective color signal output terminals 96R, 96G, and 96B via the conversion circuit 15 are output from the imaging signal processing circuit 4 by the impose circuits 5, 6, and 7. Insert it into the signal.

In the title image signal output from the titler circuit 12, a combination of the three primary color signals (R, G, B) is specified according to the operation of the fourth and fifth operation switches 34a, 34b. That is, the titler circuit 12
By operating the operation switch 34a, the title image a
The eight colors can be designated cyclically, and the eight colors of the title image b can be designated cyclically by operating the fifth operation switch 34b. That is, the color specifying circuit 70 can specify the color of the superimposed image data as one color by specifying the combination of the three primary color signals of the superimposed image data. At this time, the specified color is displayed on the electronic viewfinder 40 in characters or the like. The color designation of the title image by the operation of the fourth and fifth operation switches 34a and 34b is as follows.
The above operation can be performed even when the insertion mode is designated by operating the second operation switch 32. The video signal in which the image signal of the title image is inserted is recorded by the recording unit 20 while the title is being recorded. The color of the image can be switched.

(G-2) Application Example In the above-described embodiment, the present invention is applied to a camera-integrated VTR with a built-in title image generating device capable of recording image data of two title images in the memory 13. It is also possible to apply the present invention to a title image generating device capable of recording image data of two or more title images in a memory. For example, an image of an input video signal supplied from a reproduction side VTR or the like can be used. The present invention is also applicable to a title image generator used in a stationary titler, a telop, etc., which is stored in a memory and formed by synchronizing a title image signal from this image data with a reproduced video signal of a VTR or another input video signal. Is possible.

H. Effects of the Invention The present invention provides a title image in which a plurality of image data read from the memory means is subjected to color designation processing for each image, and the respective images based on the image data subjected to the color designation processing are superimposed. An image signal is formed from the image data.
Therefore, the title image generating device according to the present invention uses a plurality of pieces of image data stored in the memory means,
Image signals of various title images in which another title image having a different color is superimposed on a certain title image can be formed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a titler circuit of a camera-integrated VTR to which the present invention is applied, FIG. 2 is a block diagram showing a configuration of the camera-integrated VTR, and FIG. 1 is an external perspective view of a body VTR. FIGS. 4A and 4B are schematic diagrams showing title images of image data written to the memory from the titler circuit in the registration operation, and FIG. 4A is written to one static RAM constituting the memory. FIG. 4B shows a title image of the image data, and FIG. 4B shows a title image of the image data written to the other static RAM constituting the memory. FIG. 5 is a schematic diagram for explaining reading of serial image data from the memory. 6A to 6D are schematic diagrams showing a title image formed from the image data output from the titler circuit in the inserting operation, and FIG. 6A is a diagram showing the title image formed from the image data read from the one static RAM. FIG. 6B is a title image formed from image data read from the other static RAM, and FIG. 6C is a title image formed from the other static RAM with priority given to image data read from the one static RAM. The title image formed from the image data superimposed on the image data read from the sixth image is an image superimposed on the image data read from the one static RAM with priority given to the image data read from the other static RAM Each shows a title image formed from data. 11 A / D conversion circuit 12 Titler circuit 13 Memory 13a, 13b Static RAM 51, 55a, 55b Shift register 53 H address counter 54 V address counter 60 Image selection Circuit 70 ... Color designation circuit

Claims (1)

(57) [Claims] 1. A means for digitizing an input video signal to form image data; a memory means for storing a plurality of types of image data; and a priority order for superposing a plurality of types of image data read from the memory means. A title image generating apparatus comprising: processing means for synthesizing according to the above, and specifying a color of each of the superimposed image data; and means for forming an image signal of a title image from the image data output from the processing means.