JP2539936B2 - Charge transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly to a charge coupled device that can reduce a step on a substrate surface and has an electrode structure with good transfer efficiency.

[Conventional technology]

FIG. 3 (g) is a cross-sectional view of a polysilicon gate electrode of a charge coupled device (CCD), which is a conventional charge transfer device, in which 1 is a p-type silicon substrate and 2 is a Is an n ⁻ type diffusion layer, 3 is a gate insulating film, 4 is a first layer polysilicon gate electrode, and 7 is a second layer polysilicon gate electrode.

3 (a) to 3 (f) are cross-sectional views of each step of the main manufacturing process of the device of FIG. 3 (g), and the manufacturing method thereof will be described below. .

First, as shown in FIG. 3A, an n ⁻ type impurity diffusion layer 2 is formed on a p type silicon substrate 1 by ion implantation. Next, as shown in FIG. 3 (b), the surface of the substrate 1 is oxidized to form a silicon dioxide film 3 on the surface, and a first-layer polysilicon film 4 is deposited thereon by a CVD method. Next, as shown in FIG. 3C, a resist is applied and a resist 5 is processed into a predetermined pattern through a photolithography process. Then, as shown in FIG. 3D, the first layer polysilicon film 4 and the oxide film 3 are etched using the resist 5 as a mask to process the first layer polysilicon into a predetermined pattern.
Next, as shown in FIG. 3 (e), after the silicon dioxide film 3 is formed on the entire surface by oxidizing the substrate surface, CV
The second-layer polysilicon film 7 is deposited by the D method. Thereafter, as shown in FIG. 3 (f), a resist is applied and a resist is processed into a predetermined pattern through a photolithography process. Then, the second layer polysilicon 7 is etched by using the processed resist 8 as a mask and processed into a predetermined pattern.
The two-layer polysilicon gate electrode shown in FIG. 3G is completed.

As shown in FIG. 3 (g), the polysilicon electrode formed through the steps described above has a gate insulating layer Δg ₃ between the first-layer polysilicon film 4 and the second-layer polysilicon film 7. compared to the film thickness t _ox of the film 3 can be formed so as to approximately Δg ₃ ~3Δt _ox be larger.

Next, the charge transfer operation of the CCD having the above two-layer polysilicon electrode structure will be described with reference to FIG.

FIG. 4 (a) shows how four-phase clocks Φ1 to Φ4 are applied to the respective electrodes, and it is assumed that the four-phase clocks shown in FIG. 5 are used. At time t = t ₁ shown in FIG. 5, it is assumed that transfer charges exist below the electrodes to which the clocks of Φ1 and Φ2 are applied as shown in FIG. 4 (b). (In the figure, indicates transfer charge). Then at time t
= T ₂ , as shown in FIG. 4 (c), the clock of Φ3 changes from L → H, so that a potential well is formed under the electrode to which the clock of Φ3 is applied, and the transfer charge is Φ.
It spreads under the electrodes to which the clock of 1, Φ2, Φ3 is applied. Next, at time t = t ₃ , the state of transfer charge transfer becomes as shown in FIG. 4 (d) while the clock of Φ1 changes from H to L, and the clock of Φ1 changes from H to L. By doing so, the potential under the electrode to which the clock of Φ1 is applied becomes shallow, and the transfer charge moves to below the electrode to which the clock of Φ2 and Φ3 is applied. At this time the third
As shown in FIG. 3G, the first-layer polysilicon 4 and the second-layer polysilicon 4
The interval Delta] t _ox of the gate 7 of the layer polysilicon interval △ g ₃ to 3
because it has been formed about t _ox, between the gate shown in Figure 4 (d) by the dotted line circle (A unit) can not "GuHomi" potential, be transferred without any loss of charge You can As a result, at time t = t ₄ shown in FIG.
As shown in FIG. 6E, the transfer of charges from the under-electrode region to which the clocks of Φ1 and Φ2 are applied to the under-electrode region to which the clocks of Φ2 and Φ3 are applied is completed.

As described above, in the electrode structure formed by the process as shown in FIG. 3, the transfer electrode interval Δg ₃ can be formed so narrow as to prevent transfer loss during charge transfer.
In the structure manufactured by this step, after processing, as shown in FIG. 3 (g), a step of the polysilicon gate electrode is generated on the substrate surface, and the covering property is deteriorated when the upper layer film is formed in the subsequent step, and the upper layer is formed. There is a drawback that the insulating property and conductivity of the film are deteriorated, and when this upper layer film is used as a light-shielding film, a sufficient light-shielding effect cannot be obtained due to its poor coverage. There was a flaw.

Therefore, an attempt has been made to eliminate the step difference of the gate electrode and reduce the deterioration of the covering property of the upper layer film by forming the transfer electrode with only one layer of polysilicon.

That is, FIGS. 6 (a) to 6 (d) are cross-sectional views in each manufacturing process of a transfer electrode of single-layer polysilicon as another conventional example, and the manufacturing method will be described below with reference to the drawings. . However, in the figure, the same reference numerals as those in FIG. 3 indicate the same parts, and the description thereof will be omitted.

As shown in FIGS. 6 (a) to 6 (c), an n ⁻ diffusion layer 2 is formed on a substrate 1, and a resist is applied on the polysilicon film 4 deposited via an insulating film 3 thereon. It is the third example of the above-mentioned conventional example that a photolithography process is used to form a predetermined pattern.
This is similar to the case shown in FIGS. However,
Here, unlike the conventional example shown in FIG.
As shown in FIG. 6 (c), the pattern is processed so as to have the minimum size Δg ₄ that can be processed, and the polysilicon film 4 is etched using this as a mask. As shown in FIG. 6 (d). , The distance between adjacent gate electrodes is about this distance (Δ
g ₄ ′).

The transfer electrode formed through such a step has a step difference smaller than that in the case where the transfer electrode is formed by using two-layer polysilicon, and its coverage is deteriorated when an upper layer film is formed in a later step. It is possible to form the electrode with a low resistance by adopting not only polysilicon as a material for the transfer electrode but also a polycide structure in which tungsten silicide, for example, is stacked, It can also serve as a light-shielding film.

[Problems to be Solved by the Invention]

As described above, the conventional CCD in which the transfer electrode is formed of only one-layer polysilicon has an advantage that the step is reduced as compared with the case where the transfer electrode is formed using two-layer polysilicon. On the other hand, the distance between transfer electrodes that can be formed is determined by the minimum processing size of the photoresist and the processing accuracy of the polysilicon using the photoresist, as shown in FIG. 6 (c). comprising separation distance of polysilicon Delta] g ₄ 'is wider than the transfer electrode spacing Δg ₃ ~3t _ox when processed (FIG. 3 (g)) using a double-layer polycrystalline silicon.

For example, in the above-mentioned two-layer polysilicon gate electrode structure, when the thickness _tox of the gate insulating film 3 is formed to be, for example, 0.05 to 0.1 μm, the interval Δg ₃ between adjacent gate electrodes is 0.15 to 0.3.
However, in the above-mentioned one-layer polysilicon gate electrode structure, the minimum processable dimension Δg _{4 of the} photoresist 5 is limited to about 0.4 μm by the photoengraving technique. Therefore, the gap Δg ₄ ′ between the gate electrodes formed using this pattern as a mask is 0.6
It was about μm.

Generally, when the drive clock is applied, the n formed under the gate insulating film 3 increases as the film thickness _tox of the gate insulating film 3 increases.
^- Potential levels of diffusion layer 2 tends to increase. Therefore, if the space between the gate electrodes becomes wide,
As shown in the figure, the effective gate insulating film thickness t _ox ′ between the end of the gate electrode 4 and the n ⁻ diffusion layer 2 region corresponding to the gate electrode is between the gate electrode 4 and the n ⁻ diffusion layer 2. _Is larger than the gate insulating film thickness _tox of the gate electrode 4 and is higher than the potential level of the n ⁻ diffusion layer below the gate electrode 4,
The potential level of the n ^- diffusion layer becomes high, resulting in a potential level difference ΔΦ between them.

Next, the charge transfer operation when such a potential level difference occurs will be described with reference to FIG. FIG.
Then, four-phase clocks Φ1 to Φ4 are added, and the clock shown in FIG. 5 is used as this clock, as shown in FIG. 7 (b), under the electrodes to which the clocks of Φ1 and Φ2 are applied at time t = t _1. It is the same as in FIGS. 4 (a) and 4 (b) in which the transfer electrode is formed by using the two-layer polysilicon, that the transfer charge exists. In this case, as in FIG. 4 (c), FIG. 7 (c) shows the case where Φ3 changes from L → H at time t = t ₂ .
Shown in After this, at time t = t ₃ , the clock of Φ1 is changed from H → L.
In the middle of the change to, the transfer charge is transferred from the charge transfer channel area under the electrode to which the clock Φ1 is applied to the clock Φ1.
2 moves to the charge transfer channel region under the electrode to which 2 is applied, but as described above, the separation interval Δg ₄ ′ of the transfer electrode 4 is applied.
But in order to be wider than the transfer electrode interval Δg ₃ ~3t _ox when processed using a two-layer polysilicon, n ^- in the diffusion layer 2, the difference in potential level below between under the transfer electrodes and the transfer electrodes This causes a potential "dip" in the portion indicated by the dotted circle (B portion) in FIG. 7 (d). Therefore, during transfer, a part of the charge remains in this recess, causing a transfer loss as shown in FIG. 7 (e).

The present invention has been made in order to solve the above-mentioned problems, and can flatten the transfer electrodes, and even if the separation intervals of the transfer electrodes are wide, the above-mentioned potential dent occurs. It is an object of the present invention to obtain an electrode transfer device having a CCD capable of reducing the transfer loss and having a low transfer loss.

[Means for solving problems]

In the charge transfer device according to the present invention, in the CCD electrode structure formed on the semiconductor substrate or on the semiconductor layer, the insulating film on the charge transfer channel region in which the transfer electrode does not exist in the upper portion and the transfer electrode in the upper portion are formed. It has a higher dielectric constant than the existing insulating layer on the charge transfer channel region.

[Action]

In the present invention, the insulating layer on the charge transfer channel region and on the region where the transfer electrodes are separated by the insulating layer is on the charge transfer channel region and on the region where the transfer electrodes are on the insulating layer. Has a higher dielectric constant than that of the insulating layer of the charge transfer channel region, the separation distance of the transfer electrodes is equal to that of the insulating layer on the charge transfer channel region when the permittivity of the insulating layer is equal under the transfer electrode and under the transfer electrode. Even if the potential “dent” formed in the part corresponding to the transfer electrodes is wide enough to cause the loss of the transfer charge, the potential “dent” formed in the separation part of the transfer electrode in the charge transfer channel region. ”Can be reduced, and charge transfer loss can be reduced.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a manufacturing process of a CCD which is a charge transfer device according to an embodiment of the present invention. The same reference numerals as those in FIGS. 3 to 6 indicate the same or corresponding portions, and 5a and 5c are photoresists. 5c is an oxide film and 6 is a silicon nitride film.

 Next, an example of the manufacturing method of the present invention will be described.

First, as shown in FIG. 1 (a), a p-type (or n-type) silicon substrate 1 in which p-type impurity ions such as boron are implanted at a concentration of ˜1 × 10 ¹⁵ cm ⁻³ is used at the above concentration. Into the formed p-type well, n-type impurity ions such as phosphorus are added.
Injection at 0keV, 3 × 10 ^{12 -4} × 10 ¹² cm ^-2 , then 1050-11
Heat treatment at 00 ℃ for 15 minutes to 1 hour, layer thickness 0.3 to 1 μm
N ⁻ diffusion layer 2 is formed.

Next, as shown in FIG. 1 (b), the surface of the substrate is oxidized to form a silicon dioxide film of about 0.05 to 0.2 μm, and then a polysilicon film 4 is deposited to 2000 to 4000 Å by a CVD method.

Next, as shown in FIG. 1 (c), a first photoresist 5a is formed on the entire surface of the substrate by 1.7 μm, and an oxide film 5b is formed thereon by 0.1 to 0.2.
μm, and a second photoresist 5c on it 0.5 μm
To form a three-layer resist. First, the second resist 5c is subjected to a photoengraving process to have a predetermined pattern width, and
The minimum size (~ 0.4 μm) that can be machined for each pattern interval Δg ₁
m) to be processed. Then, using the processed second photoresist 5c film as a mask, the underlying oxide film 5b is etched by using anisotropic etching such as RIE, and the second resist 5c and the oxide film 5b are removed. The first photoresist 5a is etched as a mask. Finally, the polysilicon 4 is similarly etched by anisotropic etching using the first resist 5c, the oxide film 5b, and the first resist 5a thus processed into a predetermined pattern as masks. Etching the gate spacing Δ
A single-layer gate electrode of g ₁ ′ (˜0.6 μm) is formed. In the processing using such a three-layer resist structure of the thick lower layer resist 5a, the oxide film 5b, and the thin upper layer resist, it is possible to prevent the influence of the step of the underlayer, increase the resolution, and reduce the influence of the reflection of the underlayer film. Therefore, a fine pattern can be obtained.

Next, the silicon nitride film 6 is deposited by CVD as shown in FIG.
It is deposited on the entire surface by the method. The thick film is made thicker than the oxide film 3. By doing so, as shown in FIG. 9, the oxide film 3 exists below the polysilicon 4 of the gate electrode, and the nitride film 6 exists between the polysilicon 4 and the polysilicon 4 as an insulating layer.

In such a buried channel type MOS structure, the channel potential increases as the capacitance with the electrode decreases. This is because the potential between the gate electrodes is high as described above. However, as shown in FIG. 9, when the nitride film 6 is present on the channel between the gate electrodes, the nitride film has a higher dielectric constant than the oxide film (about twice that of the oxide film), so that the film below The capacitance Cg with the channel is about the same as the capacitance C _L immediately below the gate electrode, although the effective insulating film thickness (in the diagonal direction) is thicker than immediately below the gate electrode. Therefore, the channel potential under the gate electrode becomes almost the same as that of the other region, and the "dent" can be eliminated.

Next, the charge transfer operation of such an embodiment of the present invention will be described.

The four-phase clocks Φ1 to Φ4 are added in FIG. 2 (a), the clock shown in FIG. 5 is used as this clock, and as shown in FIG. 2 (b), the clocks Φ1 and Φ2 are generated at time t = t _1. The fact that the transfer charges are present in the charge transfer channel region under the applied electrode is the same as in the case of the charge transfer operation example shown in the conventional example. In this case, FIG. 2 (c) shows the case where Φ3 changes from L → H at time t = t ₂ similarly to FIG. 7 (c). At this time, the charges are distributed in the charge transfer channel region below the electrodes to which the clocks of Φ1, Φ2, and Φ3 are applied. Thereafter, at the time t = t ₃ , the transfer charge is transferred from the charge transfer channel region under the electrode to which the clock Φ 1 is applied to the clocks Φ 2, Φ while the clock of Φ 1 is changing from H to L.
3 moves to the charge transfer channel region under the electrode to which 3 is applied. At this time, in the charge transfer channel region under the separation of the transfer electrodes, according to the present invention, a dotted circle mark (B) in FIG.
Part), the transfer charge can move to the charge transfer channel region under the electrodes to which the clocks Φ2 and Φ3 are applied without receiving transfer loss.

Although the silicon nitride film is used as the film having a high dielectric constant in the above-mentioned embodiment, the material used is not limited to this, and a dielectric material having a higher dielectric constant than the insulating film directly below the gate, such as Ta ₂ O ₅ , is used. Any insulating film having a certain ratio may be used.
The insulating film does not have to be a film made of a single material, and may be a multi-layer film such as a silicon oxide film and a silicon nitride film.

Further, in the above embodiment, the case where the transfer electrode is polysilicon has been described, but the material of the electrode is not limited to polysilicon, and for example, a polycide structure formed by depositing tungsten silicide on polysilicon, a metal such as Al, etc. Any conductive material that can serve as an electrode can be applied.

Furthermore, in the above-described embodiment, the case where the charge transfer channel region is n-type has been described, but it is needless to say that it is not limited to this conductivity type.

Further, in the above embodiment, the case where the four-phase clock is used as the transfer clock is shown, but the number of phases of this transfer clock may be any number.

〔The invention's effect〕

As described above, according to the charge transfer device of the present invention, a dielectric constant of an insulating layer on another charge transfer channel region is higher on a region corresponding to a lower portion between transfer electrodes in the charge transfer channel region. Since an insulating layer having a high charge transfer rate is formed, the transfer loss at the time of charge transfer can be reduced to such an extent that the transfer loss at the time of charge transfer is not a problem even if the electrode separation distance of the CCD electrodes is wide enough to cause the transfer loss at the time of charge transfer. Further, it is possible to reduce the step difference on the surface of the substrate that occurs after the electrode is processed, and further it is possible to simplify the processing process.

[Brief description of drawings]

1 (a) to 1 (e) are cross-sectional views showing a process of manufacturing a CCD of a charge transfer device according to an embodiment of the present invention, and FIG. 2 (a).
~ (E) is a diagram showing the potential in the charge transfer channel region for explaining the operation of the present invention, Fig. 3 (a) ~.
5G is a cross-sectional view showing a conventional CCD manufacturing process, FIGS. 4A to 4E are views showing the potential in the charge transfer channel region of the CCD shown in FIG. 3G, and FIG. The figure shows the waveforms and timings of the four-layer clock, and FIG. 6 (a)-
(D) is a sectional view showing a manufacturing process of a CCD according to another conventional example, FIGS. 7 (a) to 7 (e) are CCDs shown in FIG. 6 (d).
Showing potential in the charge transfer channel region of
FIG. 8 is a diagram for explaining the problems of other conventional examples, and FIG.
The drawings are diagrams for explaining the principle of the present invention. In the figure, 1 is a p-type silicon substrate, 2 is an n ^- diffusion layer, 3
Is a gate insulating film, 4 is polysilicon, 5a and 5c are photoresists, 5b is an oxide film, and 6 is a silicon nitride film. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A charge transfer device having a plurality of charge transfer electrodes on a charge transfer channel part region formed on a semiconductor substrate or a semiconductor layer with an insulating layer interposed between the charge transfer channel part region and the charge transfer channel part region. 2. The charge transfer device according to claim 1, wherein a portion of the insulating layer corresponding to a lower portion between the transfer electrodes has a higher dielectric constant than an insulating layer directly below the transfer electrodes.