JP2537575B2 - Method for manufacturing semiconductor wafer - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is intended to perform chamfering etching in which a plurality of mechanically chamfered semiconductor wafers are sandwiched and laminated after an entire surface etching step and immersed in an etching solution to etch only the chamfered portion. The present invention relates to a method for manufacturing a semiconductor wafer.

[0002]

2. Description of the Related Art As shown in FIG. 5, a conventional method for manufacturing a semiconductor wafer is obtained by slicing step A in which a single crystal semiconductor ingot is sliced into a thin plate by a diamond cutter or the like to obtain a semiconductor wafer, and slicing. Mechanical chamfering step B for mechanically removing the peripheral corners of the semiconductor wafer, and lapping step C for polishing both sides of the mechanically chamfered semiconductor wafer.
An entire surface etching treatment step D in which the semiconductor wafer subjected to the lapping treatment is immersed in an etching solution to etch the entire surface, and a polishing step E in which one or both surfaces of the semiconductor wafer subjected to the entire surface etching treatment are mirror-polished.
And consists of.

Surface roughness is formed on the surface of the chamfered portion of the semiconductor wafer by this conventional method by cutting with a diamond cutter or the like. If the surface of the chamfered portion is rough, there is a disadvantage that stains occur and thermal strain occurs.
As a means for eliminating the surface roughness of the chamfered portion, generally, the entire surface of the semiconductor wafer is immersed in an etching solution and the surface roughness is dissolved and removed by the etching solution. However, if the entire surface is etched, even the etching on the chamfered portion is also performed on the entire surface of the semiconductor wafer. Therefore, if the etching is performed until the surface roughness of the chamfered portion is eliminated, the crystal loss increases, while There is a problem that the removal of the surface roughness of the chamfered portion is not completed when the loss is reduced.

In order to solve this problem, a method for surface treatment of a semiconductor wafer is disclosed in which only the chamfered portion of the semiconductor wafer is immersed in an etching solution before the entire surface etching treatment (Japanese Patent Laid-Open No. 62-134935). Issue).

However, this document does not point out any problems in the case where the chamfered portion is etched before the lapping. In this case, there is a problem in that the lapping abrasive grains are present between the end surface portion of the chamfered portion which has become a smooth surface by the etching treatment and the lapping carrier, and the end surface portion of the chamfered portion is scratched and becomes rough. It was happening. If the chamfered surface is rough, it may come into contact with the semiconductor wafer container (made of polypropylene or polyethylene) and the container surface may be scraped, and the scraps may adhere to the surface of the semiconductor wafer, causing troubles in subsequent processes. Even if the chamfered part is etched, it still has a rough surface, which causes thermal stress in the manufacturing process of the semiconductor device, especially during heat treatment, and deteriorates the crystallinity of the wafer, and in the case of significant causes of cracks and damage. It was something that A further problem is that various kinds of stains are held in the valleys due to the roughness of the surface, which also causes the yield or the characteristic deterioration in the manufacturing process of the semiconductor device.

[0006]

DISCLOSURE OF THE INVENTION The present invention provides a semiconductor wafer which is capable of significantly improving the smoothness of the entire chamfered portion without causing scratches or roughness on the end surface of the chamfered portion due to lapping abrasive grains. It is intended to provide a manufacturing method.

[0007]

In order to solve the above problems, the first invention of the present application is obtained by a slicing step of slicing a single crystal semiconductor ingot into a thin plate by a diamond cutter or the like to obtain a wafer, and by this slicing. In the method for manufacturing a semiconductor wafer having a mechanical chamfering step of mechanically removing the peripheral corners of the wafer, after the mechanical chamfering step, a lapping step of polishing both sides of the wafer and then the lapping treatment. The entire surface of the wafer is acid-etched in order to remove the processing strain generated in the previous step by immersing the wafer in an acid-etching solution, and only the chamfered part of the wafer subjected to the whole-surface etching is again treated with the acid etching solution. Chamfer by dipping in chamfer and acid etching the chamfer to smooth the surface And an etching step, one or both sides of the entire surface etching treatment and chamfers etching processed wafers are those having a polishing step of mirror polishing. Further, the second invention of the present application is a slicing step of slicing a single crystal semiconductor ingot into a thin plate by a diamond cutter or the like to obtain a wafer, and mechanically removing a corner portion of a peripheral portion of the wafer obtained by this slicing mechanically. In the method for manufacturing a semiconductor wafer having a chamfering step, after the mechanical chamfering step, a lapping step of polishing both sides of the wafer, and then the processing that occurred in the previous step by immersing the lapping-processed wafer in an alkali etching solution An entire surface alkali etching step of alkali-etching the entire surface to remove the strain, and only the chamfered portion of the wafer subjected to the entire surface etching treatment is dipped in an acid etching solution to acid-etch the chamfered portion for smoothing the surface of the chamfered portion. Chamfered part etching process and this whole surface etching One or both sides of the sense and chamfers etching processed wafers are those having a polishing step of mirror polishing.

The lapping step is not particularly limited with respect to the grain size of the abrasive grains, but is carried out with an accuracy of 2 μm or less in the thickness variation treated with the # 500 to # 3000, preferably # 800 to # 2000 abrasive grains. Preferably. Further, it is preferable that the entire surface etching treatment is performed by alkali etching. Furthermore, it is preferable to carry out an etching treatment with a heated sodium hydroxide or potassium hydroxide aqueous solution as the entire surface etching step.

[0009]

The etching solution for the chamfered portion etching in the present invention is a known etching solution used for etching semiconductor wafers, for example, hydrofluoric acid (50%): nitric acid (70%): acetic acid 3: 5: 3. The mixed acid mixed in the ratio of is used.

The entire surface etching treatment in the present invention (treatment which is simply called etching in the past) is conventionally known acid etching, that is, room temperature etching with an aqueous solution of hydrofluoric acid, nitric acid and acetic acid or alkali etching, that is, sodium hydroxide. Alternatively, any etching such as heating etching with an aqueous solution of potassium hydroxide can be applied.

When acid etching is performed, the smoothness of the micro surface of the semiconductor wafer is improved, but the macro dimensional accuracy is degraded. On the other hand, when alkaline etching is performed, the dimensional accuracy of the macro of the semiconductor wafer is not deteriorated but the micro surface is roughened.

Therefore, if the etching of the entire surface of the alkali and the etching of the chamfered portion are combined, the advantage of the alkali etching that the dimensional accuracy of the macro does not deteriorate is utilized, and the smoothness of the chamfered portion is increased by the etching of the chamfered portion. There is an advantage that the disadvantage that the microscopic surface is roughened by is suppressed.

In the conventional method, the wafer main plane and the chamfer are mirror-etched at the same time by acid etching after the lapping and chamfering of the wafer are completed. However, the wafer chamfer has a higher etching rate than the main plane. However, the smoothness of the chamfered portion is often insufficient in the manufacturing process of the semiconductor integrated circuit device. Since at least one surface of the main surface of the wafer is further polished after etching, it has an ideal smooth surface, but the chamfered portion remains as etched and rough. For this,
In the present invention, etching is performed in a step different from the etching of the main plane so that only the chamfered portion is finished to be smooth.

Of course, when the chamfered portion is machine-finished and the abrasive grain size of diamond is smaller, the etching amount can be saved and a desired smooth surface can be obtained. Further, when the abrasive grain size of diamond is changed from # 800 to # 1500, for example, the main plane and the chamfered portion are etched at the same time, and the chamfered portion is finished into a perfect mirror surface, without etching in two steps as in the present invention. It is possible. The etching of the main plane is
Usually, the purpose is to eliminate mechanical strain on the main plane in the previous process.
Although 0 to 20 .mu.m is etched, the etching time of the chamfered portion is short in the usual process because of this.

In the etching of the chamfered portion, if the abrasive grain size of the diamond grindstone is, for example, # 3000, a satisfactory mirror surface finish can be achieved by the alkali etching, and the macro dimensional accuracy of the alkali etching can be maintained and the micro mirror surface can be obtained. It will be possible at the same time.

In the wafer lapping process, abrasive grains having a grain size of carborundum or alumina # 500 to # 3000 are used and both sides are free-lapping with abrasive grains, and in the lapping process, variations in flatness and thickness of the wafer are remarkable. It is improved, and the thickness variation is adjusted to at least 2 μm or less, and in some cases, to 1 μm or less. The wafer that has been subjected to such lapping is treated with, for example, 30% sodium hydroxide.
% Aqueous solution at about 100 ° C., the dimensional accuracy, that is, the variation in flatness and thickness is almost maintained, and the variation in thickness is at least 2 μm or less, and in some cases 1
It can be maintained at μm, and the processing strain on the main surface of the wafer due to lapping can be completely removed.

A wafer entirely etched with sodium hydroxide or potassium hydroxide has the same flatness and thickness variation as the lapping wafer, and has a surface roughness of approximately 5 to 5.
Since the thickness is 10 μm, the laminated wafers are brought into mating contact with each other due to the minute irregularities on the surface, and even if the wafer sandwiching laminated body is placed horizontally, or the central wafer does not fall off when rotated at high speed, the chamfering is smoothly performed. The air in the space where the etching progresses, and especially the transition between the chamfered portion and the main surface is such that the adjacent wafer main surfaces are appropriately close to each other and microscopically irregularities of the surface roughness of the lapping rough surface are formed. Is retained, the etching solution can be prevented from penetrating onto the main surface of the wafer, and since the effect is uniform over the entire transition area of the main surface and the chamfered portion of the wafer, partial etching proceeds, There is an advantage that the vicinity of the outer periphery of the main surface of the wafer is not unevenly etched. In this case, since the chamfered portion is already alkali-etched, the processing strain generated by the mechanical chamfering has already been removed, and the chamfered portion is selectively etched with a slight acid etching, and only the surface smoothing is performed. You can measure it,
Only the chamfered portion may be lightly etched. With this method, the cross-sectional shape of the chamfered portion can be maintained in a state close to that during machining, which is preferable when a special chamfered shape or precision is required.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The method of the present invention will be described below with reference to FIGS. FIG. 1 is a flowchart showing an example of the method of the present invention. In the figure, A, B, C, and D are the same slicing step, mechanical chamfering step, lapping step, and entire surface etching step as those in the conventional method shown in FIG. 5 (conventionally simply referred to as an etching step). Is. F is a chamfered portion etching step of sandwiching and laminating a plurality of mechanically chamfered semiconductor wafers whose entire surface has been etched, immersing them in an etching solution and etching only the chamfered portion. E is a polishing step similar to the conventional method shown in FIG.

In the above process, the slicing process A,
The mechanical chamfering step B, the lapping step C, the entire surface etching step D, and the polishing step E are publicly known, and detailed description thereof will be omitted. As described above, as the entire surface etching treatment, either acid etching or alkali etching can be applied, but each has its advantages and disadvantages, and which etching is to be used is appropriately determined according to the intended use of the final product. do it.

However, as a means for solving the problem of the present invention, alkali etching is preferable as the entire surface etching treatment. Of course, even with acid etching, etching should not be performed until the macro flatness and thickness variations are aggravated. It should be noted that if the acid etching is strongly performed, the micro surface accuracy is improved and fine irregularities in the surface roughness are eliminated, and in extreme cases, the variation in thickness may reach 5 μm.

The chamfered portion etching step will be described with reference to FIGS. FIG. 2 is an explanatory view showing a state of performing the chamfered portion etching process. In the figure, 2 is a semiconductor wafer, which is a laminated body X in which a plurality of semiconductor wafers 2 are in close contact with each other and sandwiched and laminated.
The laminated body X is a fixed support wall 8 of a tightening device Y described later.
Further, the semiconductor wafers 2 are placed and clamped between the movable pressing walls 10, and the semiconductor wafers 2 are immersed in the etching liquid W in the container H in a state of being in close contact with each other. In this state, since only the chamfered portion 12 of the semiconductor wafer 2 is exposed in the etching liquid W, only the chamfered portion 12 is etched as shown by the dotted line in FIG. 3, for example. On the other hand, the portions of the semiconductor wafer 2 that are in close contact with each other do not come into contact with the etching solution W and therefore are not subjected to etching. In this way, only the chamfered portion 12 of the semiconductor wafer 2 is etched.

A known etching liquid may be used as the etching liquid for etching the chamfered portion.
As described above, for example, hydrofluoric acid (50%): nitric acid (70
%): Acetic acid mixed at a ratio of 3: 5: 3 is used. As the processing conditions, for example, immersion may be performed at 35 ° C. for about 30 seconds. Furthermore, a semiconductor wafer stack X
May be left standing in the etching solution or may be rotated in the etching solution.

As a device Y for tightening the laminated body X of a plurality of semiconductor wafers 2, as shown in FIG. 4, a lower arm 26, an upper arm 28, and a connection for connecting the base ends of the lower arm 26 and the upper arm 28. Has a side U-shaped main body 32 composed of a portion 30 and a fixed support wall 8 provided at the tip of the lower arm 26 and a tip of the upper arm 28 so as to be vertically movable and at the tip. What provided the fastener 34 which has the movable pressing wall 10 may be used. The stacked body X of the semiconductor wafers 2 is placed between the fixed support wall 8 and the movable pressing wall 10 of the tightening device Y, and the movable pressing wall 10 is attached.
Can be lowered and tightened. The fastener 34
A known means may be used as a means for vertically moving the upper arm 28 so that the upper arm 28 can be vertically moved. For example, a screw hole is formed in the upper arm 28, and a screw groove is formed in the side surface of the fastener 34 in the screw hole 28. Screw it so that it can move up and down. In this case, the movable pressing wall 10 is attached to the fastener 3
It goes without saying that the four 4 are movably mounted on each other so that they can rotate.

Reference numeral 36 is a guide plate, the tip of which is connected to the movable pressing wall 10. Also, the guide plate 3
A concave groove portion 38 slidably fitted into the connecting portion 30 of the main body portion 32 is provided at the base end portion of 6. Therefore, when the movable pressing wall 10 is moved up and down, the guide plate 36 also moves up and down along the connecting portion 30, and the movement of the movable pressing wall 10 is accurately guided in the vertical direction.

[0025]

As described above, according to the method of the present invention, surface roughness due to scratches on the end surface of the chamfered portion due to lapping abrasive grains is prevented, and when a wafer is inserted and transferred into a semiconductor container, There is no effect of generation of shavings due to contact with or rubbing against a portion, and adhesion of the chamfered portion is remarkably improved so as to prevent wafer loss due to contamination or thermal strain in the manufacturing process of the semiconductor integrated circuit.

Furthermore, the transition between the main surface around the wafer and the chamfer can be accurately controlled, and the difference that penetrates into the main surface of the wafer can be achieved.
Ordinary etching can be prevented, and a special shape of the cross section of the chamfered portion can be realized, and dimensional accuracy can be improved.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of a method for manufacturing a semiconductor wafer according to the present invention.

FIG. 2 is an explanatory view showing one embodiment of the method of the present invention.

FIG. 3 is an explanatory diagram showing a state in which a chamfered portion of a semiconductor wafer is etched.

FIG. 4 is a perspective view showing an example of a fastener used in the method of the present invention.

FIG. 5 is a flowchart showing a conventional method for manufacturing a semiconductor wafer.

[Explanation of symbols]

 2 semiconductor wafer 8 fixed support wall 10 movable pressing wall 12 chamfer X semiconductor wafer stack Y clamping device W etching solution H container

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yoshiharu Kimura, Yoshiharu Kimura, Daigo Odaira, Saigomura, Nishishirakawa-gun, Fukushima 150 Shirakawa Factory, Shin-Etsu Semiconductor Co., Ltd. Address: 596-2 Naoetsu Electronics Co., Ltd. (72) Inventor Toshio Hasegawa, Nakanojo, Nakakubiki-gun, Niigata, Japan JP, A) JP 62-134953 (JP, A)

Claims (2)

(57) [Claims] 1. A slicing step of slicing a single crystal semiconductor ingot into a thin plate by a diamond cutter or the like to obtain a wafer, and a mechanical chamfering step of mechanically removing a corner portion of a peripheral portion of the wafer obtained by this slicing. In the method of manufacturing a semiconductor wafer having
After this mechanical chamfering step, a lapping step of polishing both sides of the wafer, and then the lapping-processed wafer is immersed in an acid etching solution to acid-etch the entire surface in order to remove processing strain generated in the previous step. The whole surface acid etching step, and the chamfered portion etching step in which only the chamfered portion of the wafer subjected to the whole surface etching is again immersed in an acid etching solution to acid-etch the chamfered portion to smooth the surface of the chamfered portion Etching and chamfering One side of etched wafer or
And a polishing step of mirror-polishing both surfaces thereof. 2. A slicing step of slicing a single crystal semiconductor ingot into a thin plate by a diamond cutter or the like to obtain a wafer, and a mechanical chamfering step of mechanically removing a corner portion of a peripheral portion of the wafer obtained by this slicing. In the method of manufacturing a semiconductor wafer having
After this mechanical chamfering step, a lapping step of polishing both sides of the wafer, and then the lapping-processed wafer is immersed in an alkali etching solution to perform alkali etching on the entire surface to remove processing strain generated in the previous step. A full-surface alkali etching step, a chamfered portion etching step of dipping only the chamfered portion of the wafer subjected to the full-scale etching treatment in an acid etching solution to acid-etch the chamfered portion to smooth the surface of the chamfered portion, and this full-scale etching treatment And a polishing step of mirror-polishing one or both surfaces of the chamfered etching-treated wafer.