JP2537236B2 - Non-volatile semiconductor memory - Google Patents

Description

Description: [Object of the Invention] (Field of Industrial Application) The present invention relates to a nonvolatile semiconductor memory using a MOSFET having a floating gate structure as a memory cell.

(Prior Art) MOSF with floating gate structure such as FAMOS, SAMOS, etc.
An ultraviolet erasable non-volatile semiconductor memory using ET as a memory cell is generally well used. Such a memory is one of the most popular in the field of programmable ROM.

FIG. 17 is a circuit diagram of a memory cell array portion of a conventional memory using a memory cell having such a structure. Each memory cell 90 is composed of a MOSFET having a floating gate structure, and these memory cells 90 are arranged in a matrix. The control gates of the memory cells arranged in the horizontal direction in the figure are commonly connected to one row line 91, and the drains of the memory cells arranged in the vertical direction in the figure are one. Commonly connected to column line 92, the sources of all memory cells are connected to a ground voltage of 0V.

FIG. 18 is a pattern plan view of two memory cells when the memory cell array portion is integrated on a semiconductor wafer. A column line 92 is arranged so as to be orthogonal to the row line 91, and the column line 92 is connected via a contact portion 94 to a diffusion region 93 that serves as a common drain of a memory cell for 2 bits. Further, a floating gate 95 which is in an electrically floating state is provided below each row line 91.

Each such memory has one row line 91 and one column line 92.
Existing at the intersection by applying a high voltage to
Two memory cells are selected. In the selected memory cell, impact ionization (im
data is written by injecting the electrons generated by this into the floating gate. When electrons are injected into the floating gate, the threshold voltage of the cell rises, and the cell does not turn on even when a normal read voltage, for example, 5V is applied to the control gate. On the other hand, the threshold voltage of the cell in which electrons have not been injected is in the original low state, so that it is turned on when a voltage of 5 V is applied to the control gate. Then, the column line 92 is set to "1" by a load element (not shown) to change the potential of the column line 92 based on the ON / OFF state of the memory cell, and the column line potential is detected by a sense amplifier or the like. By doing so, the read data is determined.

On the other hand, data is erased by irradiating with ultraviolet rays. That is, when the ultraviolet rays are irradiated, electrons are emitted from the floating gate, whereby the threshold voltage of the memory cell returns to the original low state.

In the above memory, since it is necessary to apply a high voltage to the drain and control gate of one selected memory cell, each cell needs to be connected to the column line. In the conventional memory described above, as shown in FIG. 18, one contact portion is provided for the common drain of two memory cells, so that the number of contact portions increases and the capacity is increased. At that time, the occupied area of the contact portion becomes large. As a result, the conventional memory has the disadvantage that the chip size is increased and the manufacturing cost is high.

(Problems to be Solved by the Invention) As described above, in the related art, since the number of contact portions is large and the chip size is large, there is a problem that the manufacturing cost is high.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory which can be manufactured at low cost by reducing the chip size.

[Structure of the Invention] (Means and Actions for Solving Problems) The nonvolatile semiconductor memory of the present invention has two or more memory cells formed by floating-gate structure MOSFETs connected in series. It suffices to provide one contact portion for each memory cell, and thus the number of contact portions can be reduced as compared with the conventional case.

(Example) Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram for explaining the principle of the nonvolatile semiconductor memory according to the present invention. MC1 to M in the figure
C4 is a memory cell composed of a floating gate MOSFET having a floating gate and a control gate.
The memory cells MC are connected in series to form a series circuit 10. One end of the series circuit 10, that is, the memory cell MC
The drain of 1 is, for example, 1 via an enhancement-type (hereinafter, referred to as E-type) MOSFET 11 for applying a write voltage.
It is connected to the write voltage VP, which is a high voltage of 2.5V, and the other end of the series circuit 10, that is, the source of the memory cell MC4 is connected to the ground voltage of 0V. A voltage Vdata corresponding to write data is applied to the gate of the MOSFET 11, and select voltages VG1 to VG4 are applied to the control gates of the four memory cells MC1 to MC4. .

FIG. 2 is a pattern plan view when the circuit of FIG. 1 is integrated on a semiconductor wafer. The diffusion region 20 in the figure is to be the source and drain regions of the MOSFET 11 and each of the four memory cells MC1 to MC4, and 21 is the MO.
The gate of the SFET 11, 22 is a control gate of each of the memory cells MC1 to MC4, and 23 is a floating gate of each of the memory cells MC1 to MC4. A channel region is formed between the source and drain regions, and a gate insulating film (not shown) is provided between the channel region and the floating gate above it and between the floating gate and the control gate above it. There is.

In the memory having such a configuration, one end of the series circuit 10, that is, a connection point between the memory cell MC1 and the MOSFET 11 for applying the write voltage is connected to a column line (not shown) through a contact portion and used. Therefore, in the circuit shown in FIG. 1, one contact portion may be provided for four memory cells. For this reason, the number of contact portions can be reduced as compared with the conventional memory, and the area occupied by the contact portions can be reduced when increasing the capacity.

By the way, in the memory of the present invention, a plurality of memory cells are connected in series in order to reduce the number of contact portions, so that electrons generated by impact ionization are injected into the floating gate as in the conventional case, and The method of writing is not applicable. That is, the memory of the present invention employs a method of writing data by extracting electrons from the floating gate or by injecting holes into the floating gate and setting the threshold voltage of the memory cell to a negative value.

Now, consider a circuit model as shown in FIG. That is, the drain of the floating gate structure MOSFET 12 is the load circuit 13
To the voltage VD through and the source to ground voltage. In this state, the voltage VG of the control gate of MOSFET 12 is set to 0V.
In addition, when the voltage VD is set to a high voltage and a breakdown occurs in the vicinity of the drain of the MOSFET 12, electrons are emitted from the floating gate and the threshold voltage of the MOSFET 12 becomes negative.

FIG. 4 is a curve diagram showing the voltage-current characteristics of the floating gate structure MOSFET. The characteristic curve a in the figure is that before breakdown occurs, and when the control gate voltage VG does not exceed a certain value of positive polarity under this characteristic, the drain current ID
Does not flow. On the other hand, the characteristic curve b is after the breakdown occurs, and in this characteristic, the drain current ID flows even if the control gate voltage VG has a negative value.
That is, after the breakdown occurs in the circuit of FIG. 3, the MOSFET 12 has the characteristic of the curve b, and the threshold voltage changes from the positive polarity to the negative polarity. Further, even if the breakdown does not necessarily occur, for example, even if a current due to bunch-through flows, if the value of the control gate voltage VG at this time is low, the threshold voltage of the MOSFET 12 changes to the negative polarity. Furthermore, breakdown occurs even if the control gate voltage VG is set to 0 V or higher. In other words, the electric field between the drain of the MOSFET 12 and the floating gate is important, and some of the holes generated by breakdown or punch through near the drain are drawn by the electric field between the drain and the floating gate, Is injected into. It is considered that this causes the floating gate to become positively charged, thereby making the threshold voltage negative. In the memory of the present invention, it is important to lower VG, and since VG is low, holes will be injected into the floating gate.

Next, the operation of the circuit shown in FIG. 1 will be described with reference to the timing charts shown in FIGS.

The timing chart of FIG. 5 is for writing data, and in this example, the data is written in the memory cell MC3 during the period T1, and the data is written in the memory cell MC2 during the period T2. First, in the period T1, the selection voltage VG1, V
G2 and VG4 are set to a high voltage of, for example, about 12.5V, and only VG3 is set to a low voltage, for example, 0V. In this state, MOSFET 11
The voltage Vdata of the gate of is set to a high voltage. This makes M
OSFET11 is turned on and high voltage due to VP is in series circuit 1
Applied to one end of 0. Further, in the series circuit 10, since the memory cells MC1, MC2, MC4 are turned on and the memory cell MC3 is turned off, a high voltage is applied to the drain of the memory cell MC3 in the off state. At this time, the breakdown or punchthrough occurs in the memory cell MC3 by setting the values of VP and Vdata to the extent that the breakdown or punchthrough occurs near the drain of the memory cell MC3. Since the control gate voltage VG3 of the memory cell MC3 is set to 0V, holes generated by breakdown or punch through are injected into the floating gate. As a result, the threshold voltage of the memory cell MC3 changes to a negative value,
As a result, the data writing in the memory cell MC3 is performed.

In the period T2, the selection voltages VG1, VG3, and VG4 are set to 12.5V, and only VG2 is set to 0V. At this time, the voltage Vdata is kept in the high voltage setting state. As a result, breakdown or punch through occurs in the vicinity of the drain of the memory cell MC2 this time, holes generated thereby are injected into the floating gate, and data writing to the memory cell MC3 is performed.

It is generally known that the avalanche breakdown that occurs near the drain occurs at a lower drain voltage when the gate voltage is lower. Therefore, breakdown occurs when the control gate voltage is set to 0 V, and breakdown does not occur when the control gate voltage is high.

The timing chart of FIG. 6 is for reading data, and in this example, it is for sequentially reading data from the memory cell MC1. At the time of reading this data, a read voltage lower than 5V is applied to one end of the series circuit 10 by means not shown. Then, the control gate voltage VG of the non-selected memory cell is set to a high potential, for example, 5V, and the control gate voltage VG of the selected memory cell is a low potential, for example,
Set to 0V. Therefore, first, the control gate voltage VG1 of the memory cell MC1 is set to 0V, and the memory cell MC1 is selected. For example, if no data is written in this memory cell MC1 and its threshold voltage is positive,
This memory cell MC1 remains off. At this time,
No current flows in the series circuit 10.

Next, the control gate voltage VG2 of the memory cell MC2 is set to 0V, and the memory cell MC2 is selected. For example, if data is written in the memory cell MC2 and the threshold voltage thereof is negative, the memory cell MC2 is turned on. At this time, since the control gate voltages VG1, VG3, VG4 of the other memory cells MC1, MC3, MC4 are high voltages, these memory cells MC1, MC3, MC4 are all on. Therefore, in this case, a current flows through the series circuit 10.
Below, control gate voltages VG3 and V are applied in the order of memory cells MC3 and MC4.
Set G4 to 0V.

When this data is read, the selected memory cell MC
The potential of one end of the series circuit 10 changes based on the ON / OFF state of the serial circuit 10, and the read data is determined by detecting the potential change with a sense amplifier or the like.

FIG. 7 is a circuit diagram showing the basic configuration of the nonvolatile semiconductor memory according to the present invention, which has a multi-bit output configuration. In the figure, 30 _O to 30 _M are memory blocks for reading 1-bit data. Each memory block 30 is configured similarly to the memory block 30 _O. That is, in each memory block 30, a series circuit 10 is formed by serially connecting n memory cells MC1, MC2 ... MCn having a floating gate structure having a control gate and a floating gate.
Are arranged in rows and columns. One end of each series circuit 10 is connected to a corresponding one of the plurality of column lines C1, C2 ... Cp via an E-type MOSFET 31 for selecting a series circuit.
The gate of the MOSFET 31 connected to each series circuit 10 is
Row lines W1, W2, ... To which the decode output from the row decoder 41 provided in common to all the memory blocks 30 is applied.
, And the control gates of the memory cells MC1 to MCn in each series circuit 10 are respectively connected to W11, W12 ... W1n, W21, W22, ... W2n, ... To which the tecode output from the row decoder 41 is applied. . Each column line C is a column selection line E to which a column output line CS1, CS2, ..., CSp to which a decode output from a column decoder 42 provided in common to all memory blocks 30 is applied is connected to a gate. The data write / read node 33 is commonly connected through each of the MOSFETs 32 of the type.

The node 33 is connected to the application point of the write voltage VP via the E-type N-channel MOSFET 34 for applying the write voltage, which corresponds to the MOSFET 11 in FIG. This MOSFET 34
The output end of the data input circuit 35 is connected to the gate of the. The data input circuit 35 outputs the voltage Vdata based on the write data. Further, the node 33 is connected to a data detection node 37 via an E-type N-channel MOSFET 36 for potential separation in which a predetermined bias voltage Vdias is applied to the gate. The data detection node 37 is connected to the drain and gate of an E-type P-channel MOSFET 38 for load, and the source of the FET 38 is connected to the power supply voltage VC at the time of reading. A sense amplifier 39 is connected to the data detection node 37, and the read data determined here is output via an output buffer 40.

In the memory having such a configuration, every n memory cells are
Since it is sufficient to connect the MOSFET 31 to the column line C, the number of contact portions required when connecting the memory cell to the column line is significantly reduced. Therefore, the area occupied by the contact portion is reduced, and the chip size when increasing the capacity can be significantly reduced, which makes it possible to reduce the manufacturing cost.

 Next, the operation of the memory will be described.

FIG. 8 is a timing chart showing an example of an operation when writing data in the memory. In this example, one series circuit 10 connected to the row lines W1, W11 to W1n and the column line C1 is selected and data is written to the memory cells in the series circuit 10. At this time, the decode output of the column decoder 42 sets only one column selection line CS1 to a high voltage, and the column selection MOSFET 32 connected to the column line C1 is turned on. At this time, the other column selection line CS2
~ CSp are all set to low voltage, and the remaining column selecting MOSFETs 32 connected to the column lines C2 to Cp are turned off. Further, by the decode output of the row decoder 41, only one row line W1 of the row lines W1, W2, ... Is set to a high voltage and is connected to the series circuit 10 arranged in the same row. For selection
MOSFET 31 turns on. In this state, only the row line W11 is set to a low voltage by the decode output of the row decoder 41. At this time, it is assumed that the data input circuit 35 sets the output voltage Vdata to a high voltage. This turns on MOSFET 34, and a high voltage write voltage VP is applied to node 33. Further, the high voltage output to the node 33 is applied to the column line C1 via the column selecting MOSFET 32 which is turned on. As a result, the breakdown as described above occurs near the drain of the memory cell MC1 in the selected series circuit 10, and holes are injected into the floating gate to write data.

After this, the row line W12 is output by the decode output of the row decoder 41.
Only set to low voltage. At this time, the data input circuit
If the output voltage Vdata of 35 is set to low voltage, the row line W
No holes are injected into the floating gate of the memory cell MC2 connected to 12. Thus, the control gate voltage is set to a low voltage also for the memory cell in which holes are not injected. The reason is that the row line W is common to all the memory blocks 30, and holes need to be injected into the floating gates of the corresponding memory cells in other memory blocks.

Thereafter, similarly, the row line W1n is sequentially set to a low voltage, and the voltage Vdata is set to a voltage corresponding to the write data, so that the data writing to the n memory cells in the selected series circuit 10 can be performed. Done.

At this time, in order to prevent breakdown from occurring in the series circuit of other unselected rows, the impurity concentration in the drain region of each MOSFET 31 should be reduced to start the avalanche breakdown due to the electric field between the gate and drain. The voltage value needs to be higher than that of the memory cell.

FIG. 9 is a timing chart showing another example of the voltage waveforms of the row lines W11 to W1n at the time of writing data. 8th
In the timing chart of the figure, the row line is normally set to a high voltage and set to a low voltage for a predetermined period only when writing data, but in this example, the row line is set from W1n to W
Memory cells are set by sequentially setting the voltage to 11
The holes are sequentially injected from MCn to MC1.

Further, in the operation shown in the timing chart of FIG.
The row line is normally set to a high voltage, for example, 12.5V, and set to a low voltage, for example, 0V for a predetermined period only when writing data, but as shown in the timing chart of FIG. By setting the voltage lower than the voltage of each row line, which is 12.5V, for example, 5V during a period in which no memory cell is selected, the voltage stress on the memory cell can be reduced.

Data can be read out from the memory shown in FIG.
The one to which the selected memory cell is connected among 1, W2, ... Is set to a high voltage, for example, 5V. And row line W1
Of W1, W12, W13, ... W1n, W21, W22, W23, ... W2n, only those to which the selected memory cell is connected are set to the low voltage. All the remaining row lines are set to a high voltage, and the memory cells connected to these are turned on. At this time,
The selected cell connected to the low-voltage row line is turned on or off depending on its threshold voltage. Depending on the operating state of this selected cell, node 37 will remain charged or discharged by MOSFET 38. Then, a change in the potential of this node is detected by the sense amplifier 39, and is output as read data via the output buffer 40.

FIG. 11 is a circuit diagram showing the structure of a memory according to an embodiment of the present invention. In the memory having the basic configuration shown in FIG. 7, the other end of each series circuit 10, that is, the memory cell
The source of MCn is connected to ground voltage. However,
In the memory of this embodiment, the other end of each series circuit 10 is connected to the ground voltage via the MOSFET 51 whose gate is connected to the signal line which is set to a low voltage when writing data. With such a configuration, a through current that flows through the series circuit 10 at the time of writing data is not generated, it is possible to prevent a decrease in the drain voltage of the cell that causes a breakdown in the vicinity of its drain, and efficiently transfer holes to the floating gate. Can be injected. In addition, this MOSFET51
May be provided for each series circuit 10, respectively,
It can also be provided in common for a plurality of series circuits 10.

FIG. 12 shows one row line of the row decoder 41 shown in FIG.
FIG. 6 is a circuit diagram showing a specific configuration of a decoder unit that sets the voltage of W1. In this example, row address signals A0 to A5
6 bits are input, four serial circuits 10 are provided for each column line C, and each serial circuit 10 is composed of 16 memory cells.

Addresses A4 and A5 are input to the decoder section for setting the voltage of the row line W1. When both addresses are "1", the N-channel MOSFETs 61 and 62 are turned on and are always turned on. Voltage via P-channel MOSFET 63
The node 64 connected to VC becomes "0". As a result, the P-channel MOSFET to which the signal of the node 64 is input
The signal at the output node 68 of the inverter 67 including the 65 and the N-channel MOSFET 66 becomes "1".

When writing data, the signal line is set to 0V and the signal H is set to a high voltage. N channel when signal H is raised to high voltage
MOSFET 69 and depletion type (hereinafter referred to as D type)
The row line W1 is charged with the high voltage VP through the N-channel MOSFET 70. At this time, since the gate of the D-type N-channel MOSFET 71 connected between the node 68 and the row line W1 is set to 0V, no current due to the high voltage VP flows from the row line W1 to the node 68 side. .

When reading data, the signal line is set to 5V, for example.
At this time, since the high voltage VP is not supplied, the signal "1" of the output node 68 of the inverter 67 is output to the row line W1 as it is.

In another decoder section (not shown) for setting the voltages of the other row lines W2, W3, W4, the gates of the N-channel MOSFETs 61, 62 have addresses ▲ ▼ and A5, A4 and ▲ ▼, ▲ ▼ and ▲.
Each combination of ▼ has been entered. Then, when both address signal inputs become "1", a high voltage or a "1" level signal is output from the corresponding row line.

FIG. 13 shows one row line of the row decoder 41 shown in FIG.
FIG. 11 is a circuit diagram showing a specific configuration of a decoder unit that sets the voltage of W11. This decoder section has addresses A0, A1, A
When 2, A3 are input and all addresses are "1", N-channel MOSFETs 71, 72, 73, 74 are turned on, and connected to voltage VC via P-channel MOSFET 75 which is always on. The node 76 that has been set becomes “0”. As a result, the P-channel MOSFET to which the signal of the node 76 is input
The signal at the output node 80 of the inverter 79 composed of 77 and the N-channel MOSFET 78 is "1", the output node of the inverter 79.
The signal of the output node 84 of the inverter 83 including the P-channel MOSFET 81 and the N-channel MOSFET 82 to which the signal of 80 is input becomes "0".

When writing data, the signal line is set to 0V and the signal H is set to a high voltage. N channel when signal H is raised to high voltage
Row line W11 through MOSFET 85 and D-type N-channel MOSFET 86
Is charged with high voltage VP. At this time, since the signal of the output node 84 of the inverter 83 is "0", a current flows from the row line W11 to the node 84 side through the D-type N-channel MOSFET 87, and the row line W11 becomes a low voltage, that is, 0V. Is set. On the other hand, when any of the addresses A0, A1, A2, A3 is "0", the signal of the output node 84 of the inverter 83 becomes "1", and the row line
W11 is charged with high voltage VP. That is, when writing the data, when the row line W11 is selected, it is 0 V, and when it is not selected, it is a high voltage.

When reading data, the signal line is set to 5V, for example.
At this time, since the high voltage VP is not supplied, the signal of the output node 84 of the inverter 83 is directly output to the row line W11.

In another decoder section (not shown) for setting the voltages of the other row lines W12 to W110 to W116 (where n is 16), the N channel MO is set.
Different combinations of addresses A0 to A3 are input to the gates of SFETs 71, 72, 73, 74. And when writing data,
When all the address signals become "1", 0V voltage is output from the corresponding row line.

The circuit shown in FIG. 13 is an N-channel MOSF surrounded by a broken line.
ET78A, 78B and P-channel MOSFETs 81A, 81B may be provided. By providing these FETs, both the addresses A4 and A5 become "1" and W11 becomes "1", depending on the logic level of A0 to A3, only when one row line W1 becomes "1".
Outputs "0". When the row line W1 is not selected, that is, when W1 is "0", W11 is always "0", and the row line can be "0" when the series-connected memory cell group is not selected. preferable. But FET
These FETs can be omitted if one does not like to increase the number of.

By the way, in the circuit shown in FIG. 13, when the row line W11 is selected at the time of writing data, the voltage is set to 0V. When writing data by breaking down, 0V is acceptable, but when punching through, it is better to set this voltage to about 1V. In this case, as shown in FIG. 14, a bias circuit 88 is inserted between the N-channel MOSFET 82 of the inverter 83 in FIG. 13 and the ground voltage, and the source voltage of the N-channel MOSFET 82 is written. The threshold voltage of a memory cell that does not exist, for example, may be set to about 1V. As the bias circuit 88, an N-channel MOSFET having its gate and drain connected can be used as shown in the figure.

Also, by using this circuit in FIG. 14, the current of the cell that is turned on during data reading increases,
The read margin can be widened.

FIG. 15 is a diagram collectively showing the truth value states of the row decoder 41 which outputs the voltage waveform as shown in FIG. Here, the program signal P is a signal which is set to "0" at the time of reading out data, but the waveform of FIG. 8 has 16 row lines W11 to W regardless of the signal P and changes in the addresses A0 to A3.
One of 116 is set to "0". Row data 4
1 may be configured to satisfy such a truth value state.

FIG. 16 is a diagram collectively showing a truth value state of the row data 41 which outputs the voltage waveform as shown in FIG. 9 at the time of writing data. As address signals A0 to A3 change
16 row lines W11 to W116 are sequentially "0" from W116 to W11
Is set to That is, in the memory cell block including a plurality of memory cells connected in series, the data is written from the memory cell on the side opposite to the MOSFET 31 side among the memory cells connected in series, so that the writing is already performed. A high voltage is not applied thereafter to the memory cells in the same memory cell block, and the effect that the reliability with respect to the memory cell for which writing has been completed can be improved is obtained. The row decoder 41
Need only be configured to satisfy such a truth value state. When the row decoder 41 having the structure shown in FIG. 13 is used, a row line connected to the selection transistor 31 is provided so that unnecessary voltage is not applied to the memory cell and the reliability is not impaired. Address A to select W1
Logic is applied to both 4 and A5, and when the select transistor 31 in the memory cell block is non-conductive, this select transistor 31
The control gate of the memory cell connected to is always 0V
Therefore, it is possible to further improve the reliability when writing data or the reliability when reading data. At this time, read / write is distinguished by the signal P, and when the signal P is “0”, the
It is configured to satisfy the truth value state shown in Fig. 15.

[Effect of the Invention] As described above, according to the present invention, it is possible to provide a nonvolatile semiconductor memory that can be manufactured at low cost by reducing the chip size.

[Brief description of drawings]

FIG. 1 is a circuit diagram for explaining the principle of the nonvolatile semiconductor memory according to the present invention, FIG. 2 is a pattern plan view of the circuit of FIG. 1, and FIG. 3 is used for explaining the circuit of FIG. FIG. 4 is a diagram showing a circuit model, FIG. 4 is a curve diagram showing voltage-current characteristics of a floating gate structure MOSFET, FIGS. 5 and 6 are timing charts for explaining the operation of the circuit shown in FIG. 1, and FIG. FIG. 11 is a circuit diagram showing a basic configuration of a nonvolatile semiconductor memory according to the present invention, FIGS. 8, 9, and 10 are timing charts for explaining the operation of the memory of the above embodiment, and FIG. Is a circuit diagram showing a structure of a memory according to an embodiment of the present invention, FIGS. 12 and 13 are circuit diagrams showing a concrete structure of a row decoder in the circuit shown in FIG. 7, and FIG. FIG. 13 is a circuit diagram showing the configuration of a modified example of the circuit, FIGS. 15 and 16 are FIG. 17 is a diagram showing a truth value state of a row decoder in the circuit of FIG. 7, FIG. 17 is a circuit diagram of a memory cell array portion of a conventional memory, and FIG. 18 is a pattern plan view of the conventional memory. 10 …… Series circuit, 11,34 …… MOSFE for applying write voltage
T, 30 ... Memory block, 31 ... MOS for selecting series circuit
FET, 32 ... MOSFET for column selection, 33 ... Writing data /
Read node, 35 ... Data input circuit, 39 ... Sense amplifier, 40 ... Output buffer, 41 ... Row decoder, 42 ...
... Column decoder, MC ... Memory cell, W ... Row line, C ...
Column line, CS ... Column selection line.

Claims (2)

(57) [Claims] 1. A first selection transistor having one end connected to a first terminal, a control gate, a floating gate, a drain, a source, a channel region, and a gate between the channel region and the floating gate. A plurality of memory cells having an insulating film and connected in series between the other end of the first selection transistor and the second terminal, and connected between the second terminal and the reference potential. The second selection transistor is made conductive when reading data and made non-conductive when writing data, and a data writing operation to each memory cell is performed between the floating gate and the channel region and the floating gate. The memory cell block is formed by emitting electrons through a gate insulating film, and the first selection transistor is connected to the first selection transistor. A first row line for selecting a memory cell, connected to the memory cell, a second row line for selecting the memory cell, a first row line connected to the first row line, and the first selection line Row decoder for outputting a signal for selecting a transistor for writing, a second row decoder connected to the second row line for outputting a signal for selecting the memory cell, and writing of data And a write voltage applying means for applying a predetermined voltage to the memory cell, wherein the second row decoder applies a voltage according to write data to the selected memory cell. When writing is performed by applying to the memory cell through the memory cell, the writing is performed on the side opposite to the memory cell connected to the first selecting transistor among the plurality of memory cells. Note that the signal is output to the second row line so as to be sequentially performed from the memory cell on the side of the second terminal toward the memory cell on the side of the first selecting transistor. Semiconductor memory. 2. A first selection transistor having one end connected to a first terminal, a control gate, a floating gate, a drain, a source, a channel region, and a gate between the channel region and the floating gate. A plurality of memory cells having an insulating film and connected in series between the other end of the first selection transistor and the second terminal, and connected between the second terminal and the reference potential. The second selection transistor is made conductive when reading data and made non-conductive when writing data, and a data writing operation to each memory cell is performed between the floating gate and the channel region and the floating gate. The memory cell block is formed by emitting electrons through a gate insulating film, and the first selection transistor is connected to the first selection transistor. A first row line for selecting a memory cell, connected to the memory cell, a second row line for selecting the memory cell, a first row line connected to the first row line, and the first selection line A first row decoder for outputting a signal for selecting a transistor for use, and a signal of a first logic level connected to the second row line and for selecting the memory cell on the second row line. Alternatively, a second row decoder for supplying a signal of a second logic level whose potential is set higher than the signal of the first logic level, and the memory cell connected to the first terminal and writing data Write voltage applying means for applying a predetermined voltage to the second row decoder, wherein the second row decoder includes the unselected first selection transistor in which the first selection transistor is unselected. Memory cell block When the selection is,
A nonvolatile semiconductor memory, wherein a second row line connected to the non-selected memory cell block is set to the signal of the first logic level.