JP2535676B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a capacitor used in a one-transistor / one-capacitor dynamic random access memory (dynamic RAM).

[0002]

2. Description of the Related Art A dynamic RAM composed of a one-transistor, one-capacitor type memory cell is rapidly being highly integrated and has a large capacity due to the progress of semiconductor technology, especially the fine processing technology. 1M bits and 4M bits have already been mass-produced, and 64M bits are currently under development. As the high integration progresses in this way, conventional manufacturing techniques cannot meet the demand, and new fine processing techniques are required. Hitherto, as a memory cell for increasing the storage capacity, a stacked capacitance type cell (Stacked Capacitor Cell) in which a part of the storage capacity is stacked on a MOS transistor and an element isolation region is known.
In this storage capacity, as a method of increasing the capacity, there is a cell having a cylindrical storage node. Below, FIG.
8 and FIG. 8, a method of manufacturing a stacked capacitor cell having a conventional cylindrical storage node will be described.

First, a P-type Si semiconductor substrate 1 is thermally oxidized to form, for example, an oxide film 2 serving as a device isolation region of 4000 Å (hereinafter referred to as A), and then thermal oxidation is performed on the device region. Thus, a gate oxide film 3 of about 100 A, for example, is formed, and then a conductor film to be a gate electrode, for example, a polycrystalline Si film 4 doped with phosphorus is deposited. Next, after depositing a CVD SiO ₂ film 5 of, for example, about 1000 A, CVD SiO ₂ is used as a mask with a photoresist.
By patterning the ₂ film 5 and the polycrystalline Si film 4, and implanting, for example, about 1 × 10 ¹⁵ cm ^-2 by ion implantation, the N-type diffusion layer 6 of the source and drain of the MOS transistor connected to the storage node of the capacitor is formed. To do. Next, after removing the photoresist, for example, CVDSiO
₂ film 7 is deposited, for example, about 1000A, CVD SiO ₂ film 7, for example, RIE so that only remains on the side wall of the CVD SiO ₂ film 5 is patterned earlier polycrystalline Si film 4
To etch back (FIG. 7 (a)).

Next, the Si ₃ N ₄ film 201 is formed on the entire surface of the semiconductor substrate.
Is further deposited, and the Si ₃ N ₄ film 201 at a predetermined position of the element region surrounded by the gate electrode 4 of the MOS transistor is peeled off to form the storage node contact 12 ( FIG. 7B). Then, a pad polycrystal Si film 13 which is a first conductor film serving as a lower electrode of the capacitor is deposited and patterned using a resist 202 so as to remain in an island shape at a predetermined position (FIG. 7). (C)). Next, a CVD SiO ₂ film 14 is deposited, a hole is formed so as to contact the island-shaped remaining polycrystalline Si film 13 for pad, and then a second conductor to be a lower electrode of the capacitor is formed on the entire surface of the substrate. A polycrystalline Si film 16 which is a film is deposited (FIG. 8A). Next, etching is performed so that the polycrystalline Si film 16 remains only on the side wall of the hole, and then the CVD SiO ₂ film 14 is removed by etching (FIG. 8).
(B)). Next, the dielectric film 17 of the capacitor is formed on the entire surface of the substrate.
Is deposited, a polycrystalline Si film 18 which is a third conductor film serving as a plate electrode of the capacitor is deposited on the dielectric film 17, and further patterned to form a capacitor (FIG. 8C). .

[0005]

In the method of manufacturing a capacitor described above, the pad-like polycrystalline Si film 13 is formed in an island shape, and holes must be formed so as to be in contact with the Si film 13. It is necessary to align the holes with the Si film 13. In addition, since the polycrystalline Si film 13 is formed first, it is not allowed that the holes are larger than the polycrystalline Si film 13, so that it is necessary to sufficiently control the hole diameter. That is, in this manufacturing method, it is important to align the holes in the polycrystalline Si film 13 and control the hole diameter. In addition, this manufacturing method has a problem in that the patterning using the photo-etching method is required twice to form the lower electrode of the capacitor, resulting in an increase in the number of steps.

The present invention has been made in view of the above circumstances, and an object thereof is to reduce a memory cell area,
It is an object of the present invention to provide a method for manufacturing a semiconductor device that enables high-density integration.

[0007]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention comprises a step of forming an element isolation region in a semiconductor substrate and a MOS transistor in the element region within the element isolation region. A step of forming a first insulating film on the entire surface of the semiconductor substrate, a step of forming a first insulating film on the element isolation region, and a step of forming a first insulating film on the first insulating film of the element region surrounded by the gate electrode of the MOS transistor. A step of forming a first contact hole, a step of forming a first conductor film on the first insulating film and in the first contact hole, and a step of forming a second conductor film on the first conductor film. Forming an insulating film, forming a resist having a predetermined pattern on the second insulating film, and forming a second contact hole in the second insulating film using the resist as a mask. And this part of the above Exposing the first conductor formed on the first contact hole; and isotropically etching the second insulating film from the second contact hole using the resist as a mask. The step of enlarging the diameter of the contact hole, the step of forming a second conductor film on the second insulating film so as to cover the inner wall of the second contact hole, and except the inside of the second contact hole. The second
Removing the second conductor film formed on the surface of the insulating film, removing the second insulating film to partially expose the first conductor film, and the first Removing the exposed portion of the conductor film of
And a step of forming a dielectric film so as to cover the second conductive film, and a step of forming a third conductive film on the dielectric film.

In the step of removing the exposed portion of the first conductor film, the first conductor film may be selectively removed by etching using the second conductor film as a mask. it can. The dielectric film is SiO
₂ film, Ta ₂ O ₅ film, SiO ₂ / Si ₃ N ₄ film, SiO
It can be selected from a ₂ / Si ₃ N ₄ / SiO ₂ film and a lead titanate / lead zirconate ferroelectric film. The first conductive film and the second conductive film on the semiconductor substrate covered with the dielectric film form a cylindrical storage node. The area of one memory cell formed on the semiconductor substrate is 1 μm ×
In the case of 1.5 to 1.6 μm, the cylindrical storage node has a major axis of 1.0 to 1.4 μm and a minor axis of 0.3 to
It can be 0.6 μm.

When a SiO ₂ film or a SiO ₂ / Si ₃ N ₄ film is used as the dielectric film, the height of the cylindrical portion of the storage node can be 0.5 to 1.0 μm. , Ta ₂ O ₅ film or lead titanate / zirconate lead ferroelectric film, the height of the cylindrical portion of the storage node can be 0.5 μm or less. The second
When the second contact hole is formed in the second insulating film, the first conductor film is used as an etching stopper when the second insulating film is etched. Furthermore, in the MOS transistor, it is possible to use a so-called LDD structure in which a low concentration region is formed in the impurity diffusion layer.

[0010]

In processing a first conductor film, for example, a polycrystalline Si film for a pad, the cylindrical Si body of the accumulation node is used as a mask, so that this polycrystalline Si film is used as the accumulation node. Since it can be formed by self-alignment with respect to the guide, it is not necessary to have a margin for alignment as in the conventional case.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 is a sectional view of a memory cell for explaining the present invention, and FIGS. 2 to 5 are sectional views showing manufacturing steps thereof. First, LO is formed on a predetermined region of the P-type Si semiconductor substrate 1.
An oxide film 2 to be a device isolation region of, for example, 4000 A is formed by using the COS method, and then a gate oxide film 3 of 100 A, for example, is formed on the device region surrounded by the device isolation region by thermal oxidation. A conductor film serving as a gate electrode, for example, a polycrystalline Si film 4 doped with phosphorus is deposited. Next, after depositing a CVD SiO ₂ film 5 of, for example, 1000 A, the CVD SiO ₂ film 5 and the polycrystalline Si film 4 are patterned using a photoresist as a mask to form a gate electrode 4. The gate electrode 4 is covered with an insulating film 5 made of CVDSiO ₂ and used as a word line.
Then, for example, 1 × 10 arsenic ions are implanted by ion implantation.
¹⁵ cm ^- by implanting ² mm, to form the source of the MOS transistor connected to the storage node of the capacitor, the N-type diffusion layer 6 which is the drain region. Then, after removing the photoresist, an insulating film 7 made of CVDSiO _{2 is} deposited to a thickness of 1000 A, for example. Then, the CVD SiO ₂ film 7 is made of, for example, R so that it remains only on the sidewalls of the previously patterned CVD SiO ₂ film 5 and the polycrystalline Si film 4.
Etch back by IE (FIG. 2 (a)).

Next, the Si ₃ N ₄ film 8 to be the first insulating film is formed.
Is 500 A, and the CVD SiO ₂ film 9 is 150, for example.
00A, Si ₃ N ₄ film 10 is deposited to 500 A, for example.
As described above, the first insulating film is a three-layer composite film, but may be, for example, a two-layer structure in which the above films are appropriately combined. For example, as in the above-described conventional example, Si ₃ N is used.
_A single-layer insulating film such as _four films may be used (FIG. 2 (b)). Next, the first insulating film is coated with the photoresist 11 and further patterned, and the first contact hole is formed in order to form the contact 12 of the storage node of the capacitor at a predetermined position by using this as a mask. 121 is formed (FIG. 3)
(A)). Next, after the photoresist 11 is peeled off, a first conductor film, for example, a polycrystalline Si film 13 doped with phosphorus, which serves as a storage node of the capacitor, is formed at 200A to 50A.
About 0 A, for example, 500 A is deposited, and then a second insulating film, for example, a CVD SiO ₂ film 14 is deposited from 4000 A to
About 10000A, for example about 4000A is deposited (Fig. 3
(B)). Next, using a photoresist (not shown) as a mask, etching is performed by, for example, RIE to form a second
Of the second contact hole 122 at a predetermined position of the insulating film 14 of
To form. At the time of this etching, the polycrystalline Si film 13, which is the first conductor film, is hard to be etched, so that it functions as a kind of etching stopper, and the insulating film 7 below it is used.
Etc. are prevented from being etched (Fig. 4
(A)).

Next, the second node which becomes the storage node of the capacitor.
Of the conductor film, for example, a polycrystalline Si film 16 doped with phosphorus is deposited to about 500 A to 1000 A, for example, 1000 A, and then the resist 20 is provided only in the second contact hole.
Are formed (FIG. 4B). Next, using the resist 20 as a mask, the second conductor film 16 in the uncovered plane portion is used.
Are removed by, for example, reactive ion etching (FIG. 5).
(A)). Next, the CVD-SiO ₂ film 14 is removed by, for example, wet etching, and then the semiconductor substrate 1, that is, the entire surface of the wafer is etched back by anisotropic etching such as reactive ion etching, and then the resist 20 is removed. Remove. At this time, the first conductor film 13
The portion of the polycrystalline Si film that is not covered by the polycrystalline Si film that is the second conductor film 16 is also removed by etching, but since the second conductor film 16 is etched as a mask, The exposed portion of the first conductor film 13 does not remain. Then, the remaining first and second conductor films 13 and 16 form an accumulation node (FIG. 5).
(B)). Next, the polycrystalline Si film 1 which is the storage node
An oxide film (SiO ₂ ) 17 to be a dielectric film of a capacitor of about 50 A is formed on the layers 3 and 16 by thermal oxidation,
Subsequently, a third conductor film which will be a plate electrode of the capacitor, for example, a polycrystalline Si film 18 doped with phosphorus, for example, 2000 A is deposited to form a memory cell (FIG. 1). This cell is composed of a MOS transistor and a capacitor. The storage node of this capacitor is composed of the first and second conductor films 13 and 16, but the outer wall of the storage node is flat, and the protruding portion of the first conductor film 13 is formed. Is not formed, the cell area does not unnecessarily expand.

FIG. 6 is a sectional view of the semiconductor device according to the first embodiment of the present invention. This embodiment is characterized in that the tubular body can be controlled to have an appropriate size. After forming the first contact hole 121, a CVD-SiO ₂ film that is the second insulating film 14 including the contact hole is formed on the Si substrate 1, and the photoresist 15 is formed by RIE.
The second contact hole 122 at a predetermined position using the mask as a mask.
It is the same as the previous embodiment until the formation of. In the previous embodiment, after forming the second contact hole, the resist 15 is
Although it is removed as it is, the resist is not removed after the second contact hole is formed, and isotropic etching is performed (FIG. 6).
(A)). As shown in the drawing, as the etching is continued, the second insulating film 14 on the side wall of the second contact hole recedes under the resist 15. As a result, the diameter of the contact hole becomes wider. The resist is removed after expanding the hole diameter, and a second conductor film such as polysilicon is formed on the inner wall of the contact hole and the second insulating film 14, and the second conductor on the insulating film is etched back. Remove the membrane, then the second
The insulating film is removed by etching to expose the first conductor film. Further, the second conductor film 16 on the first conductor film 13
With the mask as a mask, the exposed portion of the polysilicon that is the first conductor film 13 is removed to remove the polysilicon film 1
A storage node consisting of 3 and the polysilicon film 16 is formed (FIG. 6B). In this sectional view,
Although the cylinder of C shows the longer hole diameter portion, its size R has a larger hole diameter than the cylindrical portion of the previous embodiment. Then, on the surface of the storage node, a silicon oxide film by thermal oxidation of about 50 A which becomes the dielectric of the capacitor and a third conductive film of phosphorus which becomes the plate electrode of the capacitor are doped with poly. A memory cell is formed by depositing a silicon film. Normally, the distance between the cylinders is determined by the limit of lithography, but in this way, the distance between the cylinders can be reduced to use a larger cylinder.

Next, a second embodiment will be described. The memory cell is similar to that shown in FIG. 1 in that a capacitor provided with a dielectric film 17 and a plate electrode 18 formed on the storage node and an M capacitor.
It has an OS transistor. The MOS transistor has a pair of N-type impurity diffusion layers 6 serving as a source and a drain formed on a P-type silicon semiconductor substrate 1 and a gate electrode 4 formed via a thin gate oxide film 3. Prepare The impurity diffusion layer 6 is an LDD composed of a relatively high concentration impurity diffusion region and a relatively low concentration impurity diffusion region.
Although it is different from the memory cell of FIG. 1 in that it has a (Lightly Doped Dorain) structure, the present invention is also applicable to a semiconductor device having such a structure.

In these embodiments, the element area of the memory cell is 1 .mu.m.times.1.5 to 1.6 .mu.m corresponding to high integration, and the size of the storage node at this time is 1 to 1
The diameter was 1.4 μm and the minor axis was 0.3 to 0.6 μm. Comparing the memory cell in this embodiment with the memory cell having the protruding portion of the first conductor film outside the storage node in the conventional example, the element area is reduced by about 35%. I understand. Further, in the present invention, the height of the cylindrical portion of the accumulation node can be set to 0.5 to 1 μm.
In the example, it was 0.5 μm. The capacitance of the capacitor is
Normally, it depends on the dielectric constant of the dielectric film and its thickness, but if a dielectric with a large unit capacitance is selected, the height of this cylindrical body is the size that occupies the space from the viewpoint of strength. From the viewpoint of, it is desirable that the value be low. In the embodiment, a SiO ₂ film of about 50 A formed by thermal oxidation is used. However, for example, when a Ta ₂ O ₅ film is used as a dielectric, the dielectric constant of this film is large, so that a cylindrical body is used. Can be approximately half or less, that is, 0.5 μm or less. The lower this height is, the stronger the tubular body is, so
The thickness of the tubular body, that is, the second conductor film can be thinned. Since the area occupied by such a thin structure becomes small, the element itself can be made small. The second conductor film has a thickness of about 0.1 μm in the embodiment, but is less than 5 μm.
It is possible to reduce the thickness to about 00 A, and by using another dielectric, it is possible to further reduce the thickness of the conductive film and to help reduce the element area. In the embodiment, the first conductor film 13 made of a polycrystalline Si film doped with phosphorus is formed, and then the second insulating film 14 made of a CVDSiO ₂ film is formed, and then this insulating film 14 is formed. By etching away the second
The contact hole 122 is formed to expose the first conductor film 14 in the contact hole. Polycrystalline Si and CVDS
Since the etching rate ratio of iO ₂ is approximately 1/8 to 1/10, this polycrystalline Si film is used as an etching stopper.
It also has a function as. The first conductor film is not limited to polycrystalline Si. As the electrode, of course, any conductive material can be used as long as it can function as the etching stopper.

In this embodiment, the thermal oxide film is used as the dielectric film of the capacitor, but instead of the SiO ₂ film 17, Si film is used.
It is represented by a dielectric film such as a ₃ N ₄ film and a Ta ₂ O ₅ film, a ferroelectric film such as a lead titanate / zirconate film, or a three-layer film composed of an oxide film, a nitride film and an oxide film. You may use a complex composite film. For the Ta ₂ O ₅ film, a CVD method or a sputtering method is used, and for the titanate / lead zirconate film, a sputtering method or the like is used. Further, in the above-mentioned embodiment, as shown in FIG. 2B, the Si ₃ N ₄ film 8, the CVDSiO ₂ film 9 and the Si ₃ N ₄ film 10 are deposited and formed as the interlayer insulating film. The Si ₃ N ₄ film may be formed by depositing about 2000 A, for example. Also, N
It is also possible to apply a type Si semiconductor substrate.

[0019]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the first conductor film is etched by using the second conductor film forming the storage node as a mask. Since it is not necessary to form an extra alignment margin in the first conductor film, and a larger cylinder can be used by narrowing the space between the cylinders, it is possible to secure a semiconductor device with highly integrated memory cells. Can be formed.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a semiconductor device illustrating the present invention.

FIG. 2 is a cross-sectional view of the manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view of the manufacturing process of the semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view of the manufacturing process of the semiconductor device shown in FIG.

5A to 5D are cross-sectional views of a manufacturing process of the semiconductor device shown in FIG.

FIG. 6 is a cross-sectional view of the manufacturing process of the semiconductor device according to the invention.

FIG. 7 is a cross-sectional view of a manufacturing process of a conventional semiconductor device.

FIG. 8 is a cross-sectional view of a conventional semiconductor device manufacturing process.

[Explanation of symbols]

1 P-type Si semiconductor substrate 2 Element isolation insulating film 3 Gate oxide film 4 Gate electrode 5 Oxide film 6 N-type diffusion layer 7 Oxide film 8 First insulating film (Si ₃ N ₄ film) 9 First insulating film (SiO ₂ film) 10 first insulating film (Si ₃ N ₄ film) 11 photoresist 12 storage node contact 121 first contact hole 122 second contact hole 13 first conductor film 14 second insulating film (CVDSiO) ₂ film) 15 photoresist 16 second conductor film 17 dielectric film 18 third conductor film (plate electrode) 20 photoresist 201 Si ₃ N ₄ film 202 photoresist

Claims (9)

(57) [Claims] 1. A step of forming an element isolation region in a semiconductor substrate, a step of forming a MOS transistor in an element region in the element isolation region, and a step of forming a first insulating film on the entire surface of the semiconductor substrate. A first insulating film is formed in the element region surrounded by the element isolation region and the gate electrode of the MOS transistor.
Forming a contact hole, forming a first conductor film on the first insulating film and in the first contact hole, and forming a second conductor film on the first conductor film. Forming an insulating film; forming a resist having a predetermined pattern on the second insulating film; and forming a second contact hole in the second insulating film using the resist as a mask. Exposing the first conductor formed in the first contact hole in this portion, and isotropically etching the second insulating film from the second contact hole using the resist as a mask. And a step of expanding the diameter of the second contact hole, forming a second conductor film on the second insulating film so as to cover the inner wall of the second contact hole, and the second contact. The surface of the second insulating film except in the holes Removing the second conductive film formed on the surface, removing the second insulating film to partially expose the first conductive film, and the first conductive film A step of removing the exposed portion of the body film, a step of forming a dielectric film so as to cover the first and second conductor films, and a third conductor on the dielectric film. A method of manufacturing a semiconductor device, comprising the step of forming a film. 2. In the step of removing the exposed portion of the first conductor film, the first conductor film is selectively removed by etching using the second conductor film as a mask. The method for manufacturing a semiconductor device according to claim 1, further comprising: 3. The dielectric film is a SiO ₂ film, Ta ₂ O
₅ film, SiO ₂ / Smi ₃ N ₄ film, SiO ₂ / Si ₃ N
_{2. The} method for manufacturing a semiconductor device according to claim 1, wherein the ₄ / SiO ₂ film and the titanate / lead zirconate ferroelectric film are selected. 4. The first conductor film and the second conductor film on the semiconductor substrate covered with the dielectric film constitute a cylindrical storage node. Item 2. A method of manufacturing a semiconductor device according to item 1. 5. When the area of one memory cell formed on the semiconductor substrate is 1 μm × 1.5 to 1.6 μm, the major axis of the cylindrical accumulation node is 1.0 to 1.4 μm.
5. The method for manufacturing a semiconductor device according to claim 4, wherein m and the minor axis are 0.3 to 0.6 μm. 6. When the SiO ₂ film or the SiO ₂ / Si ₃ N ₄ film is used as the dielectric film, the height of the cylindrical portion of the storage node is set to 0.5 to 1.0 μm. The method for manufacturing a semiconductor device according to claim 4, wherein 7. When the Ta ₂ O ₅ film or the lead titanate / zirconate ferroelectric film is used as the dielectric film, the height of the cylindrical portion of the storage node is set to 0.5 μm or less. The method for manufacturing a semiconductor device according to claim 4, wherein 8. In the case of forming the second contact hole in the second insulating film, the first conductor film is
2. The method of manufacturing a semiconductor device according to claim 1, wherein the method is used as an etching stopper when etching the second insulating film. 9. The method of manufacturing a semiconductor device according to claim 1, wherein a low concentration region is formed in an impurity diffusion layer of the MOS transistor to form an LDD structure.