JP2513495Y2 - Clamp circuit for video signal - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention relates to a clamp circuit for a video signal provided on the front side of an FM modulator of a VTR.

[Conventional technology]

Conventionally, there is a clamp circuit of this type shown in FIG. This is a sync tip clamp circuit, in which the sync tip level of the video signal supplied to the input terminal 1 is clamped by the potential of the capacitor 2. Reference numeral 3 is a diode for clamping, and 4 and 5 are amplifying transistors. Reference numeral 6 denotes an output terminal for sending a video signal to the FM modulator.

Conventionally, there is a pedestal clamp circuit as shown in FIG. In this, the pedestal level of the video signal supplied to the input terminal 1 is clamped by the potential of the capacitor 2. The timing of this clamp is set by the switch 8 which is operated by the clamp pulse at the clamp pulse input terminal 7.

[Problems to be solved by the device]

However, the conventional sync tip clamp circuit as shown in FIG. 4 has a problem that the sync signal level of the video signal obtained at the output terminal 6 becomes small.
Moreover, in the pedestal clamp circuit as shown in FIG.
Waveform distortion occurs in the pedestal level only when the switch 8 is closed. Further, immediately after the SW is turned off, the output signal changes according to the subsequent waveform change of the input video signal. As a result, the clamp operation is performed, but since the output voltage is kept constant by the clamp pulse width, it becomes impossible to transmit the video signal during that period, and there is a problem that the burst signal cannot be transmitted. Also, in both of them, since the video signal passes through the amplification circuit by the transistor 5 etc. after being clamped, there is a problem that DC drift occurs, and the conventional clamp circuit is provided separately from the pre-emphasis circuit. However, there was a problem that the cost increased and the cost increased.

The present invention has been made in view of the above problems, and provides a clamp circuit for a video signal, in which the level drop, distortion, drift and the like of the sync signal are reduced in clamping the pedestal section of the video signal. The purpose is to

[Means for solving the problem]

Means for achieving the above object in the present invention are as follows.
A differential amplifier circuit 12 whose video signal is supplied to the positive input terminal,
A first feedback circuit 21 for pre-emphasis that feeds back the video signal output from the differential amplifier circuit 12 to the negative input terminal of the differential amplifier circuit 12, and is output from the first feedback circuit 21. An output terminal 6 for sending a video signal to the frequency converter, and this output terminal 6
In the preceding stage, the gate circuit 23 that extracts the signal that becomes the level reference in the video signal from the video signal, and the average value of the signals extracted by this gate circuit 23 is held and compared with the reference voltage to obtain the error voltage with respect to the reference voltage. A video signal clamp circuit comprising a detecting means 26 for detecting and a second feedback circuit 28 for feeding back the error voltage detected by the detecting means 26 to the differential amplifier circuit 12. It is related to.

[Action]

In the above configuration, the voltage in the pedestal section is extracted and held by the voltage extracting means, and the error voltage is detected by the detecting means to obtain the control voltage.

Therefore, the video signal is sent to the output terminal without passing through the circuit for performing the clamp and hold operation, and is intended not to be directly adversely affected by the clamp and hold operation.

〔Example〕

Hereinafter, a first embodiment of the present invention will be described with reference to FIG.

Figure 1 shows the clamp circuit and the emphasis circuit.
First, the configuration will be described. The video signal supplied to the input terminal 1 is supplied to and amplified by the differential amplifier circuit 12 including the transistors 10 and 11. Reference numeral 13 is a non-inverted output line of the differential amplifier circuit 12, and this line 13 is connected to the output terminal 6 via a current amplifier circuit 16 composed of transistors 14 and 15. Further, a part of the output signal of the current amplification circuit 16 is fed back to the base of the transistor 11 of the differential amplification circuit 12 by the pre-emphasis feedback circuit 21 including the resistors 17, 18, 19 and the capacitor 20. There is. With this feedback, a pre-emphasis effect can be obtained. The video signal obtained at the output terminal 6 is supplied to a frequency modulation circuit (not shown) for frequency modulation. Further, the video signal obtained at the output terminal 6 is controlled by the control terminal 22 from which the clamp pulse control signal is obtained. The pedestal portion is extracted by the switch 23. The extracted signal is averaged and held by an integrating circuit including a resistor 24 and a capacitor 25. Reference numeral 26 is a comparison circuit, and 27 is a reference voltage generation circuit. In the comparison circuit 26, the held value of the pedestal voltage of the video signal extracted by the extraction means including the switch 23 and the reference voltage set by the reference voltage generation circuit 27 are compared. An error voltage with respect to the reference voltage is detected on the output side of the comparison circuit 26 which constitutes the detection means. This error voltage is fed back to the input side by the feedback circuit 28. The end of the feedback circuit 28 is a transistor
It is connected to a current mirror circuit 31 composed of 29 and 30. The current mirror circuit 31 can control the bias current of the entire differential amplifier circuit 12, and can control the DC potential of the video signal.

Reference numeral 32 is a loop filter which is composed of a resistor and a capacitor for stably operating the comparison circuit 26. Reference numeral 33 is a variable resistor for setting the reference voltage of the reference voltage generating circuit 27.

Next, the operation of the first embodiment having such a configuration will be described.

The video signal supplied to the input terminal 1 is the differential amplifier circuit 1
2. The signal is sent to the output terminal 6 via the current amplification circuit 16, but the video signal is pre-emphasized by the pre-emphasis feedback circuit 21. On the other hand, the video signal on the output side of the current amplification circuit 16 has its pedestal portion extracted by the closing operation of the switch 23, and is compared with the reference voltage by the comparison circuit 26 to detect an error voltage.
This error voltage is fed back to the current mirror circuit 31 by the feedback circuit 28, and the differential amplifier circuit 12
The bias voltage of is controlled to control the DC voltage of the video signal.

Therefore, the direct current level of the video signal is always determined correctly, and FM modulation and demodulation are performed so that a good reproduced image can be obtained.

The operational response characteristic can be set to an arbitrary characteristic by arbitrarily setting the value of the resistor 24, the capacitor 25, or the hoop filter 32.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention, in which the end of the feedback circuit 28 is connected to the inverting input terminal of the differential amplifier circuit 12, that is, the base side of the transistor 11. Therefore, the control voltage is applied to the inverting input terminal of the differential amplifier circuit 12 to set the DC level of the video signal.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention, in which the end of the feedback circuit 28 is connected to the non-inverting input terminal of the differential amplifier circuit 12, that is, the base side of the transistor 10. . The extracted voltage is 24 resistors and 25 capacitors.
And is held and amplified by the holding operational amplifier 34. The comparison circuit 35 performs both the error voltage detection and the reference voltage generation, and generates the control voltage of the feedback circuit 28. Therefore, the control voltage is applied to the non-inverting input terminal of the differential amplifier circuit 12 to set the DC level of the video signal.

Usually, the video signal is a signal having a DC component, and the DC component of the video is transmitted by the level difference between the pedestal level in the blanking period and the active video period. However, since the video signal is transmitted as an AC signal on the transmission line, the pedestal voltage of the video signal must be fixed when the DC component of the video is used, but as described above, the feedback that realizes the pre-emphasis characteristic is used. The pedestal voltage of the output video signal of the circuit 21 is extracted by the switch 23, and the integration circuit consisting of the resistor 24 and the capacitor 25 removes high frequency components (color burst signal, noise on the pedestal, waveform bend, etc.) and corresponds to the pedestal level DC voltage is obtained, and this voltage is compared with the reference voltage to obtain the error voltage,
This error voltage is fed back to the pre-emphasis feedback circuit.
By feeding back to 21 as the second feedback, the pedestal voltage can be fixed. Also,
At this time, since the second feedback is a DC error voltage, only the DC value of the video signal is moved, and the waveform distortion is not generated.

[Effect of device]

As described above, according to the present invention, the gate circuit extracts and clamps the pedestal portion from the output side video signal, and the error voltage is fed back from the second feedback circuit to the differential amplifier circuit. I am trying to maintain the DC level of. For this reason,
The video signal is not output via the clamp circuit, and there is no risk of the burst signal disappearing due to the level drop of the synchronization signal. Further, since the output video signal is compared with the reference voltage to detect the error voltage, the sync signal is not distorted or drifted, and the direct current level of the video signal can be set satisfactorily. Since it also functions as a pre-emphasis circuit, it is possible to provide a video signal clamp circuit having a simple circuit configuration.

[Brief description of drawings]

1 is a circuit diagram to which a clamp circuit according to a first embodiment of the present invention is applied, FIG. 2 is a circuit diagram to which a clamp circuit according to a second embodiment of the present invention is applied, and FIG. Third idea
FIG. 4 is a circuit diagram to which a clamp circuit showing the embodiment of FIG. 4 is applied, FIG. 4 is a circuit diagram showing an example of a conventional clamp circuit, and FIG. 5 is a circuit diagram showing another example of a conventional clamp circuit. 1 …… input terminal 6 …… output terminal 12 …… differential amplifier circuit 16 …… current amplifier circuit 21 …… pre-emphasis feedback circuit 22 …… control terminal 23 …… switch 26 …… comparator circuit 27 …… reference voltage Generation circuit 28 …… Feedback circuit 31 …… Current mirror circuit

Claims (1)

(57) [Scope of utility model registration request] 1. A differential amplifier circuit 12 to which a video signal is supplied to a positive input terminal, and a video signal output from the differential amplifier circuit 12 is fed back to a negative input terminal of the differential amplifier circuit 12. The first feedback circuit 21 for emphasis, the output terminal 6 for sending the video signal output from the first feedback circuit 21 to the frequency converter, and the video signal from the video signal A gate circuit 23 for extracting a signal serving as a level reference, a detection means 26 for holding an average value of the signals extracted by the gate circuit 23 and comparing it with a reference voltage, and detecting an error voltage with respect to the reference voltage, A second feedback circuit 28 for feeding back the error voltage detected by the detection means 26 to the differential amplifier circuit 12; Circuit.