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JP2504465B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JP2504465B2
JP2504465B2 JP62143064A JP14306487A JP2504465B2 JP 2504465 B2 JP2504465 B2 JP 2504465B2 JP 62143064 A JP62143064 A JP 62143064A JP 14306487 A JP14306487 A JP 14306487A JP 2504465 B2 JP2504465 B2 JP 2504465B2
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor pellet
substrate
semiconductor device
pellet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62143064A
Other languages
Japanese (ja)
Other versions
JPS63307746A (en
Inventor
光守 日高
長市郎 水野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62143064A priority Critical patent/JP2504465B2/en
Publication of JPS63307746A publication Critical patent/JPS63307746A/en
Application granted granted Critical
Publication of JP2504465B2 publication Critical patent/JP2504465B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は半導体ペレットを実装した半導体装置に適用
して有効な技術に関するもので、例えば、半導体ペレッ
トの実装に利用して有効な技術に関するものである。
Description: TECHNICAL FIELD The present invention relates to a technique effectively applied to a semiconductor device on which a semiconductor pellet is mounted, for example, a technique effectively used for mounting a semiconductor pellet. Is.

[従来の技術] 半導体ペレットを基板(リードフレーム、セラミック
パッケージ等)に固着するダイボンディング技術につい
ては、例えば、昭和60年11月20日に工業調査会から発行
された電子材料別冊「超LSI製造・試験装置ガイドブッ
ク」第131頁〜第137頁に記載されている。その概要を説
明すれば次のとおりである。
[Prior Art] For the die bonding technology for fixing semiconductor pellets to a substrate (lead frame, ceramic package, etc.), see, for example, the electronic material separate volume "VLSI Manufacturing" issued by the Industrial Research Board on November 20, 1985. -Test Equipment Guidebook ", pages 131 to 137. The outline is as follows.

即ち、この技術では、例えば、セラミック製の基板上
にプリフォーム材として金(Au)箔を載せ、さらに、こ
の金箔の上に半導体ペレットを載せてヒートブロックで
これらを加熱し、半導体ペレットのSiとAuの共晶を形成
して半導体ペレットの接着を行なうようになっている。
また、セラミック製の基板上にアルミニウム(Al)を蒸
着した後、上記金箔を載せて上記と同様な方法によって
Si、AuおよびAlの共晶を形成して接着したり、プリフォ
ーム材として銀ペーストもしくはエポキシ樹脂等を用い
て接着を行なうようにされた技術も知られている。
That is, in this technique, for example, a gold (Au) foil is placed as a preform material on a ceramic substrate, semiconductor pellets are placed on the gold foil, and these are heated by a heat block. And Au to form a eutectic to bond the semiconductor pellets.
Also, after depositing aluminum (Al) on a ceramic substrate, place the above gold foil on it and perform the same method as above.
There is also known a technique in which a eutectic of Si, Au and Al is formed and bonded, or a silver paste, an epoxy resin or the like is used as a preform material for bonding.

[発明が解決しようとする問題点] ところで、このような従来のダイボンディング技術に
よれば、半導体ペレットの下側に接合層を形成し、この
接合層によって半導体ペレットの固定がなされていたた
め次のような難点があった。
[Problems to be Solved by the Invention] By the way, according to the conventional die bonding technique as described above, since the bonding layer is formed on the lower side of the semiconductor pellet and the bonding layer fixes the semiconductor pellet, There was such a difficulty.

即ち、加熱を伴うボンディングにあっては、接合層の
冷却の際に、半導体ペレットと基板との熱膨張係数の差
に起因して半導体ペレット内部に熱応力が生じる。その
場合、大型の半導体ペレットをダイボンディングするも
のでは、その半導体ペレットの裏面と金箔等のプリフォ
ーム材とのなじみ具合を一様にすることが難しい。プリ
フォーム材としてはんだやエポキシ樹脂等を用いる場合
においても同様である。その結果、半導体ペレット内部
に生じる熱応力が不均一となり易く、半導体ペレットに
クラックが生じてしまう。このような問題は、ダイボン
ディングの際のみならず、半導体ペレットの樹脂封止を
行なったり、半導体装置を実際に使用する場合等におい
ても生じる。
That is, in the bonding accompanied by heating, thermal stress is generated inside the semiconductor pellet due to the difference in thermal expansion coefficient between the semiconductor pellet and the substrate when the bonding layer is cooled. In that case, in the case of die-bonding a large-sized semiconductor pellet, it is difficult to make the back surface of the semiconductor pellet and the preform material such as gold foil evenly fit. The same applies when solder, epoxy resin, or the like is used as the preform material. As a result, the thermal stress generated inside the semiconductor pellet is likely to be non-uniform, and the semiconductor pellet is cracked. Such a problem occurs not only during die bonding, but also when resin-sealing a semiconductor pellet or when a semiconductor device is actually used.

而して、このような半導体装置においては、このクラ
ックによって、半導体集積回路の特性劣化等が引き起こ
され、半導体装置の信頼性・歩留りの劣化を招来してい
た。
Therefore, in such a semiconductor device, the cracks cause deterioration of the characteristics of the semiconductor integrated circuit, resulting in deterioration of reliability and yield of the semiconductor device.

本発明は、かかる問題点を解消するためになされたも
ので、半導体ペレットのクラック発生を効果的に防止で
きる構造を持つ半導体装置を提供することを目的とす
る。
The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device having a structure capable of effectively preventing the occurrence of cracks in a semiconductor pellet.

この発明の前記ならびにそのほかの目的と新規な特徴
については、本明細書の記述および添附図面から明らか
になるであろう。
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[問題点を解決するための手段] 本願において開示される発明のうち代表的なものの概
要を説明すれば、下記のとおりである。
[Means for Solving Problems] An outline of typical ones of inventions disclosed in the present application will be described below.

即ち、半導体ペレットを搭載した半導体装置におい
て、上記半導体ペレットと搭載する半導体装置の基板と
の間には非接着性の放熱層を介在させ、半導体ペレット
の側面を包囲して基板上に接合層を形成し、この接合層
を介して半導体ペレットの側面と基板とを接着したもの
である。
That is, in a semiconductor device mounted with a semiconductor pellet, a non-adhesive heat dissipation layer is interposed between the semiconductor pellet and the substrate of the mounted semiconductor device, and a side surface of the semiconductor pellet is surrounded to form a bonding layer on the substrate. It is formed, and the side surface of the semiconductor pellet and the substrate are adhered to each other via this bonding layer.

[作用] 上記した手段によれば、半導体ペレットの基板への固
定が該半導体ペレットの周りに形成された接合層によっ
て行なわれているので、半導体ペレットと基板の熱膨張
係数の差等に起因して半導体ペレット内部に生じる残留
応力がその全体に亘って略均一となり、半導体ペレット
のクラック発生が抑止されるという作用によって、半導
体装置の信頼性・歩留りの向上という上記目的が達成さ
れる。
[Operation] According to the above-mentioned means, since the semiconductor pellet is fixed to the substrate by the bonding layer formed around the semiconductor pellet, it is caused by a difference in thermal expansion coefficient between the semiconductor pellet and the substrate. Thus, the residual stress generated inside the semiconductor pellet becomes substantially uniform over the whole thereof, and the crack generation in the semiconductor pellet is suppressed, whereby the above-mentioned object of improving the reliability and yield of the semiconductor device is achieved.

[実施例] 以下、本発明の実施例を図面に基づいて説明する。[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

第1図には本発明に係る半導体装置の第1の実施例が
示されている。
FIG. 1 shows a first embodiment of the semiconductor device according to the present invention.

同図において符号1は例えばセラミック製の基板を表
わし、この基板1上には熱伝導度の高い第1層(放熱
層)2が形成されている。この放熱層2は例えばゲル状
の金属粉からなり、その形成は半導体ペレット3を基板
1上へ載せる前になされる。また、この放熱層2は非接
着性であり、放熱層2の上に半導体ペレット3が単に接
触するようにして載置されている。そして、この半導体
ペレット3はそれを包み込むようにして形成された第2
図(接合層)4を介して放熱層2および基板1と接着さ
れている。つまり、この半導体装置においては、半導体
ペレット3を放熱層2の上に設置した後、例えば銀ペー
ストを半導体ペレット3を包み込むようにして塗布する
ことによって、半導体ペレット3が基板1に固定されて
いる。
In the figure, reference numeral 1 represents a ceramic substrate, for example, on which a first layer (heat dissipation layer) 2 having high thermal conductivity is formed. The heat dissipation layer 2 is made of, for example, gel-like metal powder, and is formed before the semiconductor pellet 3 is placed on the substrate 1. The heat dissipation layer 2 is non-adhesive, and the semiconductor pellets 3 are placed on the heat dissipation layer 2 so that they are in contact with each other. The semiconductor pellet 3 is formed into the second pellet formed so as to wrap it.
The heat dissipation layer 2 and the substrate 1 are bonded to each other via a drawing (bonding layer) 4. That is, in this semiconductor device, the semiconductor pellets 3 are fixed to the substrate 1 by placing the semiconductor pellets 3 on the heat dissipation layer 2 and then applying, for example, a silver paste so as to wrap the semiconductor pellets 3. .

このように構成された半導体装置によれば、半導体ペ
レットの周りに接合層4が形成されているので、半導体
ペレット3と基板1の熱膨張係数の等差に起因して半導
体ペレット3内部において生じる熱応力が部分的に集中
せずにその全体に亘って略均一となり、半導体ペレット
3のクラック発生が抑止されるという作用によって、半
導体装置の信頼性・歩留りの向上を図ることが可能とな
る。つまり、熱的影響を受けた場合、半導体ペレット3
は全体として引張荷重もしくは圧縮荷重を受けるだけな
ので、半導体ペレット3においてはクラックが発生しず
らくなり、その結果、半導体装置の信頼性・歩留りの向
上が図れる。
According to the semiconductor device configured as described above, since the bonding layer 4 is formed around the semiconductor pellet, the bonding layer 4 is formed inside the semiconductor pellet 3 due to an equal difference in thermal expansion coefficient between the semiconductor pellet 3 and the substrate 1. Due to the effect that the thermal stress becomes substantially uniform over the entire area without being partially concentrated and the generation of cracks in the semiconductor pellet 3 is suppressed, the reliability and yield of the semiconductor device can be improved. That is, when the semiconductor pellet 3 is thermally affected,
Since only the tensile load or the compressive load is received as a whole, cracks are less likely to occur in the semiconductor pellet 3, and as a result, the reliability and yield of the semiconductor device can be improved.

また、上記実施例の半導体装置では、半導体ペレット
3の下側に放熱層2を設けているので、パワートランジ
スタのように発熱を伴う半導体ペレット3では放熱性が
高まるという作用によって、半導体装置の信頼性がさら
に向上される。
Further, in the semiconductor device of the above-described embodiment, since the heat dissipation layer 2 is provided below the semiconductor pellet 3, the semiconductor pellet 3 that generates heat such as a power transistor has the effect of improving the heat dissipation property. Sex is further improved.

第2図および第3図には本発明に係る半導体装置の第
2の実施例が示されている。
2 and 3 show a second embodiment of the semiconductor device according to the present invention.

この半導体装置は、基板1に半導体ペレット埋設用の
凹部1aが多数設けられ、この各凹部1a内に放熱層2およ
び半導体ペレット3がそれぞれ埋設された構造となって
いる。また、この半導体装置では、埋設された半導体ペ
レット3の上面と基板1の上面とが略面一になるように
形成されており、それら上面にはマスク転写等によって
配線パターン5が形成され、半導体ペレット3,3間の結
線が行なわれるようになっている。なお、第2図および
第3図において、第1図と同一符号は同一構成部材を表
わすので、その重複した説明は省略する。
This semiconductor device has a structure in which a large number of recesses 1a for embedding a semiconductor pellet are provided in a substrate 1, and a heat dissipation layer 2 and a semiconductor pellet 3 are embedded in each recess 1a. Further, in this semiconductor device, the upper surface of the buried semiconductor pellet 3 and the upper surface of the substrate 1 are formed so as to be substantially flush with each other, and the wiring pattern 5 is formed on the upper surfaces by mask transfer or the like. The pellets 3 and 3 are connected to each other. Note that, in FIGS. 2 and 3, the same reference numerals as those in FIG. 1 represent the same constituent members, and thus their duplicated description will be omitted.

この実施例によれば、第1の実施例の効果が得られる
のは勿論のこと、埋設された半導体ペレット3の上面と
基板1の上面とが略面一になるように形成されているの
で、半導体ペレット3,3間の結線が容易に実現できる。
According to this embodiment, not only the effect of the first embodiment can be obtained, but also the upper surface of the buried semiconductor pellet 3 and the upper surface of the substrate 1 are formed to be substantially flush with each other. It is possible to easily connect the semiconductor pellets 3, 3.

以上本発明者によってなされた発明を実施例に基づき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention. Nor.

例えば、接合層4として銀ペーストの他にポリイミド
系の接着剤であるPIQ(日立化成(株)製)もしくはシ
リコーンゴム等半導体ペレットの接着剤一般を利用でき
る。また、接合層4を半導体ペレット3の外縁部に一部
盛るような状態で形成しても良い。
For example, as the bonding layer 4, in addition to the silver paste, a general adhesive for semiconductor pellets such as PIQ (manufactured by Hitachi Chemical Co., Ltd.) which is a polyimide adhesive or silicone rubber can be used. Alternatively, the bonding layer 4 may be formed so as to partially cover the outer edge portion of the semiconductor pellet 3.

以上の説明では主として本発明者によってなされた発
明をその背景となった利用分野である半導体ペレットの
実装技術について説明したが、ウェハを実装する場合等
にも利用できる。
In the above description, the invention made by the present inventor has been mainly described in the field of application, which is the application field of the semiconductor pellet mounting technique, but it can also be used in the case of mounting a wafer.

[発明の効果] 本願において開示される発明のうち代表的なものによ
って得られる効果を簡単に説明すれば下記のとおりであ
る。
[Effects of the Invention] The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

即ち、半導体ペレットの基板への固定をその周囲に形
成した接合層によって行なっており、半導体ペレットの
外縁と基板とが接合層を介して接着されているので、半
導体ペレットと基板との熱膨張係数の差等によって半導
体ペレット内部に生じる熱応力が均一化され、半導体ペ
レットのクラックの発生が効果的に防止され、その結
果、半導体装置の信頼性・歩留りの向上が図れる。
That is, the semiconductor pellet is fixed to the substrate by the bonding layer formed around the semiconductor pellet, and since the outer edge of the semiconductor pellet and the substrate are bonded via the bonding layer, the thermal expansion coefficient of the semiconductor pellet and the substrate is large. The thermal stress generated inside the semiconductor pellets is made uniform due to the difference between the two, and the generation of cracks in the semiconductor pellets is effectively prevented. As a result, the reliability and yield of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明に係る半導体装置の第1の実施例の縦断
面図、 第2図は本発明に係る半導体装置の第2の実施例の縦断
面図、 第3図は第2図の半導体装置の平面図である。 1……基板、2……放熱層、3……半導体ペレット、4
……接合層。
1 is a vertical sectional view of a first embodiment of a semiconductor device according to the present invention, FIG. 2 is a vertical sectional view of a second embodiment of a semiconductor device according to the present invention, and FIG. It is a top view of a semiconductor device. 1 ... Substrate, 2 ... Heat dissipation layer, 3 ... Semiconductor pellet, 4
…… Bonding layer.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】半導体ペレットを接合層によって基板に接
着した半導体装置において、上記半導体ペレットと上記
基板との間には非接着性の放熱層を介在させ、半導体ペ
レットの側面を包囲して基板上に接合層を形成し、この
接合層を介して半導体ペレットの側面と基板とを接着し
たことを特徴とする半導体装置。
1. In a semiconductor device in which a semiconductor pellet is bonded to a substrate by a bonding layer, a non-adhesive heat dissipation layer is interposed between the semiconductor pellet and the substrate, and a side surface of the semiconductor pellet is surrounded to form a substrate on the substrate. A bonding layer is formed on the substrate, and the side surface of the semiconductor pellet and the substrate are bonded via the bonding layer.
JP62143064A 1987-06-10 1987-06-10 Semiconductor device Expired - Lifetime JP2504465B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62143064A JP2504465B2 (en) 1987-06-10 1987-06-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62143064A JP2504465B2 (en) 1987-06-10 1987-06-10 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS63307746A JPS63307746A (en) 1988-12-15
JP2504465B2 true JP2504465B2 (en) 1996-06-05

Family

ID=15330073

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62143064A Expired - Lifetime JP2504465B2 (en) 1987-06-10 1987-06-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2504465B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5164328A (en) * 1990-06-25 1992-11-17 Motorola, Inc. Method of bump bonding and sealing an accelerometer chip onto an integrated circuit chip

Also Published As

Publication number Publication date
JPS63307746A (en) 1988-12-15

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