JP2591785B2 - Computer equipment - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer device, and more particularly, to a BI that controls input / output devices connected to the computer device.
The present invention relates to a device for controlling activation of an OS system.

[Conventional technology]

Conventionally, in this type of computer device, a BIOS (Basic Input Output Sys- tem) stored in a storage medium such as a ROM has been used.
tem) The input and output are controlled by reading the program.

Then, when the power is turned on, the CPU outputs the BIOS program storage address on the ROM and reads the BIOS program.

However, since the ROMT access time is longer than the minimum sigle time of the CPU, a wait cycle is inserted into the CPU to adjust the ROM access time.

[Problems to be solved by the invention]

Thus, in the conventional computer device, the CPU is B
Since it is necessary to insert a wait state when reading the IOS program, there is a problem that the processing by the minimum cycle of the CPU is hindered, and the efficiency of data processing by high-speed access is greatly reduced.

Even if an attempt is made to improve this kind of problem by using a high-speed access type ROM, the cost of the ROM is extremely high, which causes a rise in the total cost.

The present invention has been made in order to solve the above-described problem, and when a read access of a BIOS program stored at a predetermined address of a ROM occurs, the BIOS program is written from a predetermined address of a high-speed access type RAM, and then generated. By changing the ROM access request to RAM access without changing the ROM access address,
It is an object of the present invention to obtain a computer device capable of reading and controlling a BIOS program at any time at high speed.

[Means for solving the problem]

A computer device according to the present invention includes a random access memory that stores a basic input / output program stored in a read-only memory from a predetermined address, and a basic that writes a basic input / output program read from the read-only memory from a predetermined address of the random access memory. I / O program writing means, mask signal generation means for generating a mask signal for inhibiting memory access to read-only memory after completion of writing of basic I / O program to random access memory by the basic I / O program writing means, Memory access control means for converting an access request of the read only memory into a predetermined address access request of a random access memory based on a mask signal transmission state and an address signal output from the mask signal generation means; It is those provided.

[Action]

In the present invention, the basic input / output program read from the read-only memory by the basic input / output program writing means is sequentially written from a predetermined address of the random access memory, and when the writing of the basic input / output program to the random access memory is completed, the mask is output. Signal generating means generates a mask signal for inhibiting memory access to the read-only memory. Then, under this state, the memory access control means monitors the mask signal transmission state and the address signal, converts the read only memory access request into a predetermined address access request of the random access memory, and stores the request in the random access memory. Execute the basic input / output program reading.

[Embodiment] FIG. 1 is a block diagram for explaining a configuration of a computer apparatus according to an embodiment of the present invention.
It is composed of a PU and its peripheral circuits, and outputs read signals, write signals, address signals, and the like. 2 is a ROM which stores a basic input / output program (Basic Input Output System)
For example, it is stored corresponding to addresses F0000-FFFFF.
Reference numeral 3 denotes a RAM, which comprises an area E1 for storing a basic input / output program stored in a ROM 2 and an area E2 functioning as a work area of the CPU circuit 1, and the area E1 has an address of 0000.
0-DFFFF is allocated, and the area E2 has an address of E0000-F00
00 is allocated in advance.

A memory read signal 4 is output from the CPU circuit 1 to the AND gate 5. A mask signal 6 is input to the AND gate 5 from a mask signal generator 7 serving as a mask signal generating means of the present invention, and the AND of the mask signal 6 and the memory read signal 4 is used to generate a memory read signal 4 (memory access request). Prohibits sending to ROM2.

Reference numeral 8 denotes a RAM address controller serving as a memory access control means of the present invention, which monitors an address signal on an address bus 9 and, for example, sets the address line A ₁₆ to L level when the address content is F0000-FFFFF, the contents of the address in the case of non-F0000-FFFFF outputs the contents of the address lines a ₁₆ by the CPU circuit 1 is output as a direct RAM3 address information. As a result, the content of the address becomes F0000
Since the address lines A ₁₆ is L level when the -FFFFF, contents of the address is changed to E0000-EFFFF.

The CPU circuit 1 also serves as the basic input / output program writing means of the present invention, and the addresses F0000-FFFFF of the ROM 2 are used.
To read the basic input / output program and
The data is written to the addresses E0000 to F0000 of M3, and after this writing is completed, an instruction to set the mask signal 6 to the L level is output to the mask signal generator 7.

FIG. 2 is a schematic diagram for explaining a memory map changing process of the RAM 3 shown in FIG. 1, and the same components as those in FIG. 1 are denoted by the same reference numerals.

(A) corresponds to a memory mapping state in which the mask signal 6 is in the H level state, and (b) corresponds to a memory mapping state in which the mask signal 6 is in the L level state.

First, a process of writing the BOIS program into the RAM 3 will be described with reference to FIG.

First, after the power is turned on, the CPU circuit 1 outputs the memory read signal 4
Is set to the H level, and an instruction signal for setting the mask signal 6 from the mask signal generator 7 to the H level is output.

As a result, as shown in FIG. 2 (a), addresses F0000-FFFFF of ROM2 are accessed, and B2 stored in ROMT2 is accessed.
The IOS program is read, and the CPU circuit 1
Area E2 of RAM3 according to the address E0000-EFFFF output to
Write 5

Next, the CPU circuit 1 outputs an instruction signal for setting the mask signal 6 from the mask signal generator 7 to L level. As a result, the memory read signal 4 from the AND gate 5 becomes RO
Since it is output to M2, access to ROM2 from CPU circuit 1 is prohibited.

Here, the RAM address controller 8 monitors the address output from the CPU circuit 1 onto the address bus 9, and the
In 0-FFFFF, and when the mask signal 6 from the mask signal generator 7 is at the L level, forcedly set to L level address lines A _16.

As a result, the CPU circuit 1 stores the address F0000 for ROM2.
Even if -FFFFF is output to the address bus 9, the RAM address controller 8 converts the access into an address for E2 in the area of RAM3, that is, a memory access request for addresses E0000-EFFFF. A state in which a hardware configuration that virtualizes the state in which the memory mapping shown in b) is performed is established.

In the above embodiment, when the ROM 2 is disconnected from the CPU circuit 1, this is achieved by prohibiting the transmission of the memory read signal 4. However, the address output from the CPU circuit 1 is decoded to decode the chip select signal to the ROM 2. The same effect can be expected even if the transmission to the ROM 2 is prohibited.

FIG. 3 is a flowchart illustrating an example of a RAM access process according to the present invention. Note that (1) to (11) indicate each step. First, wait for the power to be turned on (1), and when the power is turned on, set the memory read signal 4 to the H level, that is, to “1”. (2). Next, the mask signal 6 is set to "1" (3). As a result, access to the ROM 2 becomes possible, and the CPU circuit 1 reads the BIOS program stored in the ROM 2 and starts writing to the addresses E0000-EFFFF of the RAM 3. Next, the process waits for the end of the writing of the BIOS program (4), and when the writing is completed, sets the mask signal 6 to "0" (5) and prohibits the CPU circuit 1 from accessing the ROM 2 (6).

Next, the RAM address controller 8 reads the address (7), and the contents are read from the address F0000-FFFFF for ROM2.
To determine whether it (8), to force the YES if address lines A ₁₆ to L level (9), a memory of a memory access request to addresses F0000-FFFFF for ROM2 to RAM3 address E0000-EFFFF Change to an access request (10) and proceed to other processing.

On the other hand, if the determination in step (8) is NO, the RAM 3 is accessed at the specified address (11), and the process proceeds to another process.

〔The invention's effect〕

As described above, the present invention provides a random access memory that stores a basic input / output program stored in a read-only memory from a predetermined address, and writes a basic input / output program read from a read-only memory from a predetermined address of the random access memory. Basic input / output program writing means, mask signal generation means for generating a mask signal for inhibiting memory access to the read-only memory after completion of writing the basic input / output program to the random access memory by the basic input / output program writing means, Memory access control means for converting an access request for a read-only memory into a predetermined address access request for a random access memory based on a mask signal transmission state and an address signal output from the mask signal generation means; Thus, it is possible to configure hardware that makes a memory access request to the storage address of the basic input / output program stored in the read-only memory a memory access to the storage address of the basic input / output program stored in the random access memory. The start of the basic input / output program can be controlled without changing the storage address of the stored basic input / output program, and the basic input / output program can be written to the random access memory without changing the memory map configuration of the read-only memory. it can.

Therefore, without changing the ROM access address,
It has an excellent effect of building an inexpensive computer system that can read and control the BIOS program from the AM at any time at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining a configuration of a computer apparatus showing one embodiment of the present invention, and FIG.
FIG. 3 is a schematic diagram illustrating a RAM memory map change process, and FIG. 3 is a flowchart illustrating an example of a RAM access process according to the present invention. In the figure, 1 is a CPU circuit, 2 is a ROM, 3 is a RAM, 4 is a memory read signal, 5 is an AND gate, 6 is a mask signal, 7 is a mask signal generator, 8 is a RAM address controller, and 9 is an address bus. It is.

Claims (1)

(57) [Claims] 1. A computer device for reading a basic input / output program stored in a read-only memory and processing input / output data, wherein a random access storing a basic input / output program stored in the read-only memory from a predetermined address. A memory, a basic input / output program writing means for writing a basic input / output program read from the read-only memory from a predetermined address of the random access memory, and a basic input / output program writing to the random access memory by the basic input / output program writing means After completion, a mask signal generating means for generating a mask signal for inhibiting a memory access to the read-only memory, and the read-on state based on a mask signal transmission state and an address signal output from the mask signal generating means. Computer apparatus being characterized in that includes a memory access control means for converting the access request of the memory at a predetermined address access request of the random access memory.