JP2587722Y2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2587722Y2 JP2587722Y2 JP4781393U JP4781393U JP2587722Y2 JP 2587722 Y2 JP2587722 Y2 JP 2587722Y2 JP 4781393 U JP4781393 U JP 4781393U JP 4781393 U JP4781393 U JP 4781393U JP 2587722 Y2 JP2587722 Y2 JP 2587722Y2
- Authority
- JP
- Japan
- Prior art keywords
- support plate
- main surface
- semiconductor chip
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本考案は、複数の半導体素子を含
む半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a plurality of semiconductor elements.
【０００２】[0002]
【従来の技術】リードフレームの支持板の一方の主面に
複数の半導体素子（以下、チップという）を固着し、こ
のチップの電極とリードフレームの外部リードとを金属
細線によって電気的に接続した半導体装置は公知であ
る。2. Description of the Related Art A plurality of semiconductor elements (hereinafter referred to as chips) are fixed to one main surface of a support plate of a lead frame, and electrodes of the chip are electrically connected to external leads of the lead frame by thin metal wires. Semiconductor devices are known.
【０００３】[0003]
【考案が解決しようとする課題】ところで、半導体装置
の高機能化を図るためにはチップ数を増加しなければな
らない。上述のような支持板を使用する半導体装置にお
いて、チップ数を増加する場合には、１枚の支持板に複
数のチップを搭載することができるように支持板の面積
を大きくするか、複数のチップを支持するために複数の
支持板を用意することが必要になり、装置の大型化を招
いた。The number of chips must be increased in order to increase the functionality of a semiconductor device. In a semiconductor device using a support plate as described above, when the number of chips is increased, the area of the support plate may be increased so that a plurality of chips can be mounted on one support plate, or a plurality of chips may be provided. In order to support the chip, it is necessary to prepare a plurality of support plates, resulting in an increase in the size of the device.
【０００４】そこで、本考案の目的は小型化が達成でき
るのみでなく、製作しやすい構造を有している半導体装
置を提供することにある。[0004] Therefore, an object of the present invention is to provide a semiconductor device having a structure which can not only achieve miniaturization but also is easy to manufacture.
【０００５】上記目的を達成するための本考案は、実施
例を示す図面の符号を参照して説明すると、一方及び他
方の主面を有する金属支持板３と、前記金属支持板３の
前記一方の主面に固着された第１の半導体チップ１と、
前記金属支持板３の前記他方の主面に固着された第２の
半導体チップ２と、複数の外部リード６、７と、前記複
数の外部リード６、７と前記第１及び第２の半導体チッ
プ１、２のボンディングパッド１１、１２、１４、１５
とを接続している内部接続用金属細線８ａ、８ｂ、９
ａ、９ｂと、前記第１及び第２の半導体チップ１、２と
前記支持板３と前記複数の内部接続用金属細線８ａ、８
ｂ、９ａ、９ｂと前記複数の外部リード６、７の先端部
とを被覆するように形成された絶縁性被覆樹脂体１０と
を有する半導体装置において、前記第１の半導体チップ
１は前記支持板３の前記一方の主面側から見て前記支持
板３から張り出さないように形成され、前記第２の半導
体チップ２は前記支持板３の前記一方の主面側から見て
前記支持板３から張り出した部分２ａ、２ｂを有するよ
うに形成され、前記第１の半導体チップ１の前記ボンデ
イングパッド１１、１２は前記第１の半導体チップ１の
前記支持板３に対して固着されている側の主面とは反対
の主面上に設けられ、前記第２の半導体チップ１の前記
ボンディングパッド１４、１５は前記第２の半導体チッ
プ２の前記支持板３に対して固着されている側の主面に
設けられ、前記第２の半導体チップ２は前記支持板３に
対して固着されている側の主面に配線導体層を有し且つ
前記配線導体層を被覆するように設けられた絶縁性接着
層５によって前記支持板３に固着されていることを特徴
とする半導体装置に係わるものである。[0005] To achieve the above object, the present invention has been implemented.
Description will be made with reference to reference numerals in the drawings showing examples.
A metal support plate 3 having one main surface;
A first semiconductor chip 1 fixed to the one main surface;
A second fixed to the other main surface of the metal support plate 3;
A semiconductor chip 2, a plurality of external leads 6, 7;
External leads 6, 7 and the first and second semiconductor chips.
Bonding pads 11, 12, 14, 15
Metal wires 8a, 8b, 9 for internal connection
a, 9b, the first and second semiconductor chips 1, 2,
The support plate 3 and the plurality of metal wires for internal connection 8a, 8
b, 9a, 9b and tips of the plurality of external leads 6, 7
An insulating coating resin body 10 formed so as to cover
The first semiconductor chip
1 is the support plate viewed from the one main surface side of the support plate 3
The second semiconductor is formed so as not to protrude from the plate 3.
The body chip 2 is viewed from the one main surface side of the support plate 3.
It has portions 2a and 2b projecting from the support plate 3.
The bond of the first semiconductor chip 1
Ining pads 11 and 12 are provided on the first semiconductor chip 1.
Opposite to the main surface on the side fixed to the support plate 3
And provided on the main surface of the second semiconductor chip 1.
The bonding pads 14 and 15 are connected to the second semiconductor chip.
The main surface of the side of the pump 2 which is fixed to the support plate 3
And the second semiconductor chip 2 is provided on the support plate 3.
Having a wiring conductor layer on the main surface on the side fixed to
Insulating adhesive provided to cover the wiring conductor layer
The present invention relates to a semiconductor device which is fixed to the support plate 3 by a layer 5 .
【０００６】[0006]
【考案の効果】本考案は次の効果を有する。 （イ） 第１及び第２の半導体チップ１、２は金属製支
持板３によって支持されているので、これ等を安定的に
支持することができる。 （ロ） 第２の半導体チップ２のボンディングパッド１
４、１５は張り出し部分２ａ、２ｂに設けられ、平面的
に見て第１の半導体チップ１のボンディングパッド１
１、１２と同一側に配置されているので、外部リード
６、７に対する金属細線９ａ、９ｂによる接続を容易に
達成することができる。 （ハ） 第２の半導体チップ２の表面には配線導体層が
設けられているが、絶縁性接着層５によって第２の半導
体チップ２が支持板３の固着されているので、配線導体
層の絶縁を確保することができる。 [Effects of the Invention] The present invention has the following effects. (A) The first and second semiconductor chips 1 and 2 are made of metal.
These are stably supported because they are supported by the holding plate 3.
Can be supported. (B) Bonding pad 1 of second semiconductor chip 2
4 and 15 are provided on the overhang portions 2a and 2b,
The bonding pad 1 of the first semiconductor chip 1
Since they are arranged on the same side as 1 and 12, external leads
Easy connection to metal wires 6 and 7 by thin metal wires 9a and 9b
Can be achieved. (C) On the surface of the second semiconductor chip 2, a wiring conductor layer is provided.
Provided, but the second semiconductor layer is formed by the insulating adhesive layer 5.
Since the body chip 2 is fixed to the support plate 3, the wiring conductor
Layer insulation can be ensured.
【０００７】[0007]
【実施例】次に、図１を参照して本考案の実施例に係わ
る半導体装置を説明する。この半導体装置は、第１及び
第２の半導体素子としての第１及び第２のモノリシック
ＩＣチップ１、２と、これ等を支持する金属平板から成
る支持板３と、接着層４、５と、複数の外部リード６、
７と、内部接続用金属細線８ａ、８ｂ、９ａ、９ｂと、
絶縁性被覆樹脂体１０とから成る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. This semiconductor device includes first and second monolithic IC chips 1 and 2 as first and second semiconductor elements, a support plate 3 made of a flat metal plate for supporting them, adhesive layers 4 and 5, A plurality of external leads 6,
7, metal wires 8a, 8b, 9a, 9b for internal connection;
And an insulating coating resin body 10.
【０００８】第１のチップ１は支持板３の一方の主面
（表面）に絶縁性接着層４で固着され、第２のチップ２
は支持板３の他方の主面（裏面）に絶縁性接着剤５で固
着されている。第１及び第２のチップ１、２は種々の半
導体領域や電極層が周知の方法で設けられているが、図
１では省略されている。第１のチップ１は支持板３より
も幾らか小さく形成され、この表面にリード細線接続用
電極即ちボンディングパッド１１、１２を有し、これ等
に金属細線８ａ、８ｂの一端が周知のワイヤボンディン
グ方法で固着されている。金属細線８ａ、８ｂの他端は
一方及び他方の側の複数の外部リード６、７から選択さ
れたものに固着されている。The first chip 1 is fixed to one main surface (front surface) of the support plate 3 with an insulating adhesive layer 4 and the second chip 2
Is fixed to the other main surface (back surface) of the support plate 3 with an insulating adhesive 5. The first and second chips 1 and 2 are provided with various semiconductor regions and electrode layers by a known method, but are omitted in FIG. The first chip 1 is formed somewhat smaller than the support plate 3 and has on its surface electrodes for connecting fine lead wires, ie, bonding pads 11 and 12, to which one ends of fine metal wires 8a and 8b are connected by a known wire bonding. Secured in a way. The other ends of the thin metal wires 8a, 8b are fixed to one selected from the plurality of external leads 6, 7 on one and the other sides.
【０００９】第２のチップ２は矢印１３で示すように支
持板３の一方の主面側から見て支持板３から張り出した
部分２ａ、２ｂを有し、この表面（支持板３に近い側の
面）にボンディングパッド１４、１５が設けられ、これ
等に金属細線９ａ、９ｂの一端が周知のワイヤワボンデ
ィング法で固着されている。金属細線９ａ、９ｂの他端
は一方及び他方の側の複数の外部リード６、７から選択
されたものに固着されている。なお、この実施例では、
支持板３及び第２のチップ２が共に平面形状四角形であ
り、第２のチップ２の外部リード６、７側の２辺に沿っ
た帯状領域が張り出し部分２ａ、２ｂとなっている。The second chip 2 has portions 2a and 2b projecting from the support plate 3 as viewed from one main surface side of the support plate 3 as shown by an arrow 13, and the surface thereof (the side close to the support plate 3). Are provided with bonding pads 14 and 15, and one ends of the thin metal wires 9a and 9b are fixed to these by a well-known wire bonding method. The other ends of the thin metal wires 9a and 9b are fixed to one selected from a plurality of external leads 6 and 7 on one and the other sides. In this embodiment,
The support plate 3 and the second chip 2 are both rectangular in plan view, and the strip-shaped regions along the two sides of the second chip 2 on the side of the external leads 6, 7 are overhanging portions 2a, 2b.
【００１０】第２のチップ２の上面中央領域に配線導体
層（図示せず）が存在するが、絶縁性接着層５で被覆さ
れているために支持板３から電気的に分離されている。
なお、第２のチップ２の上面の配線導体層の上に特別に
絶縁層を設け、第２のチップ２と支持板３との電気的絶
縁をより確実に達成することもできる。また、第１のチ
ップ１の下面の一部又は全部及び第２のチップ２の上面
の一部を必要に応じて支持板３に半田等で電気的に結合
することもできる。Although a wiring conductor layer (not shown) exists in the central region of the upper surface of the second chip 2, it is electrically separated from the support plate 3 because it is covered with the insulating adhesive layer 5.
Note that an insulating layer may be provided on the wiring conductor layer on the upper surface of the second chip 2 so as to more reliably achieve the electrical insulation between the second chip 2 and the support plate 3. It can also be electrically coupled with solder or the like to the support plate 3 as necessary part of the first part or the whole and a second top surface of the chip 2 of the lower surface of the chip 1.
【００１１】支持板３と外部リード６、７はリードフレ
ームから得たものであり、製作段階においてはそれぞれ
が相互に連結されている。複数の外部リード６、７の中
の１本又は２本が支持板に連結されている。絶縁被覆樹
脂体１０は周知のモールド法によって第１及び第２のチ
ップ１、２と支持板３と金属細線８ａ、８ｂ、９ａ、９
ｂと外部リード６、７の一部とを被覆するように形成さ
れている。The support plate 3 and the external leads 6 and 7 are obtained from a lead frame, and are connected to each other in a manufacturing stage. One or two of the plurality of external leads 6 and 7 are connected to the support plate. The insulating coating resin body 10 is formed by a well-known molding method using the first and second chips 1 and 2, the support plate 3, and the fine metal wires 8 a, 8 b, 9 a, 9
b and a part of the external leads 6 and 7 are formed.
【００１２】半導体装置を図１の構造にすれば、支持板
３の両主面を第１及び第２のチップ１、２の固着に使用
できるので、半導体装置の小型化が達成される。また、
第２のチップ２は張り出した部分２ａ、２ｂを有するの
で、ここを使用して金属細線９ａ、９ｂによる接続を第
１のチップ１と同一主面側から容易に達成することがで
きる。When the semiconductor device has the structure shown in FIG. 1, both main surfaces of the support plate 3 can be used for fixing the first and second chips 1 and 2, so that the size of the semiconductor device can be reduced. Also,
Since the second chip 2 has the protruding portions 2a and 2b, the connection using the thin metal wires 9a and 9b can be easily achieved from the same main surface side as the first chip 1 by using this.
【図１】実施例の半導体装置を示す中央縦断面図であ
る。FIG. 1 is a central longitudinal sectional view showing a semiconductor device of an embodiment.
１、２ 第１及び第２のチップ ３ 支持板 ２ａ、２ｂ 張り出し部分 1, 2 First and 2nd chips 3 Support plate 2a, 2b Overhang portion
Claims (1)
（３）と、前記金属支持板（３）の前記一方の主面に固
着された第１の半導体チップ（１）と、前記金属支持板
（３）の前記他方の主面に固着された第２の半導体チッ
プ（２）と、複数の外部リード（６、７）と、前記複数
の外部リード（６、７）と前記第１及び第２の半導体チ
ップ（１、２）のボンディングパッド（１１、１２、１
４、１５）とを接続している内部接続用金属細線（８
ａ、８ｂ、９ａ、９ｂ）と、前記第１及び第２の半導体
チップ（１、２）と前記支持板（３）と前記複数の内部
接続用金属細線（８ａ、８ｂ、９ａ、９ｂ）と前記複数
の外部リード（６、７）の先端部とを被覆するように形
成された絶縁性被覆樹脂体（１０）とを有する半導体装
置において、 前記第１の半導体チップ（１）は前記支持板（３）の前
記一方の主面側から見て前記支持板（３）から張り出さ
ないように形成され、 前記第２の半導体チップ（２）は前記支持板（３）の前
記一方の主面側から見て前記支持板（３）から張り出し
た部分（２ａ、２ｂ）を有するように形成され、 前記第１の半導体チップ（１）の前記ボンデイングパッ
ド（１１、１２）は前記第１の半導体チップ（１）の前
記支持板（３）に対して固着されている側の主面とは反
対の主面上に設けられ、 前記第２の半導体チップ（２）の前記ボンディングパッ
ド（１４、１５）は前記第２の半導体チップ（１）の前
記支持板（３）に対して固着されている側の主面に設け
られ、 前記第２の半導体チップ（２）は前記支持板（３）に対
して固着されている側の主面に配線導体層を有し且つ前
記配線導体層を被覆するように設けられた絶縁性接着層
（５）によって前記支持板（３）に固着されて いること
を特徴とする半導体装置。1. A metal support plate having one and another main surface.
(3) and fixing the metal support plate (3) to the one main surface.
A mounted first semiconductor chip (1) and the metal support plate
(3) a second semiconductor chip fixed to the other main surface;
(2), a plurality of external leads (6, 7),
External leads (6, 7) and the first and second semiconductor chips.
Bonding pads (11, 12, 1)
4, 15), and a metal wire for internal connection (8
a, 8b, 9a, 9b) and the first and second semiconductors
Chips (1, 2), the support plate (3), and the plurality of insides
Connection metal wires (8a, 8b, 9a, 9b) and the plurality
So as to cover the tips of the external leads (6, 7).
Semiconductor device having insulating coating resin body (10) formed
In location, the first semiconductor chip (1) in front of the support plate (3)
The support plate (3) projects from the one main surface side.
And the second semiconductor chip (2) is located in front of the support plate (3).
Projecting from the support plate (3) when viewed from one main surface side
And the bonding package of the first semiconductor chip (1).
(11, 12) are in front of the first semiconductor chip (1).
The main surface on the side fixed to the support plate (3) is opposite to the main surface.
The bonding package of the second semiconductor chip (2) is provided on a pair of main surfaces.
(14, 15) are in front of the second semiconductor chip (1).
Provided on the main surface on the side fixed to the support plate (3)
Is, the second semiconductor chip (2) is paired to the support plate (3)
A wiring conductor layer on the main surface on the side fixed
An insulating adhesive layer provided so as to cover the wiring conductor layer
(5) The semiconductor device is fixed to the support plate (3) by (5) .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4781393U JP2587722Y2 (en) | 1993-08-09 | 1993-08-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4781393U JP2587722Y2 (en) | 1993-08-09 | 1993-08-09 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0714657U JPH0714657U (en) | 1995-03-10 |
| JP2587722Y2 true JP2587722Y2 (en) | 1998-12-24 |
Family
ID=12785810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4781393U Expired - Lifetime JP2587722Y2 (en) | 1993-08-09 | 1993-08-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2587722Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102979854A (en) * | 2012-08-29 | 2013-03-20 | 鹤壁汽车工程职业学院 | Flexible speed reducer with large transmission ratio |
-
1993
- 1993-08-09 JP JP4781393U patent/JP2587722Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0714657U (en) | 1995-03-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6673650B2 (en) | Multi chip semiconductor package and method of construction | |
| US5637828A (en) | High density semiconductor package | |
| JPH03169062A (en) | Semiconductor device | |
| JPH064595Y2 (en) | Hybrid IC | |
| JP3801989B2 (en) | Semiconductor device package having a die protruding from a lead frame pad | |
| JPH05326735A (en) | Semiconductor device and manufacture thereof | |
| KR100621547B1 (en) | Multi-chip package | |
| US7122885B2 (en) | Flip-chip packaging | |
| JPS622628A (en) | Semiconductor device | |
| JPS628534A (en) | Mounting structure for semiconductor device | |
| JP2587722Y2 (en) | Semiconductor device | |
| JPH0645504A (en) | Semiconductor device | |
| JPH0582582A (en) | Semiconductor device | |
| JPH0521698A (en) | Semiconductor device | |
| JP3942495B2 (en) | Semiconductor device | |
| JPH03109760A (en) | Semiconductor device | |
| JPH0622997Y2 (en) | Insulator-sealed semiconductor device | |
| JP2629461B2 (en) | Resin-sealed semiconductor device | |
| JPH04349655A (en) | Resin-sealed multi-chip package | |
| JPH01206660A (en) | Lead frame and semiconductor device utilizing same | |
| JP2000124392A (en) | Semiconductor device | |
| JPH0513624A (en) | Semiconductor device | |
| JPS6245159A (en) | Semiconductor device | |
| JPH05283592A (en) | Semiconductor lead frame | |
| JPH0670243U (en) | Circuit board device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071023 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081023 Year of fee payment: 10 |
|
| EXPY | Cancellation because of completion of term | ||
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081023 Year of fee payment: 10 |