JP2570837B2 - Microprocessor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor whose operating frequency can be divided with respect to an input clock.

[Conventional technology]

Among conventional microprocessors, those whose frequency can be divided by software and whose number of waits inserted in a bus cycle can be programmed by software can be inserted even if the operating frequency is changed. The number of weights did not change.

This conventional example will be described with reference to the block diagram of FIG. 6 and the timing chart of FIG. In FIG. 6, reference numeral 11 denotes a weight control register for storing the set number of weights;
Is the operating frequency control unit that divides the input clock, 14
Is a bus cycle control unit, 15 is a signal line for inputting an external clock, 16 is a signal line for transmitting the number of waits set in the wait control register 11 to the bus cycle control unit 14, and 20 is an operating frequency control unit. 12 is a signal line for transmitting the operation clock divided by 12 to the bus cycle control unit 14.

As shown in the timing chart of FIG. 7A, the basic bus cycle of the microprocessor is composed of two clocks T1 and T2. By inserting a TW state into a bus cycle for a memory or an input / output device having a long access time, the bus cycle can be extended.
For example, assuming that "4" is set as the number of weights to be inserted into the weight control register 11, the information is transmitted to the bus cycle controller 14 via the signal line 16. As shown in the timing diagram of FIG. 7 (b), the bus cycle control unit 14 adds TW to the basic bus cycles T1 and T2.
To extend the bus cycle. Here, when the operating frequency is set to 1/2, the operating frequency control unit 12 divides the frequency of the input clock 15 by 2 and transmits it to the bus cycle control unit 14. This bus cycle controller 14 completes one bus cycle in twice as long as the timing chart of FIG. 7B, as shown in the timing chart of FIG. 7C.

[Problems to be solved by the invention]

As described above, in the conventional microprocessor, the operating frequency can be divided by software and the number of waits to be inserted in a bus cycle can be programmed by software. Even if it is lowered, the number of weights inserted will not change, and even when operating at low frequency, the same number of weight states will be inserted as when operating at high frequency, which will cause unnecessary performance degradation Had disadvantages.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor in which the number of wait states set by software can be automatically adjusted in accordance with the number of divisions of an input clock. To provide.

[Means for solving the problem]

According to the configuration of the present invention, in a microprocessor in which an operating frequency is frequency-divided by a predetermined frequency with respect to an input clock by software and output, the number of wait states inserted to extend a bus cycle is reduced. Storage means for storing, and shift means for shifting the number of weight states from the storage means in a direction in which the number of weight states is reduced when the frequency division number is large in accordance with the frequency division number, and outputting the shifted state. And a bus cycle control means for controlling a wait state to be inserted by an output from the shift means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

1 and 2 are a block diagram of a first embodiment of the present invention and a waveform diagram showing the operation timing. In the figure, reference numeral 11 denotes a wait control register for storing a set number of waits, 12 denotes an operating frequency control unit for dividing an input clock, and 13 denotes a content of the wait control register 11 divided by an operating frequency control unit 12. Shifter that shifts according to the frequency division ratio of the operating clock, 14 is a bus cycle control unit,
Reference numeral 15 denotes a signal line for inputting an external clock, and reference numeral 16 denotes a number of waits set in the wait control register 11.
13 is a signal line for transmitting the frequency division ratio divided by the operating frequency control unit 12 to the shifter 13, and 19 is a bus cycle control unit 14 for indicating the number of weights actually inserted from the shifter 13.
Reference numeral 20 denotes a signal line for transmitting the operation clock divided by the operation frequency control unit 12 to the bus cycle control unit 14.

As shown in FIG. 3, the shifter 13 according to the present embodiment is configured such that the weight control register 11
26 and an inverter 27 for the frequency division number signal 18. These transfer gates 21 to 26
Is “1”, the transfer gates 21 to 23 are “1”,
The transfer gates 24-26 become "0" and output "010". When the frequency division number signal 18 is "0", the transfer gates 24-26 are "1", and the transfer gates 21-23 are "0". And "100" is output.

First, "100" (4) is set by the program as the number of waits to be inserted in the bus cycle.
Here, assuming that the input clock is set to be used as it is as the operation clock, the operating frequency control unit 12 transmits the input clock 15 as it is to the bus cycle control unit 14 via the signal line 20 as the operation clock. On the other hand, the fact that the frequency of the input clock is not divided is transmitted to the shifter 13 by making the signal line 18 inactive.

The basic bus cycle completes one bus cycle with two clocks T1 and T2 as shown in the timing diagram of FIG. 2A, but the wait control register 11 contains "4" as the number of waits to be inserted. Since it is set and the signal line 18 is inactive, the shifter 13 transmits to the bus cycle control unit 14 via the signal line 19 so as to insert four waits. Therefore, the bus cycle control unit 14
As shown in FIG. 7B, four TWs are inserted.

Next, assuming that the input clock is set to be used by dividing it by two, the operating frequency control unit 12 divides the input clock 15 by two and transmits it to the bus cycle control unit 14 via the signal line 20. On the other hand, the signal line 18 is activated to transmit to the shifter 13 that the input clock is used by dividing the frequency by two. Here, “4” is set in the weight control register 11 as the number of weights to be inserted.
Is active, the shifter 13 shifts the set number of weights “100” rightward by one bit to “01”.
The signal is transmitted to the bus cycle controller 14 via the signal line 19 so that two waits are inserted. Therefore, buses
The cycle control unit 14 inserts two TWs as shown in the timing chart of FIG. 2 (c).

As shown in the timing chart of FIG. 2, even if the number of waits to be inserted is two, the operation clock is doubled, so that one bus cycle in the timing chart of FIG. This is longer than one bus cycle in the timing diagram b), and the access time can be sufficiently secured.

The present embodiment is an example of the case where the frequency is divided by 2. However, the number of weights can be easily controlled to an optimum value by shifting right by 2 bits in the case of dividing by 4 and shifting right by 3 bits in the case of dividing by 8. be able to.

FIGS. 4 and 5 are a block diagram and a waveform diagram showing a timing chart of the second embodiment of the present invention. This embodiment is different from FIG. 1 in that a ready (READY) signal line 17 for controlling the number of waits externally inserted into a bus cycle is added.

In this embodiment, "100" (4) is set in the wait control register 11 by the program as the number of waits to be inserted in the bus cycle. Here, assuming that the input clock is set to be used as it is as the operation clock, the operation frequency control unit 12
The signal 15 is transmitted as it is as an operation clock to the bus cycle control unit 14 via the signal line 20, and the fact that the frequency of the input clock is not divided is transmitted to the shifter 13 by inactivating the signal line 18. When the READY signal line 17 is "1" as shown in the timing charts of FIGS. 5 (a) and 5 (b), the basic bus cycle is one bus cycle with two clocks T1 and T2.
Complete the cycle.

Since the number of weights to be inserted is set to “4” in the weight control register 11 and the signal line 18 is inactive, the shifter 13 is controlled by the signal line 19 so that four waits are inserted. The information is transmitted to the unit 14. Here, since the READY signal line 17 is "0", the bus cycle control unit 14 continues until the READY signal line 17 becomes "1" as shown in the timing charts of FIGS. 5 (c) and 5 (d). Then, insert 7 TWs. Next, assuming that the input clock is set to be used by dividing it by two, the operating frequency control unit 12 divides the input clock (15) by two and divides the input clock (15) by two via the signal line 20. Communicate to 14. On the other hand, the signal line 18 is activated to transmit to the shifter 13 that the input clock is divided by two and used. Here, 4 is set as the number of weights to be inserted in the weight control register 11, but since the signal line 18 is now active, the shifter 13 shifts the set number of weights “100” by one bit to the right. The signal is shifted to “010” and transmitted to the bus cycle controller 14 via the signal line 19 so as to insert two waits. Here, since the READY signal line 17 is "0", the bus cycle control unit 14 inserts three TWs as shown in the timing charts of FIGS. 5 (e) and 5 (f).

As shown in the timing diagram of FIG. 5, even if the number of weights to be inserted is two, the bus control signal is input by an external control signal.
The cycle can be extended, and the optimal number of weights can be inserted.

〔The invention's effect〕

As described above, according to the present invention, the operating frequency can be divided by software, the number of waits inserted in a bus cycle can be programmed by software, and when the operating frequency is lowered, the number of waits inserted can be reduced. By making it variable, it is possible to minimize the performance degradation of the entire system.

Power consumption can be reduced by dividing the operating frequency by software and operating at a low frequency, which is particularly effective in a battery-operable system such as a laptop computer.

In this case, it is also important to minimize the performance degradation of the entire system even if the operating frequency is reduced. That is, when operating at a low frequency, the access time to the memory and the input / output device can be spared, and the number of weights is not required as much as when operating at a high frequency. Then, half the number of weights to be inserted is sufficient.

As described above, the present invention has an effect that the performance degradation of the entire system can be minimized by automatically adjusting the preset number of weights according to the operating frequency.

[Brief description of the drawings]

FIGS. 1 and 4 are block diagrams showing the configuration of the first and second embodiments of the present invention. FIGS. 2 and 5 are waveform diagrams showing the operation timings of FIGS. 1 and 4. 3 is a circuit diagram of an example of the shifter 13 of FIG. 1, FIG. 6 is a block diagram of an example of a frequency division control unit of a conventional processor, and FIG. 7 is a waveform diagram showing operation timings of FIG. 11 Wait control register, 12 Operating frequency control unit, 13 Shifter, 14 Bus cycle control unit, 15
... Input clock, 16 ... Set wait number signal line, 17 ...
Ready signal line, 18 division frequency signal line, 19 insertion number signal line, 20 operation clock line, 21 to 26 transfer gate, 27 inverter.

Claims (1)

(57) [Claims] 1. A microprocessor in which an operating frequency is divided by a predetermined frequency into an input clock by software and output, the number of wait states inserted to extend a bus cycle is stored. Shift means for shifting the number of wait states from the storage means in accordance with the frequency division number in a direction in which the number of wait states decreases when the frequency division number is large; A bus cycle control means for controlling a wait state to be inserted by an output from the shift means.