JP2570410B2 - Electronic circuit package - Google Patents
Electronic circuit packageInfo
- Publication number
- JP2570410B2 JP2570410B2 JP63325200A JP32520088A JP2570410B2 JP 2570410 B2 JP2570410 B2 JP 2570410B2 JP 63325200 A JP63325200 A JP 63325200A JP 32520088 A JP32520088 A JP 32520088A JP 2570410 B2 JP2570410 B2 JP 2570410B2
- Authority
- JP
- Japan
- Prior art keywords
- electronic circuit
- circuit package
- chip
- housing
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Mounting Of Printed Circuit Boards And The Like (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、電子回路パッケージに関する。Description: TECHNICAL FIELD The present invention relates to an electronic circuit package.
近年、電気機器の高性能化、高機能化の進展に伴な
い、電子部品の高密度実装が要請されており、半導体装
置（シリコンチップ等）を直接、基板に搭載するCOB
（チップオンボード）,COF（チップオンフィルム）を含
め、種々の実装構造が考えられている。In recent years, with the development of higher performance and higher functionality of electrical equipment, high-density mounting of electronic components has been required, and COBs that directly mount semiconductor devices (silicon chips, etc.) on substrates have been demanded.
Various mounting structures are considered, including (chip-on-board) and COF (chip-on-film).
第２図は、従来の電子回路パッケージの一例を示す断
面図である。FIG. 2 is a sectional view showing an example of a conventional electronic circuit package.
第２図に示すように、電気機器の筺体10にボルト７、
ナット11を介して固定されたプリント基板13の上に、パ
ターニングされた配線パッド２にチップ部品14が直接搭
載接続されており、又、ICチップ５は、アイランドパタ
ーン15にマウント材16を介して直接搭載されているICチ
ップ５は配線パッド２にボンディング線17により接続さ
れ、オーバーコート18により損傷から保護されている。As shown in FIG. 2, bolts 7,
A chip component 14 is directly mounted and connected to a patterned wiring pad 2 on a printed board 13 fixed via a nut 11, and the IC chip 5 is attached to an island pattern 15 via a mounting material 16. The directly mounted IC chip 5 is connected to the wiring pad 2 by a bonding wire 17 and is protected from damage by an overcoat 18.
上述した従来の電子回路パッケージは、全てが剛体で
形成されている為、筺体への実装状態で配線基板とチッ
プ部品の熱膨張係数を合致させないと応力集中の発生す
る接続部あるいはICチップにクラックがしばしば発生
し、信頼性上、重大な問題を起こしていた。これは、配
線基板の機能として基板材料の誘電率を低く保つ必要性
があり、この事を満足させたまま、上記熱膨張係数を完
全に合致させる事が困難な事も一因となっている。さら
に本実装構造では、ICチップの放熱性が悪い。近年では
MOSICと言えどもハイパワー，高速化の傾向が著しく、
放熱性が悪い実装状態では、電子回路パッケージの性能
を発揮出来ないという問題点があった。Since the conventional electronic circuit packages described above are all formed of rigid bodies, cracks may occur in the connection parts or IC chips where stress concentration occurs if the thermal expansion coefficients of the wiring board and chip components do not match when mounted on the housing. Often occurred, causing serious reliability problems. This is because it is necessary to keep the dielectric constant of the substrate material low as a function of the wiring substrate, and it is also difficult to completely match the coefficient of thermal expansion while satisfying this. . Furthermore, in this mounting structure, the heat dissipation of the IC chip is poor. in recent years
MOSIC has a remarkable trend of high power and high speed,
There is a problem that the performance of the electronic circuit package cannot be exhibited in a mounting state with poor heat radiation.
本発明の目的は、応力集中を回避し、しかも、ICチッ
プの放熱を確実に行なえる電子回路パッケージを提供す
ることにある。An object of the present invention is to provide an electronic circuit package that can avoid stress concentration and reliably dissipate heat from an IC chip.
本発明の電子回路パッケージは、可撓性を有する配線
基板と、該基板上に筺体への取付可能な構造を有するヒ
ートシンクが一体化して形成された半導体装置がフェー
スダウンボンディングされ、前記可撓性配線基板上に設
けた前記配線基板と筺体間を半固定する為のファスナー
とを有して構成されている。In the electronic circuit package of the present invention, a semiconductor device in which a flexible wiring board and a heat sink having a structure attachable to a housing are integrally formed on the board is face-down bonded, It is configured to have a fastener provided on the wiring board and a fastener for semi-fixing between the housing and the housing.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は、本発明の一実施例を示す断面図である。 FIG. 1 is a sectional view showing one embodiment of the present invention.
第１図に示す様に、ポリイミドフィルムあるいはテフ
ロンフィルム等の低誘電率材料で構成された可撓性配線
基板１の上に設けたCu等の配線パッド２の上に半田等を
介してチップコンデンサ３を直接搭載する。次に、Auあ
るいは半田等のバンプ４を有するICチップ５は裏面に熱
膨張係数の整合をとるのが容易なAg入りエポキシ等の良
熱伝導性接着層６を介してボルト７を埋め込んだベリリ
ヤ等のヒートシンク８と一体化され、ICチップ５はバン
プ４を介し可撓性基板１の配線パッド２に直接フェース
ダウンボンディングされる。次に、ICチップ５はポリイ
ミド等によりポッティング部９を設けて保護し、電子回
路パッケージを構成する。As shown in FIG. 1, a chip capacitor is placed on a wiring pad 2 made of Cu or the like provided on a flexible wiring substrate 1 made of a low dielectric constant material such as a polyimide film or a Teflon film via solder or the like. 3 is mounted directly. Next, the IC chip 5 having the bumps 4 made of Au or solder is provided with a berryll embedded with a bolt 7 via a good heat conductive adhesive layer 6 made of Ag-containing epoxy or the like which can easily match the coefficient of thermal expansion on the back surface. The IC chip 5 is directly face-down bonded to the wiring pad 2 of the flexible substrate 1 via the bump 4. Next, the IC chip 5 is protected by providing a potting portion 9 with polyimide or the like, thereby forming an electronic circuit package.
次に、この電子回路パッケージを実装する場合には、
例えば、Al等で構成され放熱フィンを有し放熱面積の大
きい筺体10に設けた開孔部にヒートシンク８のボルト７
を挿入し、ナット11により締付けて固定し、ヒートシン
ク８と筺体10との両者の界面に於ける熱伝導を確実なも
のにしている。チップ部品の搭載された可撓性配線基板
１は、ボルト7,ナット11の取付部以外は、Al等の金属あ
るいは、ポリイミド等の耐熱性樹脂で構成されたファス
ナー12で配線基板１の可塑性を損う事なく半固定されて
いる。この構造はナット11及びファスナー12を筺体10か
ら離脱させて電子回路パッケージを筺体10から容易に取
りはずす事が可能で検査，修理等が簡便に実行出来る利
点がある。Next, when mounting this electronic circuit package,
For example, the bolt 7 of the heat sink 8 is provided in an opening provided in the housing 10 having a heat radiation fin made of Al or the like and having a large heat radiation area.
Is inserted and tightened and fixed with a nut 11 to ensure heat conduction at the interface between the heat sink 8 and the housing 10. The flexible wiring board 1 on which the chip components are mounted is made of a metal 12 such as Al or a fastener 12 made of a heat-resistant resin such as polyimide, except for the mounting portions of the bolts 7 and the nuts 11, to make the wiring board 1 plastic. Semi-fixed without loss. This structure has an advantage that the electronic circuit package can be easily removed from the housing 10 by detaching the nut 11 and the fastener 12 from the housing 10, and inspection and repair can be easily performed.
以上説明した様に本発明は、可撓性配線基板上に搭載
したヒートシンクを有する半導体装置と配線基板に設け
たファスナーとを設けることにより、実装時に半導体装
置の裏面に構成したヒートシンクを筺体シャシーに取付
けて放熱性に優れた実装が達成出来、かつファスナーに
よる基板と筺体シャシー間の半固定結合は基板の可撓性
を損わない為、従来方法で問題となる応力集中を分散出
来、高密度、高性能、高信頼性、高メンテナンス性を有
する電子回路パッケージを提供出来る効果がある。As described above, the present invention provides a semiconductor device having a heat sink mounted on a flexible wiring substrate and a fastener provided on the wiring substrate, so that the heat sink formed on the back surface of the semiconductor device at the time of mounting can be provided in a chassis. Mounting can achieve mounting with excellent heat dissipation, and the semi-fixed connection between the board and the chassis chassis with fasteners does not impair the flexibility of the board, so stress concentration, which is a problem with the conventional method, can be dispersed, and high density There is an effect that an electronic circuit package having high performance, high reliability, and high maintainability can be provided.
第１図は本発明の一実施例を示す断面図、第２図は従来
の電子回路パッケージの一例を示す断面図である。 １……可撓性配線基板、２……配線パッド、３……チッ
プコンデンサ、４……バンプ、５……ICチップ、６……
接着層、７……ボルド、８……ヒートシンク、９……ポ
ッティング部、10……筺体、11……ナット、12……ファ
スナー、13……プリント基板、14……チップ部品、15…
…アイランドパターン、16……マウント材、17……ボン
ディング線、18……オーバーコート。FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 2 is a sectional view showing an example of a conventional electronic circuit package. 1 ... flexible wiring board, 2 ... wiring pad, 3 ... chip capacitor, 4 ... bump, 5 ... IC chip, 6 ...
Adhesive layer, 7 Bold, 8 Heat sink, 9 Potting section, 10 Housing, 11 Nuts, 12 Fasteners, 13 Printed circuit board, 14 Chip components, 15
... island pattern, 16 ... mounting material, 17 ... bonding wire, 18 ... overcoat.
Claims (1)
に搭載され且つ筺体に取付け可能な構造を有するヒート
シンクを備えた半導体装置と、前記配線基板に設けて前
記配線基板を前記筺体に取付けるためのファスナーとを
有することを特徴とする電子回路パッケージ。A semiconductor device having a flexible wiring board, a heat sink mounted on the wiring board and having a structure attachable to a housing; and a semiconductor device provided on the wiring board and mounting the wiring board on the housing. An electronic circuit package comprising: a fastener for attaching the electronic circuit to the electronic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63325200A JP2570410B2 (en) | 1988-12-22 | 1988-12-22 | Electronic circuit package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63325200A JP2570410B2 (en) | 1988-12-22 | 1988-12-22 | Electronic circuit package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02170494A JPH02170494A (en) | 1990-07-02 |
| JP2570410B2 true JP2570410B2 (en) | 1997-01-08 |
Family
ID=18174138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63325200A Expired - Lifetime JP2570410B2 (en) | 1988-12-22 | 1988-12-22 | Electronic circuit package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2570410B2 (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2595054Y2 (en) * | 1992-12-25 | 1999-05-24 | 株式会社ケーヒン | Radiator for electronic control unit |
| JP3416450B2 (en) * | 1997-03-21 | 2003-06-16 | 三菱電機株式会社 | Power transistor module mounting structure |
| US8238087B2 (en) | 2010-01-06 | 2012-08-07 | Apple Inc. | Display module |
| US8213168B2 (en) | 2010-01-06 | 2012-07-03 | Apple Inc. | Assembly of a display module |
| US8432678B2 (en) | 2010-01-06 | 2013-04-30 | Apple Inc. | Component assembly |
| US7995334B2 (en) | 2010-01-06 | 2011-08-09 | Apple Inc. | Printed circuit board |
| US8345410B2 (en) | 2010-01-06 | 2013-01-01 | Apple Inc. | Handheld computing device |
| EP2557592A1 (en) * | 2010-06-14 | 2013-02-13 | Sharp Kabushiki Kaisha | Electronic device, display device, and television receiver |
| DE102019210710B4 (en) * | 2019-07-19 | 2021-02-11 | Continental Automotive Gmbh | Antenna device for an automobile and an automobile |
-
1988
- 1988-12-22 JP JP63325200A patent/JP2570410B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02170494A (en) | 1990-07-02 |
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