JP2565908B2 - Compound semiconductor device - Google Patents

Description

TECHNICAL FIELD The present invention relates to an improvement of a semiconductor substrate in a compound semiconductor device, and more particularly to a semiconductor device in which a III-V group compound semiconductor layer is formed on the substrate by epitaxial growth.

<Prior Art> Compound semiconductors, particularly III-V group compound semiconductors such as GaAs, have not only superior mobility and selectivity of band gap but also direct transitions as compared with conventional silicon semiconductors. Therefore, it has attracted attention in recent years as a material for optoelectronic devices such as solar cells.

When a semiconductor device is constructed using this kind of material, from the viewpoint of material economy and weight reduction of the device, at least the surface side that is required to function as a semiconductor is required without forming the entire semiconductor substrate with a compound. It has been proposed to make only a compound semiconductor layer. That is, using silicon as a substrate, a GaAs-based compound semiconductor layer is deposited on this surface,
The deposited layer is subjected to necessary processing for semiconductor elements such as PN junctions to manufacture light emitting devices and integrated circuits.

Where, silicon and GaAs have lattice constants and thermal expansion coefficients of 4
%, 50% different, so high quality G on silicon substrate
In order to deposit aAs, it is necessary to overcome problems such as generation of lattice defects due to the difference in lattice constant and thermal expansion coefficient.

For such problems, on a Si substrate, for example, at low temperature
Attempts have been made to first deposit a very thin GaAs buffer layer of about 100 Å, then perform epitaxial growth at normal growth temperature, and to prevent the propagation of misfit dislocations by using a superlattice. It was Further, various methods for reducing the dislocation density of the epitaxially grown layer obtained by these methods have been tried, and improvement of these growth conditions has made it possible to grow high-quality GaAs.

<Problems to be Solved by the Invention> However, it has been experimentally confirmed that when GaAs is deposited to a thickness of about 3 μm or more, cracks are generated in the GaAs growth layer due to the difference in thermal expansion coefficient.

Next, the effect of the above crack when a PN junction is formed on the GaAs growth layer will be described.

FIG. 7 shows P-GaAs after depositing n-GaAs (S-doped, carrier concentration of about 1 × 10 ¹⁷ / cm ³ ) to a predetermined thickness on a Si substrate.
(Zn-doped, carrier concentration about 2 × 10 ¹⁸ / cm ³ ) about 0.3μ
It shows the dependency of the reverse saturation current value of the pn junction formed by m deposition on the growth layer thickness.

It was found that the reverse saturation current value decreased as the total grown layer thickness increased, and the crystallinity of the GaAs grown layer was significantly improved.

However, when the thickness of the grown layer was about 3.5 μm or more, cracks were generated and a rapid increase in the reverse saturation current value was observed (indicated by X in FIG. 7). It is considered that this is because migration of the electrode metal material occurs through the cracks and a local short circuit of the pn junction occurs. When a device that carries current in the direction perpendicular to the substrate, such as a solar cell, is manufactured using a GaAs growth layer containing such cracks, the solar cell's open circuit voltage and fill factor significantly deteriorate. Occurs, and the desired conversion efficiency cannot be achieved.

As described above, at present, obtaining a high-quality GaAs growth layer on a Si substrate and obtaining a growth layer with no cracks require conditions that contradict the GaAs epitaxial growth. It can be said that the degree of freedom of the GaAs compound semiconductor device formed above is greatly limited.

The present invention was devised in view of the above points, and a high quality semiconductor layer can be obtained even if there is a large difference in physical properties such as thermal expansion and lattice constant between the compound semiconductor layer and its substrate. It is an object of the present invention to provide a compound semiconductor device maintained at

<Means for Solving Problems> In order to achieve the above-mentioned object, the present invention provides a compound semiconductor device in which a compound semiconductor layer is deposited on a substrate, and a crack generated in the compound semiconductor layer is generated. In the embodiment of the present invention, in order to realize the structure as described above, the Si substrate is composed of an amorphous semiconductor or a polycrystalline semiconductor material having a fine grain size. A high-quality GaAs growth layer with a thickness greater than the critical thickness for cracking is deposited on top of it, and the temperature is once lowered to around room temperature to generate cracks, and then the temperature is raised again to obtain a polycrystalline structure of amorphous or fine grain size. By filling the cracks with GaAs, it is possible to obtain a compound semiconductor device in which any inconvenience as a semiconductor device due to migration of electrode metal or the like is prevented.

<Operation> Even if a crack is generated in the compound semiconductor layer deposited on the substrate due to the difference in thermal expansion coefficient between the two, the generated crack is filled with a semiconductor having an amorphous or polycrystalline structure with a minute grain size. Therefore, the electrode material formed on the surface does not short-circuit a device such as a PN junction formed in the compound semiconductor layer in the thickness direction, and a solar cell using such a compound semiconductor layer. Even if a device such as a light emitting diode is manufactured, its operation is not impaired.

<Embodiment> An embodiment of the present invention will be described below in detail with reference to the manufacturing steps with reference to the drawings.

FIG. 1 shows a GaAs layer 3 formed on a Si substrate 1 via a buffer layer 2 of Ge, GaP, GaAlAs or the like by a crystal growth method such as MOCVD or MBE.
FIG. 3 is a diagram showing a cross section of a structure of a semiconductor substrate in which is deposited to a thickness of 3.5 μm or more. In this case, the buffer layer 2 can be omitted by appropriately selecting the GaAs epitaxial growth conditions, and the GaAs layer 3 can be immediately deposited on the Si substrate 1 to form the buffer layer 2. Typical temperature during deposition of GaAs layer 3 is 700 ° C
Is.

After completion of GaAs deposition, cracks 4 caused by the difference in thermal expansion coefficient between Si and GaAs were formed in the GaAs layer 3 when the temperature was lowered to near room temperature.
Occurs a lot. Some cracks 4 penetrate the entire GaAs deposited layer 3 and some cracks stop halfway. Some extend to the buffer layer 2 and some do not.
An example of an enlarged view of the portion where the crack 4 is generated is shown in FIG.

Then, once the temperature is lowered to around room temperature, the temperature is raised again to about 400 ° C in the same reaction furnace, and for example, GaAlAs5 is 0.05μ.
about m. Hereinafter, this layer is referred to as a low temperature deposition layer.

The low-temperature deposition layer 5 has an amorphous structure or a polycrystalline structure having a small grain size.

As shown in FIG. 3, the low-temperature deposition layer 5 is formed not only on the surface of the GaAs layer 3 but also inside the crack 4, and has an effect of filling the recess of the crack 4.

After that, even when the temperature is lowered to room temperature again, the low-temperature deposition layer 5 filling the depressions of the cracks 4 relaxes the stress generated due to the difference in the thermal expansion coefficient between GaAs and Si, and no new cracks are observed. .

The semiconductor material forming the low temperature deposition layer 5 is GaAlAs.
However, the material of the buffer layer 2 such as Ge and GaP, or GaAs may be used. Further, impurity doping may be performed as necessary. Further, the cycle of GaAs deposition temperature room temperature low temperature deposition layer formation → room temperature may be repeated a plurality of times.

FIG. 4 and FIG. 5 respectively show examples in the case of forming the metal layer 6 on the surface of the semiconductor substrate manufactured by the above process.

FIG. 4 shows the case where the metal layer 6 is formed on the low temperature deposition layer 5, and FIG. 5 shows the Ga other than the metal layer forming portion.
The case where the low temperature deposition layer 5 on the As surface is removed by selective etching is shown, and the low temperature growth layer and the metal layer can be processed according to the desired device structure.

FIG. 6 shows a cross section of a GaAs solar cell formed on a Si substrate as an example of a specific semiconductor device manufactured by the above steps.

In FIG. 6, n− is formed on the Si substrate 1 via the buffer layer 2.
The GaAs layer 3a, the p-GaAs layer 3b, and the p-GaAlAs layer 3c are deposited with a metal thickness of 3 μm or more, and the generated cracks 4 are filled with the p-GaAs low temperature deposition layer 5a. The light-receiving surface side is the light-receiving surface side electrode
The low temperature deposition layer other than the lower part of 6a is removed by selective etching. The back surface side electrode 7 is formed on the entire back surface side.

In the above example, Si is used as the substrate and GaA is used as the compound semiconductor layer.
Although s has been described as an example, the present invention can be similarly applied to other substrate-semiconductor material combinations having a large difference in thermal expansion coefficient.

<Effect of the Invention> As described above, according to the present invention, when another material is used as a substrate and a compound semiconductor layer is epitaxially grown thereon to form a substrate of a semiconductor device, even if the compound semiconductor layer and the substrate are Even if there is a large difference in physical properties such as thermal expansion and lattice constant, the semiconductor layer can be kept in high quality, the manufacturing of the compound semiconductor device becomes very easy, and the selection range of materials becomes wide, A compound semiconductor device excellent in economic efficiency can be obtained.

[Brief description of drawings]

1 to 5 are sectional views showing a manufacturing process of a compound semiconductor device as one embodiment of the present invention, and FIG. 6 is a sectional view showing a structure of a solar cell as a more specific embodiment, FIG. 7 is a diagram showing experimental data specifically showing the problems to be solved by the present invention. 1 ... Si substrate, 2 ... buffer layer, 3 ... GaAs growth layer, 3a ...
... n-GaAs growth layer, 3b ... p-GaAs growth layer, 3c ... p-
GaAlAs growth layer, 4 ... crack, 5 ... low temperature deposition layer, 5a
...... p-GaAs low temperature deposition layer, 6 …… metal layer, 6a …… light receiving surface side electrode, 7 …… back surface electrode.

Claims (6)

(57) [Claims] 1. A semiconductor device comprising a compound semiconductor layer deposited on a substrate, wherein the cracks occurring in the compound semiconductor layer are filled with a semiconductor material having an amorphous or polycrystalline structure of fine grain size. A compound semiconductor device comprising: 2. The amorphous or polycrystalline semiconductor material having a fine grain size is deposited at a temperature lower than the temperature at which the compound semiconductor layer is deposited in the same deposition apparatus after the deposition of the compound semiconductor layer. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is formed by: 3. The substrate according to claim 1 or 2, wherein the substrate is a Si substrate, and a III-V group compound semiconductor layer having a thickness of 3 μm or more is deposited on the Si substrate. A compound semiconductor device according to the item. 4. The compound semiconductor device according to claim 1, 2, or 3, wherein a part of said compound semiconductor layer is made of GaAs. 5. The compound semiconductor device according to claim 3 or 4, wherein the compound semiconductor layer is formed by forming a solar cell element. 6. The compound semiconductor device according to claim 3, wherein the compound semiconductor layer forms a light emitting diode.