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JP2565362B2 - Method for manufacturing multilayer wiring board - Google Patents

Method for manufacturing multilayer wiring board

Info

Publication number
JP2565362B2
JP2565362B2 JP62333551A JP33355187A JP2565362B2 JP 2565362 B2 JP2565362 B2 JP 2565362B2 JP 62333551 A JP62333551 A JP 62333551A JP 33355187 A JP33355187 A JP 33355187A JP 2565362 B2 JP2565362 B2 JP 2565362B2
Authority
JP
Japan
Prior art keywords
layer
insulating film
metal layer
thickness
via hole
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP62333551A
Other languages
Japanese (ja)
Other versions
JPH01173784A (en
Inventor
原子太郎 川村
康稔 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP62333551A priority Critical patent/JP2565362B2/en
Publication of JPH01173784A publication Critical patent/JPH01173784A/en
Application granted granted Critical
Publication of JP2565362B2 publication Critical patent/JP2565362B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は多層配線基板の製造方法に関するものであ
る。
The present invention relates to a method for manufacturing a multilayer wiring board.

(従来の技術) 従来、半導体集積回路素子等を搭載する多層配線基板
はアルミナセラミックス等の電気絶縁材料から成る基体
と該基体の表面及び内部に埋設、焼付けられているタン
グステン(W)、モリブデン(Mo)等の高融点金属より
成る電気配線用導体層とにより構成されている。
(Prior Art) Conventionally, a multilayer wiring board on which a semiconductor integrated circuit element or the like is mounted has a base made of an electrically insulating material such as alumina ceramics, and tungsten (W) and molybdenum (embedded in the surface and inside of the base and baked). Mo) etc. and a conductor layer for electric wiring made of a high melting point metal.

かかる従来の多層配線基板は通常、電気絶縁性に優れ
たアルミナ(Al2O3)等のセラミックスから成るグリー
ンシートを使用し、その表面にタングステン(W)、モ
リブデン(Mo)、マンガン(Mn)等の高融点金属から成
る導体ペーストをスクリーン印刷法により所定のパター
ンに厚膜印刷するとともにこれを複数枚積層し、しかる
後、前記積層したものを約1500℃の温度で焼成すること
によって形成されている。
Such a conventional multilayer wiring board usually uses a green sheet made of ceramics such as alumina (Al 2 O 3 ) having excellent electric insulation property, and has tungsten (W), molybdenum (Mo), manganese (Mn) on its surface. It is formed by printing a thick film of a conductive paste composed of a high melting point metal such as a screen printing method into a predetermined pattern and laminating a plurality of these, and then firing the laminated ones at a temperature of about 1500 ° C. ing.

しかし乍ら、近年に至り、ハイブリッドIC及びLSI等
の半導体集積回路素子の高密度化・高集積化の急激な進
歩に伴い、該LSI等を実装する多層配線基板もその配線
密度を高めることが要求され、従来の多層配線基板では
電気配線用導体層が厚膜により形成されていることから
配線用導体層の微細化が難しく、かつ全体の厚みが厚く
なって多層化が困難となり、十分な高密度化が達成でき
ないという問題があった。
However, in recent years, with the rapid progress in high density and high integration of semiconductor integrated circuit devices such as hybrid ICs and LSIs, it is possible to increase the wiring density of a multilayer wiring board on which the LSIs are mounted. In the conventional multilayer wiring board, it is difficult to miniaturize the wiring conductor layer because the conductor layer for electric wiring is formed of a thick film in the conventional multilayer wiring board, and it becomes difficult to form a multilayer because the entire thickness becomes thick. There was a problem that high density could not be achieved.

そこで上記従来の多層配線基板の欠点を解消するため
に回路配線としての電気配線用導体層を厚膜方法に代え
て蒸着法、スパッタリング法等の気相成長法による薄膜
形成技術を用いて形成し、かつ各電気配線用導体層の絶
縁を高分子材料をスピンコーティング法等により塗布
し、絶縁膜を形成することによって行い、これによって
導体層を薄膜化、微細化させ電気配線用導体層を高密度
となした多層配線基板が提案されている。
Therefore, in order to solve the above-mentioned drawbacks of the conventional multilayer wiring board, the conductor layer for electric wiring as the circuit wiring is formed by using a thin film forming technique by a vapor deposition method such as a vapor deposition method or a sputtering method instead of the thick film method. In addition, the insulation of each conductor layer for electrical wiring is performed by applying a polymer material by a spin coating method or the like to form an insulating film, which makes the conductor layer thin and fine and enhances the conductor layer for electrical wiring. A multilayer wiring board having a high density has been proposed.

(発明が解決しようとする問題点) しかしながら、前記多層配線基板では高分子材料から
成る絶縁膜に設けたビアホール側面に導体層を被着さ
せ、該側面導体層により絶縁膜の上下面に位置する電気
配線用導体層を接続する場合、前記絶縁膜に設けたビア
ホールの側面には気相成長法では導体層を層着し難く導
体層の被着性が極めて悪い。そのためMIL-STD 883C 101
0規格に基づく熱衝撃試験等の加速試験を行った場合、
絶縁膜上面の導体層とビアホール壁面に被着させた導体
層との接続抵抗率が1%以上となり、全抵抗変化率が数
十%にも及び、その結果、電圧レベルの変化が大きく、
上記ビアホールの側面における接続信頼性が著しく悪
い。これは前記ビアホール壁面における導体層の層厚が
絶縁膜上面の導体層の層厚に比べて薄いことから、半導
体集積回路素子を多層配線基板に取着する際の加熱等に
より絶縁膜が膨張し、前記ビアホール壁面の厚み方向に
引張応力を生じた時に層厚の薄い前記ビアホール壁面の
導体層が破断するためと考えられる。
(Problems to be Solved by the Invention) However, in the above-mentioned multilayer wiring board, a conductor layer is adhered to the side surface of the via hole provided in the insulating film made of a polymer material, and the side surface conductor layer positions the insulating film above and below the insulating film. When connecting a conductor layer for electric wiring, it is difficult to deposit the conductor layer on the side surface of the via hole provided in the insulating film by the vapor phase growth method, and the adherence of the conductor layer is extremely poor. Therefore MIL-STD 883C 101
When an accelerated test such as a thermal shock test based on 0 standard is performed,
The connection resistivity between the conductor layer on the upper surface of the insulating film and the conductor layer deposited on the wall surface of the via hole is 1% or more, the rate of change in total resistance reaches several tens of percent, and as a result, the change in voltage level is large.
The connection reliability on the side surface of the via hole is extremely poor. This is because the thickness of the conductor layer on the wall surface of the via hole is smaller than the layer thickness of the conductor layer on the upper surface of the insulating film, so that the insulating film expands due to heating when attaching the semiconductor integrated circuit element to the multilayer wiring board. It is considered that, when a tensile stress is generated in the thickness direction of the wall surface of the via hole, the conductor layer on the wall surface of the via hole having a small layer thickness is broken.

(発明の目的) 本発明者等は上記欠点に鑑み種々の実験の結果絶縁膜
の上面と該絶縁膜に設けたビアホールの壁面とに気相成
長法により下地金属層を層着させるとともに該下地金属
層上に電解メッキ法により導電層を被着させ、電気配線
用導体層を下地金属層と導電層の2層構造となすと、絶
縁膜の上面とビアホールの壁面とに設けた電気配線用導
体層との接続が強固なものとなり、これによって熱衝撃
試験等の加速試験に対しても上記段差部における接続信
頼性を極めて優れたものとなることを知見した。
(Object of the Invention) In view of the above-mentioned drawbacks, the present inventors have conducted various experiments and, as a result of vapor phase epitaxy, deposit a base metal layer on the upper surface of an insulating film and the wall surface of a via hole provided in the insulating film. When a conductive layer is deposited on the metal layer by electrolytic plating and the conductor layer for electric wiring has a two-layer structure of a base metal layer and a conductive layer, for electric wiring provided on the upper surface of the insulating film and the wall surface of the via hole. It has been found that the connection with the conductor layer becomes strong, and thereby the connection reliability at the step portion is extremely excellent even in an accelerated test such as a thermal shock test.

本発明は上記知見に基づき絶縁膜上面と該絶縁膜に設
けたビアホール壁面とに設けた電気配線用導体層の接続
を強固なものとなし、両者の接続信頼性を極めて高いも
のとなした多層配線基板を提供することにある。
Based on the above findings, the present invention makes the connection of the conductor layer for electrical wiring provided on the upper surface of the insulating film and the wall surface of the via hole provided in the insulating film strong, and makes the connection reliability of both layers extremely high. To provide a wiring board.

(問題点を解決するための手段) 本発明の多層配線基板の製造方法は、上面に配線導体を
有する絶縁基体上に、ビアホールを有するポリイミド樹
脂、シリコーン樹脂、ポリブタジエン樹脂、ポリアミド
イミド樹脂、ポリ四弗化エチレン樹脂のいずれかの高分
子材料から成る絶縁膜を成膜させしかる後、前記絶縁膜
の上面及びビアホール壁面に気相成長法によりチタン、
モリブデンの少なくとも1種と銅の複数層から成る下地
金属層を層着させるとともに該下地金属層上に電解メッ
キ法により銅から成る導電層を被着させ、下地金属層と
導電層の2層構造を有する電気配線用導体層を形成する
ことを特徴とするものである。
(Means for Solving the Problems) A method for manufacturing a multilayer wiring board according to the present invention comprises a polyimide resin having a via hole, a silicone resin, a polybutadiene resin, a polyamideimide resin, and a polytetrafluoroethylene resin on an insulating substrate having a wiring conductor on the upper surface. After forming an insulating film made of any polymer material of fluoroethylene resin, titanium is formed on the upper surface of the insulating film and the wall surface of the via hole by vapor phase epitaxy,
A base metal layer composed of at least one type of molybdenum and a plurality of layers of copper is deposited, and a conductive layer made of copper is deposited on the base metal layer by electrolytic plating to form a two-layer structure of the base metal layer and the conductive layer. And forming a conductor layer for electric wiring having.

(実施例) 次に本発明を添付図面に示す実施例に基づき詳細に説
明する。
(Example) Next, the present invention will be described in detail based on an example shown in the accompanying drawings.

第1図は本発明の製造方法を説明するための多層配線
基板の要部拡大断面図であり、1はアルミナセラミック
ス等から絶縁基体である。
FIG. 1 is an enlarged cross-sectional view of an essential part of a multilayer wiring board for explaining the manufacturing method of the present invention, and 1 is an insulating base made of alumina ceramics or the like.

前記絶縁基体1は、例えばアルミナ(Al2O3)、シリ
カ(SiO2)等のセラミック原料粉末に適当な溶剤、溶媒
を添加混合して泥漿物を作り、これを従来周知のドクタ
ーブレード法によりシート状と成すとともに高温で焼成
することにより製作される。
The insulating substrate 1 is prepared by adding and mixing an appropriate solvent and a solvent to a ceramic raw material powder such as alumina (Al 2 O 3 ) or silica (SiO 2 ) to prepare a slurry, which is prepared by a conventionally known doctor blade method. It is manufactured by forming it into a sheet and baking it at a high temperature.

前記絶縁基体1の上面には、従来周知のイオンプレー
ティング法、スパッタリング法等の気相成長法により配
線導体2が形成され、更にその上部には高分子材料をス
ピンコーティングし、加熱処理を行うことによって成膜
された絶縁膜3が被着形成されている。前記絶縁膜3に
使用される高分子材料としてはポリイミド樹脂、シリコ
ーン樹脂、ポリプタジエン樹脂、ポリアミドイミド樹
脂、ポリ四弗化エチレン樹脂が好適に使用される。
A wiring conductor 2 is formed on the upper surface of the insulating substrate 1 by a vapor phase growth method such as a well-known ion plating method and a sputtering method. Further, a polymer material is spin-coated on the wiring conductor 2 and heat treatment is performed. The insulating film 3 thus formed is deposited. Polyimide resin, silicone resin, polyptadiene resin, polyamideimide resin, and polytetrafluoroethylene resin are preferably used as the polymer material used for the insulating film 3.

次に、前記絶縁膜3上に同様の気相成長法によりシリ
カまたはチタン等の薄膜を成膜するとともにフォトリソ
グラフィにより導体パターン形成し、該パターンをマス
クとして反応性イオンエッチング等により絶縁膜3を選
択的に除去してビアホール4を形成する。
Next, a thin film of silica or titanium is formed on the insulating film 3 by the same vapor phase growth method, and a conductor pattern is formed by photolithography, and the insulating film 3 is formed by reactive ion etching or the like using the pattern as a mask. It is selectively removed to form a via hole 4.

そして、次に前記ビアホール4を有する絶縁膜上に上
記と同様の気相成長法によりチタン、モリブデン等から
成る第1の下地金属層5と銅から成る第2の下地金属層
6を順次被着する。
Then, a first base metal layer 5 made of titanium, molybdenum or the like and a second base metal layer 6 made of copper are sequentially deposited on the insulating film having the via holes 4 by the same vapor deposition method as described above. To do.

そして最後に、前記第2の下地金属層6の上に電解メ
ッキ法により銅の導電層7を被着形成させ、これによっ
て製品として多層配線基板が完成する。
Finally, a copper conductive layer 7 is deposited on the second base metal layer 6 by electrolytic plating to complete a multilayer wiring board as a product.

即ち、本発明においては回路配線としての電気配線用
導体層を気相成長法により被着される下地金属層5,6と
電解メッキ法により層着される導電層7の2層構造とし
たことから、絶縁膜のビアホール壁面に位置する導体層
はその層厚が大となってビアホール壁面に強固に接合
し、その結果、絶縁膜3上面とビアホール壁面とに被着
させたそれぞれの導電層の接続を確実なものとなすこと
ができる。
That is, in the present invention, the conductor layer for electric wiring as the circuit wiring has a two-layer structure of the underlying metal layers 5 and 6 deposited by vapor deposition and the conductive layer 7 deposited by electrolytic plating. Therefore, the conductor layer located on the wall surface of the via hole of the insulating film has a large layer thickness and is strongly bonded to the wall surface of the via hole, and as a result, the conductive layer of each conductive layer adhered to the upper surface of the insulating film 3 and the wall surface of the via hole is The connection can be made reliable.

また前記電気配線用導体層の層厚をビアホールの壁面
において、絶縁膜の膜厚の1/10以上とすると半導体集積
回路素子を実装する際等において熱が印加され、絶縁膜
が膨張し、ビアホール側面の導体層に引張応力が生じた
としても該導体層は破断することはない。
When the layer thickness of the conductor layer for electrical wiring is 1/10 or more of the thickness of the insulating film on the wall surface of the via hole, heat is applied when the semiconductor integrated circuit element is mounted, etc., and the insulating film expands to cause the via hole. Even if tensile stress occurs in the conductor layer on the side surface, the conductor layer does not break.

尚、絶縁膜チタン、モリブデンの少なくとも1種から
成る第1の下地金属層5はその厚さが0.03μm未満とな
ると半導体集積回路素子を実装する際等に熱が印加され
ると、該第1の下地金属層5とその上に層着される銅か
ら成る第2の下地金属層6との間に相互拡散が起こり、
前記チタン、モリブデンの少なくとも1種から成る第1
の下地金属層5が絶縁膜に直接接触して密着不良を発生
し、接続抵抗変化率が大となる傾向にある。また前記層
厚が0.5μmを越えると第1の下地金属層5の内部応力
が高くなり、絶縁膜に被着させた際、前記内部応力によ
って絶縁膜にクラックを発生させ、絶縁抵抗や密着強度
が劣化する傾向にある。そのためチタン、モリブデンの
少なくとも1種から成る第1の下地金属層はその層厚を
0.03〜0.50μmの範囲とすることが好ましい。
If the thickness of the first base metal layer 5 made of at least one of the insulating film titanium and molybdenum is less than 0.03 μm, when heat is applied when mounting a semiconductor integrated circuit element, the first base metal layer 5 is Interdiffusion occurs between the underlayer metal layer 5 and the second underlayer metal layer 6 made of copper deposited on the underlayer metal layer 5 of
First comprising at least one of titanium and molybdenum
There is a tendency that the underlying metal layer 5 directly contacts the insulating film to cause poor adhesion and the rate of change in connection resistance increases. Further, when the layer thickness exceeds 0.5 μm, the internal stress of the first base metal layer 5 becomes high, and when applied to the insulating film, the internal stress causes cracks in the insulating film, resulting in insulation resistance and adhesion strength. Tend to deteriorate. Therefore, the thickness of the first base metal layer composed of at least one of titanium and molybdenum
It is preferably in the range of 0.03 to 0.50 μm.

一方、銅から成る第2の下地金属層6はその層厚が0.
1μm未満の場合には、その上面に後で電解メッキ法に
より導電層を層着させる際、その導電層にムラが生じ、
ビアホールの壁面における被覆性が悪くなる傾向にあ
る。また層厚が2.0μmを越える場合には第2の下地金
属層6の内部応力が高くなり、前記第1の下地金属層5
と同様、絶縁膜にクラックを発生させてしまう傾向にあ
る。そのため第2の下地金属層6はその層厚を0.1〜2.0
μmの範囲とすることが好ましい。
On the other hand, the second base metal layer 6 made of copper has a layer thickness of 0.
When the thickness is less than 1 μm, unevenness occurs in the conductive layer when the conductive layer is deposited on the upper surface later by electrolytic plating.
The coverage on the wall surface of the via hole tends to deteriorate. Further, when the layer thickness exceeds 2.0 μm, the internal stress of the second underlayer metal layer 6 becomes high, and the first underlayer metal layer 5 is
Similarly to the above, there is a tendency that cracks are generated in the insulating film. Therefore, the second base metal layer 6 has a layer thickness of 0.1 to 2.0.
It is preferably in the range of μm.

また、銅から成る導電層はその層厚が1μm未満の場
合、ビアホール等の段差部における接続信頼性が低下
し、逆に10μmを越えると導電層の内部応力が高くなっ
て絶縁膜にクラックを発生させてしまう傾向にあり、そ
のため導電層はその厚みを1〜10μmの範囲とすること
が望ましい。
When the thickness of the conductive layer made of copper is less than 1 μm, the connection reliability at the stepped portion such as a via hole is deteriorated. On the contrary, when it exceeds 10 μm, the internal stress of the conductive layer becomes high and cracks occur in the insulating film. Therefore, the conductive layer preferably has a thickness in the range of 1 to 10 μm.

以上、詳述したように本発明はビアホールの壁面に回
路配線としての電気配線用導体層を形成して成る多層配
線基板の製造方法として頗る有用である。
As described above in detail, the present invention is extremely useful as a method for manufacturing a multilayer wiring board in which a conductor layer for electric wiring as circuit wiring is formed on the wall surface of a via hole.

上述した本発明の顕著な利点は以下に示す実験例及び
比較例により容易に認識される。
The above-mentioned remarkable advantages of the present invention can be easily recognized by the following experimental examples and comparative examples.

実施例1 タングステンまたはモリブデン等から成る配線導体を
設けたアルミナ質セラミックスから成るセラミック基板
上に、ビアホールを有するポリイミド樹脂から成る膜厚
25μmの絶縁膜を形成し、該絶縁膜上に気相成長法によ
りモリブデンから成る第1の下地金属層を層厚0.2μ
m、次で銅から成る第2の下地金属層を層厚1.0μm成
膜し、更にその上に電解銅メッキ法により銅の導電層を
層厚2μm被着した試料を100個用意した。これらをMIL
-STD 883C 1010規格に基づき−65℃と150℃にそれぞれ
5分間保持する熱衝撃を30回加え、該熱衝撃試験前のビ
アホールの上下層間の抵抗値に対する熱衝撃試験後の抵
抗値の変化率を求めたところの変化率は1%以下であ
り、導体層の破断は皆無であった。
Example 1 A film thickness made of a polyimide resin having a via hole on a ceramic substrate made of alumina ceramics provided with a wiring conductor made of tungsten or molybdenum.
A 25 μm insulating film is formed, and a first base metal layer made of molybdenum is formed on the insulating film by a vapor phase growth method to a thickness of 0.2 μm.
Then, a second base metal layer made of copper and having a layer thickness of 1.0 μm was formed, and a copper conductive layer was further deposited thereon by electrolytic copper plating to prepare a sample having 100 μm in thickness. These MIL
-Based on STD 883C 1010 standard, heat shock of 5 minutes each at -65 ° C and 150 ° C is applied 30 times, and the rate of change of resistance value after the thermal shock test with respect to the resistance value between the upper and lower layers of the via hole before the thermal shock test. The change rate was 1% or less, and there was no breakage of the conductor layer.

実施例2 実施例1と同様の方法により、シリコーン樹脂から成
る膜厚25μmの絶縁膜上にモリブデンから成る第1の下
地金属層を層厚0.2μm、銅から成る第2の下地金属層
を層厚1.0μmに順次被着させ、その上に銅の導電層を
電解メッキにより層厚2μmに層着した試料を50個用意
し、実施例1と同様の方法により抵抗の変化率を求め
た。
Example 2 By the same method as in Example 1, a first base metal layer made of molybdenum and a second base metal layer made of copper were formed on the insulating film made of silicone resin and having a film thickness of 25 μm with a layer thickness of 0.2 μm. Fifty samples, each having a thickness of 1.0 μm and sequentially deposited with a copper conductive layer by electroplating to a layer thickness of 2 μm, were prepared, and the rate of change in resistance was determined by the same method as in Example 1.

その結果は抵抗の変化率は1%以下であり、且つ導電
層の破断は皆無であった。
As a result, the rate of change in resistance was 1% or less, and the conductive layer was not broken at all.

実施例3 実施例1と同様の方法により、ポリアミドイミド樹脂
から成る膜厚25μmの絶縁膜上にモリブデンから成る第
1の下地金属層を層厚0.2μmに、銅から成る第2の下
地金属層を層厚1.0μmに順次被着し、その上に銅の導
電層を電解メッキにより層厚2μmに層着した試料を50
個用意し、実験例1と同様の方法により抵抗の変化率を
求めた。
Example 3 By the same method as in Example 1, a first base metal layer made of molybdenum was formed on an insulating film made of polyamideimide resin having a thickness of 25 μm to a thickness of 0.2 μm, and a second base metal layer made of copper was made. Samples were sequentially deposited to a layer thickness of 1.0 μm, and a copper conductive layer was deposited thereon to a layer thickness of 2 μm by electrolytic plating.
Individual pieces were prepared and the rate of change in resistance was determined by the same method as in Experimental Example 1.

その結果は抵抗の変化率は1%以下であり、且つ導電
層の破断は皆無であった。
As a result, the rate of change in resistance was 1% or less, and the conductive layer was not broken at all.

実施例4 実施例1と同様の方法により、ポリブタジエン樹脂か
ら成る膜厚25μmの絶縁膜上にチタンから成る第1の下
地金属層を層厚0.2μmに、銅から成る第2の下地金属
層を層厚1.0μmに順次被着し、その上に銅の導電層を
電解メッキにより層厚2μmに層着した試料を50個用意
し、実施例1と同様の方法により抵抗の変化率を求め
た。
Example 4 By the same method as in Example 1, a first base metal layer made of titanium was formed on a 25 μm-thick insulating film made of polybutadiene resin to a thickness of 0.2 μm, and a second base metal layer made of copper was formed. Fifty samples were prepared by sequentially depositing a layer thickness of 1.0 μm and then depositing a copper conductive layer on the layer thickness of 2 μm by electrolytic plating. The rate of change in resistance was determined by the same method as in Example 1. .

その結果は抵抗の変化率は1%以下であり、且つ導電
層の破断は皆無であった。
As a result, the rate of change in resistance was 1% or less, and the conductive layer was not broken at all.

実施例5 実施例1と同様の方法により、ポリ四弗化エチレンか
ら成る膜厚25μmの絶縁膜上にチタンから成る第1の下
地金属層を層厚0.2μmに、銅から成る第2の下地金属
層を層厚1.0μmに順次被着し、その上に銅の導電層を
電解メッキにより層厚2μmに層着した試料を50個用意
し、実施例1と同様の方法により抵抗の変化率を求め
た。
Example 5 By the same method as in Example 1, a first base metal layer made of titanium was formed on an insulating film made of polytetrafluoroethylene having a thickness of 25 μm to a thickness of 0.2 μm, and a second base made of copper was made. Fifty samples were prepared by sequentially depositing a metal layer to a layer thickness of 1.0 μm and depositing a copper conductive layer on the layer to a layer thickness of 2 μm by electrolytic plating. The rate of change in resistance was determined by the same method as in Example 1. I asked.

その結果は抵抗の変化率は1%以下であり、且つ導電
層の破断は皆無であった。
As a result, the rate of change in resistance was 1% or less, and the conductive layer was not broken at all.

比較例 ダングステンまたはモリブデン等から成る配線導体を
設けたアルミナ質セラミックスから成るセラミック基板
上に、ビアホールを有するポリイミド樹脂から成る膜厚
25μmの絶縁膜を形成し、該絶縁膜上に気相成長法によ
りモリブデンから成る下地金属層を層厚0.2μm被着し
た後、同様の気相成長法により銅から成る導電層を層厚
3μm被着させた試料100個を用意した。これらを実施
例1と同様の方法により抵抗の変化率を調べたところ抵
抗変化率3%以上となり、また導体層には破断が認めら
れるものもあった。
Comparative example Film thickness made of polyimide resin with via holes on a ceramic substrate made of alumina ceramics with wiring conductors made of dangsten or molybdenum
A 25 μm insulating film is formed, a molybdenum base metal layer of 0.2 μm is deposited on the insulating film by vapor deposition, and a conductive layer of copper is deposited by 3 μm by the same vapor deposition method. 100 adhered samples were prepared. When the rate of change in resistance of these was examined by the same method as in Example 1, the rate of change in resistance was 3% or more, and some conductor layers were ruptured.

(発明の効果) 以上詳述した通り、本発明の多層配線基板の製造方法
によれば、絶縁膜上面及び該絶縁膜に設けられたビアホ
ールの壁面に被着される電配線用導体層が気相成長法に
よる下地金属層と電解メッキよる導電層との2層構造を
成すことからビアホール壁面における導体層の厚みが大
となり、その結果、ビアホールの壁面における導体層の
接合を強固とし、接続信頼性が高く、且つ電気配線用導
体層の破断を皆無となすことができる。
(Effects of the Invention) As described in detail above, according to the method for manufacturing a multilayer wiring board of the present invention, the conductor layer for electrical wiring that is adhered to the upper surface of the insulating film and the wall surface of the via hole provided in the insulating film is formed. Since the two-layer structure of the underlying metal layer by the phase growth method and the conductive layer by electroplating is formed, the thickness of the conductor layer on the wall surface of the via hole becomes large, and as a result, the conductor layer is firmly bonded on the wall surface of the via hole, and the connection reliability In addition, it is possible to prevent breakage of the conductor layer for electric wiring.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の多層配線基板の製造方法を説明するた
めの多層配線基板の要部拡大断面図である。 1……絶縁基体、2……配線導体 3……絶縁膜、4……ビアホール 5……第1の下地金属層 6……第2の下地金属層 7……導電層 8……電気配線用導体層
FIG. 1 is an enlarged sectional view of an essential part of a multilayer wiring board for explaining a method for manufacturing a multilayer wiring board according to the present invention. 1 ... Insulating substrate, 2 ... Wiring conductor, 3 ... Insulating film, 4 ... Via hole, 5 ... First underlying metal layer, 6 ... Second underlying metal layer, 7 ... Conductive layer, 8 ... For electrical wiring Conductor layer

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】上面に配線導体を有する絶縁基体上に、ビ
アホールを有する絶縁膜を成膜させ、しかる後、前記絶
縁膜の上面及びビアホール壁面に気相成長法により下地
金属層を層着させるとともに少なくともビアホール壁面
の下地金属層上に前記絶縁膜の厚みに対して1/10以上の
厚みに導電層を電解メッキ法により被着させ、下地金属
層と導電層の2層構造を有する電気配線用導体層を形成
したことを特徴とする多層配線基板の製造方法。
1. An insulating film having a via hole is formed on an insulating substrate having a wiring conductor on the upper surface, and then a base metal layer is deposited on the upper surface of the insulating film and the wall surface of the via hole by a vapor phase growth method. Along with at least the underlying metal layer on the wall surface of the via hole, a conductive layer having a thickness of 1/10 or more of the thickness of the insulating film is deposited by an electrolytic plating method, and an electrical wiring having a two-layer structure of the underlying metal layer and the conductive layer. A method for manufacturing a multi-layer wiring board, comprising forming a conductor layer for use in wiring.
【請求項2】前記電解メッキ法により被着される導電層
が銅(Cu)から成ることを特徴とする特許請求の範囲第
1項記載の多層配線基板の製造方法。
2. The method of manufacturing a multilayer wiring board according to claim 1, wherein the conductive layer deposited by the electrolytic plating method is made of copper (Cu).
【請求項3】前記絶縁膜がポリイミド樹脂、シリコーン
樹脂、ポリブタジエン樹脂、ポリアミドイミド樹脂及び
ポリ四弗化エチレン樹脂のいずれかの高分子材料から成
ることを特徴とする特許請求の範囲第1項記載の多層配
線基板の製造方法。
3. The insulating film is made of a polymer material selected from the group consisting of polyimide resin, silicone resin, polybutadiene resin, polyamideimide resin and polytetrafluoroethylene resin. Manufacturing method of multilayer wiring board.
【請求項4】前記下地金属層がチタン(Ti)、モリブデ
ン(Mo)の少なくとも1種と銅(Cu)の2層構造である
ことを特徴とする特許請求の範囲第1項記載の多層配線
基板の製造方法。
4. The multilayer wiring according to claim 1, wherein the underlying metal layer has a two-layer structure of at least one of titanium (Ti) and molybdenum (Mo) and copper (Cu). Substrate manufacturing method.
JP62333551A 1987-12-28 1987-12-28 Method for manufacturing multilayer wiring board Expired - Fee Related JP2565362B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62333551A JP2565362B2 (en) 1987-12-28 1987-12-28 Method for manufacturing multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62333551A JP2565362B2 (en) 1987-12-28 1987-12-28 Method for manufacturing multilayer wiring board

Publications (2)

Publication Number Publication Date
JPH01173784A JPH01173784A (en) 1989-07-10
JP2565362B2 true JP2565362B2 (en) 1996-12-18

Family

ID=18267308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62333551A Expired - Fee Related JP2565362B2 (en) 1987-12-28 1987-12-28 Method for manufacturing multilayer wiring board

Country Status (1)

Country Link
JP (1) JP2565362B2 (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS529357B2 (en) * 1972-04-26 1977-03-15
JPS58161346A (en) * 1982-03-18 1983-09-24 Nippon Denso Co Ltd Formation of metallic projected electrode
JPS59178749A (en) * 1983-03-30 1984-10-11 Fujitsu Ltd Wiring structure
JPS59202681A (en) * 1983-05-04 1984-11-16 松下電工株式会社 Method of producing printed circuit board

Also Published As

Publication number Publication date
JPH01173784A (en) 1989-07-10

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