JP2565162B2 - Bipolar transistor and manufacturing method thereof - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bipolar transistor in which an emitter region is formed by self-alignment in a base region and a manufacturing method thereof, and particularly to reduce parasitic resistance and parasitic capacitance. The present invention also relates to a bipolar transistor capable of speeding up the operation by narrowing the base width and a method for manufacturing the bipolar transistor.

[Outline of Invention]

According to the present invention, in a bipolar transistor in which a base extraction electrode layer is formed of a low resistance semiconductor layer, and a base region and an emitter region inside the base region are formed by self-alignment, the base region is formed of a single crystal semiconductor layer. At the same time, the connecting means for connecting the base extraction electrode layer and the base region is formed of a polycrystalline semiconductor layer having substantially the same thickness as that of the single crystal semiconductor layer, and the polycrystalline semiconductor layer is formed with impurities from the base extraction electrode layer. Is diffused into a high-concentration region, the parasitic resistance and the parasitic capacitance can be reduced, and the base width can be narrowed to increase the operating speed of the bipolar transistor.

[Conventional technology]

In order to improve the operation speed of the bipolar transistor, it is essential to reduce the parasitic resistance and the parasitic capacitance and to narrow the base width. A so-called graft base type bipolar transistor as shown in FIG. 4 is known as an example of a bipolar transistor which meets such a demand to some extent.

In FIG. 4, for example, a p-type semiconductor substrate (10
1) An n-type epitaxial layer is formed on the n ⁺ -type buried layer (102) formed in (1) by epitaxial growth or the like. The n-type epitaxial layer is an island-shaped region rather than an element isolation region (103) such as silicon oxide. It is separated into (104) and (105). A p ⁺ type base region (106) is formed facing the surface of the n type semiconductor layer of the island region (104), and an n ⁺ type emitter region (107) is formed in the base region (106). Has been done. The base region (106) is a base active region (10) that functions as an original base in the central portion.
6i) and a graft base region (106g) containing a high concentration of impurities for removing the base. The graft base region (160g) is formed by diffusion of p-type impurities from the base extraction electrode layer (108) made of a p ⁺ -type polycrystalline silicon layer, and the base active region (106i) is formed by the base extraction electrode layer. It is formed by implanting p-type impurities using (108) as a mask. Further, the emitter region (107) uses the insulating layer (109) formed on at least the side wall of the base extraction electrode layer (108) as a mask, and n ⁺ for emitter extraction formed on the insulating layer (9). It is formed by diffusion of impurities from the type polycrystalline silicon layer (110). The insulating layer (109) has a base extraction electrode layer (1
An opening (111) is provided in the upper part of 08), and a metal such as aluminum is deposited on the opening (111) to form a base electrode (112)
Has become. Similarly, a metal is deposited on the n ⁺ type polycrystalline silicon layer (110) to form an emitter electrode (113). Further, the insulating layer (109) has an island region (105).
An opening (114) is also provided immediately above, and a metal is similarly deposited here to form a collector electrode (115).

According to the so-called graft base type bipolar transistor having such a structure, it is possible to simplify the manufacturing process of the emitter and the base by self-alignment, reduce the parasitic resistance and the parasitic capacitance, and reduce the base width. To be achieved.

[Problems to be solved by the invention]

By the way, in order to further increase the speed and integration of the bipolar transistor and reduce the power consumption, further reduction in the vertical direction (the thickness direction of the substrate) is desired, and in particular, it is necessary to narrow the base width. It has been demanded. However, if the base width is narrowed, the depletion layer of the emitter and the depletion layer of the collector spread and finally come into contact with each other as the voltage applied to the collector increases, and the base width becomes zero, causing a short circuit state of the emitter and the collector. A so-called punch-through phenomenon easily appears. In order to prevent this punch-through phenomenon, it is effective to increase the concentration of the p-type impurity in the base active region (106i), but keeping the base width narrow and increasing the impurity concentration are contradictory. It is a request. The introduction of the impurities is usually performed by ion implantation. However, when the ion implantation is performed, the concentration of ions has a constant distribution width with respect to the distance. Therefore, when trying to increase the concentration of ions, the distribution region of ions is inevitably expanded, and as a result, the base width is expanded.

Therefore, an object of the present invention is to provide a bipolar transistor capable of high-speed operation and a manufacturing method thereof by increasing the concentration of impurities introduced into the base while keeping the base width narrow.

[Means for solving problems]

That is, the bipolar transistor according to the present invention includes a base lead-out electrode layer made of a low-resistance semiconductor layer and a base region formed in a self-aligned manner at the bottom of a base window defined by the pattern edge of the base lead-out electrode layer. ,
A base connection region connecting the base extraction electrode layer and the base region, a sidewall insulating film formed along the side wall surface of the base window, and an emitter window defined by the sidewall insulating film are covered. An emitter extraction electrode layer made of a low resistance semiconductor layer; and an emitter region formed in a self-aligned manner by solid-phase diffusing impurities from the emitter extraction electrode layer into the base region at the bottom of the emitter window. The base region and the base connection region are formed of a semiconductor layer having a substantially uniform thickness along the inner wall surface of the base window. At this time, the semiconductor layer has a single crystal region serving as a base region and another crystal region containing a high concentration of impurities diffused in solid phase from the base extraction electrode and serving as the base connection region adjacent to each other. Is preferred.

Further, a method for manufacturing a bipolar transistor according to the present invention comprises a step of patterning a low resistance semiconductor layer to form a base extraction electrode layer, and a base on the bottom of a base window defined by a pattern edge of the base extraction electrode layer. A step of forming the region in a self-aligning manner, a step of forming a sidewall insulating film along the side wall surface of the base window,
Forming a low-resistance semiconductor layer so as to cover the emitter window defined by the sidewall insulating film to form an emitter extraction electrode layer, and forming the emitter extraction electrode layer from the emitter extraction electrode layer to the base region at the bottom of the emitter window. A step of forming an emitter region in a self-aligned manner by solid-phase diffusion of impurities into the base region,
Further, the base region and the base connection region connecting the base extraction electrode layer are formed as a part of the semiconductor layer having a substantially uniform thickness along the inner wall surface of the base window. Here, the semiconductor layer is removed except for a single crystal region serving as the base region and a polycrystalline region serving as the base connection region containing a high concentration of impurities that are solid-phase diffused from the base extraction electrode. May be.

[Action]

In the bipolar transistor according to the present invention,
Since the single crystal region serving as the base region and the base connection region connecting the base extraction electrode layer and the base region are formed in the semiconductor layer having a substantially uniform film thickness, the base width is made extremely narrow. It becomes possible. Moreover, since the base region of this single crystal is formed without ion implantation, it contains impurities at a high concentration even though the base width is narrow, and it is possible to effectively prevent punch-through. You can

〔Example〕

 The preferred embodiments of the present invention will be described below.

The present embodiment is a bipolar transistor in which a base extraction electrode layer is formed of a low resistance semiconductor layer, and a base region and an emitter region inside the base region are formed by self-alignment. A base connection region connecting to the region is formed of a polycrystalline region containing a high concentration of impurities diffused from the base extraction electrode, and the base region is formed of a single crystal region. This is an example of a bipolar transistor capable of reducing punch-through by reducing the parasitic resistance and the parasitic capacitance by forming the region and the semiconductor layer at the same time as a semiconductor layer having substantially the same film thickness. This will be described with reference to FIG.

FIG. 1 shows a main part of a bipolar transistor according to the present invention. In this figure, for example, an n-type epitaxial layer (3) is provided by epitaxial growth or the like on an n ⁺ -type buried layer (2) formed in a p-type semiconductor substrate (1) having a (111) surface as a surface. The n-type epitaxy layer (3) is separated into a number of island-shaped regions which will be element formation regions by an element isolation region (4) made of silicon oxide or the like. On such a substrate, a gate extraction electrode layer (7), which is a low resistance semiconductor layer made of p ⁺ -type polycrystalline silicon, and silicon oxide, etc., through an interlayer insulating film (6) made of silicon oxide, silicon nitride, or the like. An insulating layer (8) is sequentially formed, and an opening (9) is formed by patterning immediately above the n-type epitaxial layer (3).
Is provided. Further, a p-type silicon layer (10), which is a semiconductor layer containing a high concentration of p-type impurities, is formed facing the opening (9). The p-type silicon layer (10) is a single crystal silicon layer at the bottom of the opening (9) and is a base region (10b) to be a base forming portion.
And a base connection region (10c) made of polycrystalline silicon containing a high concentration of p-type impurities for electrical connection with the base extraction electrode layer (7). The base connection region (10c) is formed by diffusing p-type impurities from the base extraction electrode layer (7) made of p ⁺ -type polycrystalline silicon, and the opening (9) is further provided with a sidewall (11). An emitter extraction electrode layer (12) made of n ⁺ -type polycrystalline silicon is deposited therethrough. When this substrate is annealed, the emitter extraction electrode layer (12)
From the above, the n-type impurity is diffused toward the inside of the base region (10b) by self-alignment using the sidewall (11) as a mask to form the emitter region (13). At this time, the p-type impurities diffuse from the base connection region (10c) into the n-type epitaxial layer (3), and the graft base region (14) is formed. Further, an emitter electrode (15) is formed on the emitter extraction electrode layer (12) by covering with a metal such as aluminum. In addition, the base electrode (17) is provided in the opening (16) provided in the insulating layer (8) on the base extraction electrode layer (7), and another island-shaped region (see (2) in FIG. (See (5)) and the opening (see (18) in FIG. 2 (F)) provided in the interlayer insulating film (6) and the insulating layer (8) above the collector electrode (see FIG. 2 (F)). ) (See (19)) are respectively deposited.

The greatest structural feature of the bipolar transistor as described above is that the base connection region (10c) electrically connects the base region (10b) and the base extraction electrode layer (7).
However, it is a part of the same p-type silicon layer (10) as the base region (10b) and has a substantially same film thickness. Since the p-type silicon layer (10) is a thin film formed by epitaxial growth, it is possible to make the base width B _W extremely narrow, and it is possible to realize a high speed bipolar transistor. Moreover, since the base region (10b) has a high impurity concentration, it is possible to effectively prevent the pinch through and reduce the parasitic resistance even though the base width is very narrow.

The structural characteristics of such a bipolar transistor also lead to the characteristics of the manufacturing method. That is, the present manufacturing method skillfully utilizes the characteristics of the epitaxial growth method in which the crystallinity of the underlayer is inherited and the crystal is grown, and the crystal plane anisotropy and the KOH etching having the concentration dependence on the impurity boron. is there. Hereinafter, a method for manufacturing a bipolar transistor according to the present invention will be described with reference to FIGS. 2 (A) to 2 (F).

First, in FIG. 2A, an n ⁺ type buried layer (2) and ap ⁺ type channel cut layer (20) are formed on a p type semiconductor substrate (1) having a (111) plane, and n is formed on the entire surface. After epitaxially growing the type semiconductor layer, an element isolation region (4) of silicon oxide is formed by selective oxidation isolation or the like, and a substrate is formed into some island-shaped regions for forming an element, for example, an n-type epitaxial layer (3). And an island region (5).

Next, as shown in FIG. 2B, a thin silicon oxide film is formed on the entire surface of such a substrate by thermal oxidation, CVD or the like to form an interlayer insulating film (6). At this time, a silicon nitride film may be used instead of the silicon oxide film.

A base extraction electrode layer (7) made of p ⁺ -type polycrystalline silicon is further deposited on the interlayer insulating film (6) so as to face the upper portion of the n-type epitaxial layer (3). At this time, the concentration of boron, which is a p-type impurity, in the base extraction electrode layer (7) is determined by the diffusion of boron in the base connection region (10c), which will be described later, from the base extraction electrode layer (7).
Choose high enough to be around 10 ²⁰ cm ^-3 .

An insulating layer (8) of silicon oxide is further deposited on the entire surface of this substrate by CVD or the like. The insulating layer (8) may be made of silicon nitride.

Next, as shown in FIG. 2 (C), the insulating layer (8), the base extraction electrode layer (7) and the interlayer insulating film (6) are patterned by RIE or the like to form an n-type epitaxial layer (3). An opening (9) for forming a base and an emitter is provided immediately above. At this time, in order not to damage the surface of the n-type epitaxial layer (3), only the interlayer insulating film (6) may be removed by liquid phase etching.

Next, in order to form a semiconductor layer to be a base region and a base connection region, as shown in FIG. 2D, a p-type silicon layer (10) is epitaxially grown on the entire surface of the substrate by MBE. At this time, since the p-type silicon layer (10) grows while inheriting the crystallinity of the underlying layer, the polycrystalline silicon layer (10p) grows in the exposed portion of the insulating layer (8) and the opening (9). Similarly, a polycrystalline silicon layer grows on the side wall of the base extraction electrode layer (7) exposed at () to form a base connection region (10c), while the bottom (111) face of the opening (9) serves as the surface. n-type epitaxial layer (3)
On the upper surface of, a single crystal silicon layer having a (111) surface as a surface grows and becomes a base region (10b). At this time, the thickness of the p-type silicon layer (10) is set to 1,000 Å or less, and the temperature of boron which is a p-type impurity is set to 10 ¹⁸ to 10 ¹⁹ cm ^-3 . Therefore, on the side wall of the opening (9), the base extraction electrode layer (7) and the p-type silicon layer (10) having different boron concentrations are formed in contact with each other.

Next, in order to use the p-type silicon layer (10) formed on the side wall of the opening (9) as a means for electrically connecting the base region (10b) and the base extraction electrode layer (7), an appropriate annealing is performed. Perform processing. Then, due to the difference in the boron concentration, p is removed from the base extraction electrode layer (7) at the side wall of the opening (9).
Boron diffuses into the type silicon layer (10) to form a base connection region (10c). This annealing treatment is performed so that the concentration of boron in the base connection region (10c) is 10 ²⁰ cm ⁻³ or more. In addition, this annealing treatment causes a small p ⁺ -type region in the n-type epitaxial layer (3) immediately below the base connection region (10c) to become a graft base region (14), and the base region (10b) and the base extraction electrode layer are formed. (7) Plays a role of helping electrical connection with.

The above-mentioned p-type silicon layer (10) can be formed by an epitaxial growth method instead of MBE. However, the p-type impurity from the above-mentioned base region (10b) to the n-type epitaxial layer (3) is reproduced. In the sense of preventing diffusion,
It can be said that MBE, which can be carried out at a low temperature, is more preferable. Further, after depositing polycrystalline silicon on the entire surface of the substrate by LP (decompression) CVD method, n at the bottom of the opening (9) is deposited.
The base region (10b) may be formed by growing a single crystal by solid phase growth in the portion in contact with the type epitaxial layer (3).

Next, in the p-type silicon layer (10), etching is performed using KOH in order to remove the polycrystalline silicon layer (10p) while leaving the base connection region (10c) and the base region (10b). This step utilizes the surface anisotropy of etching of silicon with KOH and the boron concentration dependence.

First, KOH has surface anisotropy that it does not etch the (111) surface of silicon. Therefore, the base region (10b) made of the single crystal silicon layer grown on the bottom of the opening (9) is not etched.

Further, KOH has a boron concentration dependency that it does not etch a silicon layer containing boron at a concentration of 10 ²⁰ cm ^-3 or more. This characteristic is shown in FIG. In this figure,
The vertical axis represents the etching rate (Å / min) and the horizontal axis represents the boron concentration in the silicon layer. Looking at this, the etching rate is
It can be seen that when the boron concentration near 10 ¹⁹ cm ^-3 is used as a boundary, it sharply decreases on the high concentration side. Therefore, as shown in FIG. 2 (E), a region having a boron concentration of 10 ¹⁹ cm ⁻³ or less, that is, the upper surface of the insulating layer (8) and the opening (9).
Only the polycrystalline silicon layer (10p) formed near the entrance of is removed selectively.

Next, the emitter is formed. First, as shown in FIG. 2 (F), a side wall (11) is formed on the side wall of the opening (9), and then a polycrystalline silicon layer is deposited by CVD or the like. Impurities are injected to form an emitter extraction electrode layer (12). The emitter extraction electrode layer (12) may be formed by MBE or the like.

Next, when this substrate is annealed, self-alignment is performed at the bottom of the opening (9) using the sidewall (11) as a mask, and the emitter extraction electrode layer (12) is transferred to the base region (10b). The n-type impurity diffuses to form an emitter region (13). Therefore, in the single crystal silicon region, the portion narrowed by the formation of the emitter region (13) functions as the original base, and the base width becomes B _w . In addition,
This annealing process is performed by diffusing the p-type impurity from the base region (10b) to the n-type epitaxial layer (3) to increase the base width.
It is desirable to carry out at the lowest possible temperature so that B _w does not spread.

Next, an opening (16) is provided in the insulating layer (8) on the base extraction electrode layer (7) to form a base contact, while an island region connecting to the n ⁺ type buried layer (2) is formed. An opening (18) is provided just above (5) to form a collector contact. When metal wiring such as aluminum is deposited on the openings (16) and (18) and the emitter extraction electrode layer (12), the base electrode (17),
A collector electrode (19) and an emitter electrode (15) are formed respectively.

In this example, the step of growing the p-type silicon layer (10) over the entire surface was performed as shown in FIG. 2 (D), but instead of this, a substrate in the state shown in FIG. 2 (C) was used. Alternatively, selective epitaxial growth may be performed. in this case,
Since neither a single crystal silicon layer nor a polycrystalline silicon layer grows on the insulating layer (8) of silicon oxide, the substrate in the state shown in FIG. 2 (E) can be obtained directly.

Further, the present invention is not limited to the above-mentioned embodiment, and the p-type conductivity and the n-type conductivity may be exchanged with each other.

〔The invention's effect〕

In the bipolar transistor created by the above manufacturing method, the base region is formed by epitaxial growth and is provided in the semiconductor layer containing a high concentration of impurities, so that the base width can be extremely narrowed,
In addition, it is possible to prevent punch through. Also,
For electrical connection between the base region and the base extraction electrode layer, a portion of the semiconductor layer on the side wall surface of an opening for forming a base and an emitter, that is, a vertical portion of the semiconductor layer is used as a base connection region. It is realized by Since this semiconductor layer is formed by the epitaxial growth method which is excellent in the controllability of the film thickness, the film thickness can be made extremely thin, and thus the area of the substrate necessary for forming the base can be reduced.

If the base connection region of the structure using the vertical portion of the semiconductor layer as described above is to be formed by the so-called sidewall forming technique using RIE which has been the mainstream in the past, first, about 3,000 Å of polycrystalline silicon After forming and depositing on the entire surface of the substrate, etch back must be performed, which complicates the process. In addition, the width of the formed base region cannot be made thinner than 1,500 to 2,000Å or less, and the base region may be damaged. Therefore, the manufacturing method according to the present invention is extremely effective in miniaturizing the bipolar transistor.

Further, in the bipolar transistor according to the present invention, the area of the emitter and the base can be reduced, so that the parasitic capacitance C _BE between the base and the emitter and the parasitic capacitance C _CB between the collector and the base are reduced. Moreover, since the impurity concentration of the base region, the base connection region, and the base extraction electrode layer is high, the parasitic resistance is also effectively reduced.

As described above, the present invention is extremely effective for miniaturization, speedup, and improvement of reliability of the bipolar transistor.

[Brief description of drawings]

FIG. 1 is a schematic sectional view of a main part of a bipolar transistor according to the present invention. 2 (A) to 2 (F) are schematic cross-sectional views illustrating a method of manufacturing a bipolar transistor according to the present invention in the order of steps thereof.
FIG. 2A is an oxidation separation step, FIG. 2B is a gate extraction electrode layer and insulating layer formation step, FIG. 2C is a patterning step, and FIG. 2D is a p-type silicon layer formation. 2 (E) shows the selective removal step of the p-type silicon layer, and FIG. 2 (F) shows the step of forming the emitter region and each electrode. FIG. 3 is a characteristic diagram showing the boron concentration dependence of the etching of the silicon layer by KOH. Fourth
The figure is a schematic cross-sectional view showing the structure of a conventional graft-based bipolar transistor. 1 ... Semiconductor substrate 7 ... Base extraction electrode layer 8 ... Insulation layer 10 ... P-type silicon layer 10c ... Base connection region 10b ... Base region 10p ... Polycrystalline silicon layer 12 ... Emitter extraction electrode layer 13 …… Emitter region 15 …… Emitter electrode 17 …… Base electrode 19 …… Collector electrode

Claims (4)

(57) [Claims] 1. A base extraction electrode layer made of a low-resistance semiconductor layer, a base region formed in a self-aligned manner at the bottom of a base window defined by a pattern edge of the base extraction electrode layer, and the base extraction electrode. Base connecting region connecting the layer and the base region, a sidewall insulating film formed along the side wall surface of the base window, and a low resistance semiconductor layer covering the emitter window defined by the sidewall insulating film. A bipolar transistor having an emitter extraction electrode layer made of, and an emitter region formed in a self-aligned manner by solid-phase diffusing impurities from the emitter extraction electrode layer into the base region at the bottom of the emitter window. The base region and the base connection region are made of a semiconductor layer having a substantially uniform thickness along the inner wall surface of the base window. Lara transistor. 2. The semiconductor layer adjoins a single crystal region serving as the base region and a polycrystalline region serving as the base connection region containing a high concentration of impurities diffused from the base extraction electrode in a solid phase. The bipolar transistor according to claim 1, which has the following features. 3. A step of patterning a low resistance semiconductor layer to form a base extraction electrode layer, and a base region is formed in a self-aligned manner at the bottom of a base window defined by a pattern edge of the base extraction electrode layer. A step of forming a side wall insulating film along the side wall surface of the base window, a step of forming a low resistance semiconductor layer so as to cover the emitter window defined by the side wall insulating film, and an emitter extraction electrode layer And a step of forming the emitter region in a self-aligned manner by solid-phase diffusing impurities from the emitter extraction electrode layer into the base region at the bottom of the emitter window. And a base connection region connecting the base region and the base extraction electrode layer The method of manufacturing a bipolar transistor formed as part of a semiconductor layer of substantially uniform thickness along the inner wall surface of the base window. 4. The semiconductor layer leaves a single crystal region serving as the base region, and a polycrystalline region serving as the base connection region containing a high concentration of impurities diffused by solid phase from the base extraction electrode. The method for manufacturing a bipolar transistor according to claim 3, wherein the bipolar transistor is removed.