JP2552883Y2 - Gate array with built-in booster circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a gate array with a built-in booster circuit that operates at high speed even with a relatively low voltage power supply such as a battery.

<Conventional technology> There is a CMOS gate array as a gate array that operates with a relatively low voltage power supply such as a battery. In a low voltage type, all logic circuits operate even with a power supply voltage of about 1 V. . However, such a low-voltage CMOS gate array also has a drawback that if the power supply voltage is actually low, the operation speed is significantly limited, and its use is limited. CMOS
The reason why the operation speed is reduced when the power supply voltage is reduced in the gate array is as follows.

<Problem to be solved by the invention> The operating speed of a CMOS gate array is determined by the propagation delay time of a MOS transistor. The propagation delay time increases as the difference between the gate-source voltage of the MOS transistor and the threshold voltage decreases, The operating speed becomes slow.
Therefore, if the threshold voltage of the MOS transistor is lowered to increase the difference between the gate-source voltage and the threshold voltage, the propagation delay time is reduced and the operation speed is increased. However, if the threshold voltage is set too low, the leakage current increases between the drain and source of the MOS transistor, and the current consumption increases. In such a case, the replacement life of the battery is shortened in the CMOS gate array that frequently uses the battery as the power supply. Therefore,
The threshold voltage cannot be extremely low and the MO
When the threshold voltage is set to a level where the leakage current between the drain and source of the S transistor does not matter, the propagation delay time is several tens to hundreds of times when the power supply voltage is 1 V compared to when the power supply voltage is 5 V. become longer.

To solve this problem, double the power supply voltage of the LSI,
It is conceivable to operate the logic circuit by increasing the voltage by three times. However, if such an LSI is to be manufactured in full custom, a considerably long development period is required.

The present invention was created in view of the above circumstances,
It is an object of the present invention to provide a gate array in which a logic circuit operates at a high speed even at a low voltage and a development period is relatively short.

<Means for Solving the Problems> A gate array according to the present invention is a gate array with a built-in booster circuit having a booster circuit for boosting a power supply voltage,
An oscillator for generating a pulse signal, an inverter for inverting the level of the pulse signal generated by the oscillator, a first capacitor to which an output of the inverter is provided at one end, and a pulse generated by the oscillator. Switching means for applying the pulse signal to the other end of the first capacitor when the signal is at a high level and cutting off the other end of the first capacitor, and opening the other end of the first capacitor when at a low level; A second capacitor connected to the other end of the first capacitor and supplying a charging voltage to the logic circuit.

<Operation> When the pulse signal generated by the oscillation means is at a high level,
For example, at the power supply voltage level, one end of the first capacitor is charged to the low level and the other end is charged to the power supply voltage level.
From this state, when the pulse signal generated by the oscillating means switches to a low level, one end of the first capacitor goes to the power supply voltage level, and accordingly, the other end of the first capacitor rises to twice the power supply voltage level. Is done. As a result, the double voltage is charged in the second capacitor, and by repeating this cycle, the voltage applied to the logic circuit approaches twice the power supply voltage level without limit. If such a booster circuit is provided in two or three stages, the logic circuit can be operated at a voltage three times or four times the power supply voltage.

<Example> Hereinafter, an example of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an example of a gate array according to the present invention, FIG. 2 is a schematic diagram of the chip, FIG. 3 is a circuit diagram of a level shifter used in the booster circuit, and FIG. 5 is a timing chart for explaining the operation of the circuit.

The gate array, as shown in FIGS. 1 and 2,
It consists of a logic circuit and a booster circuit.
Oscillating means 10 operating at Vcc is provided. Oscillation means 10
Outputs a pulse signal whose low level is GND and whose high level is the power supply voltage Vcc to the inverter 20 and the switching means 30. The inverter 20 operates at the power supply voltage Vcc, inverts the level of the pulse signal output from the oscillating means 10, and applies the inverted signal to one end of the first capacitor 40. The other end of the first capacitor 40 is connected to one end of a second capacitor 50 via an analog switch 32 of the switching means 30 described later. The other end of the second capacitor 50 is grounded. The logic circuit operates with a voltage charged at one end of the second capacitor 50.

The switching means 30 has two analog switches 31 and 32 controlled by a voltage Vcc2 which is twice the power supply voltage Vcc. The pulse signal output from the oscillating means 10 is double-converted by the level shifter 33 to the analog switch 31 and given as a conduction control signal. The conduction control terminal of the analog switch 32 receives the output of the level shifter 33 from the inverter. 34
Given through. Thus, the analog switch 31
Is turned on when the pulse signal output from the oscillating means 10 is at a high level, and the voltage is applied to the other end of the first capacitor 40, and turned off when the pulse signal output from the oscillating means 10 is at a low level. State. When the pulse signal output from the oscillation unit 10 is at a high level, the analog switch 32
When the state becomes the F state and the pulse signal output from the oscillating means 10 is at a low level, the state is turned on to make the first capacitor 40 and the second capacitor 50 conductive.

The control voltage of the analog switches 31 and 32 is the power supply voltage Vc
The double of c is due to the analog switches 31 and 3
This is because the signal voltage controlled by 2 is twice the power supply voltage Vcc.

As shown in FIG. 3, the level shifter 33 for converting the level of the control voltage of the analog switches 31 and 32 includes two
It has a well-known configuration in which NchMOS transistors Tr1 and Tr2, two PchMOS transistors Tr3 and Tr4, and an inverter are combined.

When the signal input to the gate of the transistor Tr1 is at low level GND, the transistor Tr1 is turned off and the transistor Tr2 is turned on. When the transistor Tr2 is turned on, the voltage at the node between the transistor Tr4 and the transistor Tr2 is determined by the resistance ratio between the transistor Tr4 and the transistor Tr2. When the voltage becomes smaller than (Vcc2−Vth3), the transistor T2 is turned off.
r2 is turned on, and the transistors Tr3 and Tr1
At the node between Vcc2 and Vcc2. Vth3 is a threshold voltage of the transistor Tr3. Then, the transistor Tr4 is turned off and the transistor Tr4 is turned off.
The voltage at the node between 4 and the transistor Tr2 goes to low level GND.

When the signal input to the gate of the transistor Tr1 is at the high level Vcc, the transistors Tr1 and Tr4 are on, the transistors Tr2 and Tr3 are off, and the voltage at the node between the transistor Tr4 and the transistor Tr2 is high. Vcc2. Thus, the pulse signal of the amplitude Vcc input to the gates of the transistors Tr1 and Tr2 is level-shifted to the amplitude Vcc2, and the transistor Tr4 and the transistor T4
It is extracted from the node between r2.

The booster circuit built-in gate array having the above configuration operates as follows.

In the booster circuit, a node between the oscillating means 10 and the inverter 20 is a point A, a node between the inverter 20 and the first capacitor 40 is a point B, and between the first capacitor 40 and the analog switch 31 of the switching means 30. Is a point C, and a node between the analog switch 31 and the second capacitor 50 is a point D, as shown in FIG. , A pulse waveform having a high level of the power supply voltage Vcc appears, and an inverted waveform thereof appears at point B.

When the point A is at the high level Vcc, the analog switch 31 of the switching means 30 is turned on and the analog switch 32 is turned off. In addition, point B becomes low level GND. Therefore, a high level Vcc voltage is derived at the point C, and the first capacitor 40 is charged to the GND level at the point B side and to the Vcc level at the point C side. When the point A shifts to the low level GND from this state, the analog switch 31 becomes non-conductive,
The voltage at the point switches from low level GND to high level Vcc. Therefore, the point C at the Vcc level becomes the voltage Vcc2 which is twice the Vcc. Further, the analog switch 32 changes from the non-conductive state to the conductive state. Therefore, a voltage of the Vcc2 level is derived at the point D, and the second capacitor 50 is charged by this voltage. By repeating this cycle, the steady voltage at the point D approaches Vcc2 without limit, and as a result, the logic circuit is driven by the voltage Vcc2 which is twice Vcc. Vcc from 1 to 1.5V
Then, the operation speed of the logic circuit driven by Vcc2 is several tens times faster than that of the logic circuit driven by Vcc.

The initial operation of boosting after turning on the power is as follows. That is, when the power supply voltage Vcc is applied from outside the gate array and the output of the oscillation means 10 and the voltage at the point A become Vcc, the PN junction of the analog switch 31 (forward drop voltage =
0.6V), the voltage at point C becomes (Vcc-0.6). That is, the charging voltage of the capacitor 40 at this time is (Vcc-0.6)
It is. Then, when the voltage at the point A becomes 0 and the voltage at the point B becomes Vcc due to the inversion of the oscillation waveform, the voltage at the point C becomes (V
cc-0.6) + Vcc. Then, similarly, through the PN junction of the analog switch 32 (forward drop voltage = 0.6 V), D
The point has a voltage of [(Vcc−0.6) + Vcc] −0.6 = 2 · Vcc. This voltage (= Vcc2) is supplied to the level shifter 33 and the inverter 34, and the circuit becomes operable.

If booster circuits are provided in two or three stages, three times the power supply voltage,
The logic circuit can be operated at four times the voltage.

FIG. 5 is a cross-sectional view showing another chip structure, showing a case where the capacitor capacity is large. The chip encapsulated in the resin 60 is such that the chips 61 and 62 of the first capacitor and the second capacitor are separated from the gate array chip 63 and the substrate 64
It is configured to be mounted on a gate array chip
63 and capacitor chips 61 and 62, capacitor chip 6
Wires 66 are connected between 1,62 and the external leads 65,65, respectively.

<Effects of the Invention> Since the gate array according to the present invention operates the logic circuit by increasing the power supply voltage, the operation speed of the logic circuit can be increased, and the application of the gate array can be expanded. In addition, since the threshold voltage can be set to a level at which the leakage current of the MOS transistor does not matter, the current consumption does not increase. Further, since the booster circuit for boosting the power supply voltage of the logic circuit is independent of the logic circuit, the development period can be relatively short.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of a gate array according to the present invention, FIG. 2 is a schematic diagram of the chip, FIG. 3 is a circuit diagram of a level shifter used in the booster circuit, and FIG. A timing chart for explaining the operation of the circuit,
FIG. 5 is a sectional view showing another chip structure. 10 Oscillating means 20 Inverter 30 Switching means 40 First capacitor 50 Second capacitor

Claims (1)

(57) [Scope of request for utility model registration] 1. A gate array with a built-in booster circuit having a booster circuit for boosting a power supply voltage, wherein the booster circuit inverts an oscillating means for generating a pulse signal and a level of the pulse signal generated by the oscillating means. An inverter, a first capacitor to which an output of the inverter is applied to one end; and a pulse signal generated by the oscillating means when the pulse signal is at a high level. Switching means for shutting off the side and opening the other end of the first capacitor when it is at a low level, and a second capacitor connected to the other end of the first capacitor and supplying a charging voltage to the logic circuit. A gate array with a built-in booster circuit.