JP2550902B2 - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JP2550902B2 JP2550902B2 JP5327131A JP32713193A JP2550902B2 JP 2550902 B2 JP2550902 B2 JP 2550902B2 JP 5327131 A JP5327131 A JP 5327131A JP 32713193 A JP32713193 A JP 32713193A JP 2550902 B2 JP2550902 B2 JP 2550902B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- package
- wiring
- pins
- pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はピングリッドアレイパッ
ケージの半導体装置に関し、特に両面にピンを設けたＰ
ＧＡ型パッケージの半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device of a pin grid array package, and more particularly to a P device having pins on both sides.
The present invention relates to a GA type package semiconductor device.
【０００２】[0002]
【従来の技術】従来のピングリッドアレイパッケージ
（以後ＰＧＡと称する）は、図３に示すようにパッケー
ジ本体１の片面から、複数のピン２が垂直に突出し、ピ
ン２はパッケージ本体１の内部で、配線３を通り、半導
体集積回路チップ６とボンディングワイヤ５を介して接
続されるステッチ４まで電気的につながっている。ＰＧ
ＡはＱＦＰ（クワッドフラットパッケージ）等の他のパ
ッケージに比べ、超多ピンが可能、消費電力の最大許容
値が大きい、といった利点があり、そういった場合に使
用されることが多い。2. Description of the Related Art In a conventional pin grid array package (hereinafter referred to as PGA), a plurality of pins 2 vertically project from one surface of a package body 1 as shown in FIG. The wiring 4 is electrically connected to the stitch 4 which is connected to the semiconductor integrated circuit chip 6 via the bonding wire 5. PG
Compared to other packages such as QFP (Quad Flat Package), A has the advantages that it can have a large number of pins and has a large maximum allowable value of power consumption, and is often used in such cases.
【０００３】そこで、ピン数をさらに増加させるために
図４のようにピンをパッケージの両面に配置する方法も
公知である（例えば、公開実用新案公報昭６３−８７８
４１）。Therefore, in order to further increase the number of pins, a method of arranging the pins on both sides of the package as shown in FIG. 4 is also known (for example, JP-A-63-878).
41).
【０００４】[0004]
【発明が解決しようとする課題】ＰＧＡは超多ピン、高
消費電力の製品に多用されるため、多ピン化、高消費電
力化が進んでいる。しかし、ピン数を増加させると配線
が細く長くなり、パッケージ内配線のインピーダンス、
インダクタンスが増大し、電源ラインのノイズ量が増大
する。また消費電力が高い場合、パッケージ内に大電力
が流れ電源のノイズ量はさらに増大する。Since the PGA is frequently used in products with an extremely large number of pins and high power consumption, the number of pins and power consumption are increasing. However, if the number of pins is increased, the wiring becomes thin and long, and the impedance of the wiring inside the package
The inductance increases and the amount of noise on the power supply line increases. Further, when the power consumption is high, a large amount of power flows in the package and the noise amount of the power source further increases.
【０００５】電源にノイズが入ると、基準電圧が変動す
るため、特にアナログ回路、ノイズ量が大きくなればデ
ジタル回路にも致命的なエラーを起こす。When the power supply is noisy, the reference voltage fluctuates, so that a fatal error occurs in the analog circuit, especially in the digital circuit if the noise amount becomes large.
【０００６】そこでＰＧＡのピン数を増加させながら
も、電源にノイズ量を減らすことが必要だった。Therefore, it is necessary to reduce the amount of noise in the power supply while increasing the number of PGA pins.
【０００７】[0007]
【課題を解決するための手段】本発明のＰＧＡは、ピン
をパッケージの両面に設け、その片面に電源（ＧＮＤ又
はＶCC）のピンを他の片面に信号ピンを持つ構造を有し
ている。The PGA of the present invention has a structure in which pins are provided on both sides of a package, and one side has a power supply (GND or V CC ) pin and the other side has a signal pin. .
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。The present invention will be described below with reference to the drawings.
【０００９】図１は本発明のＰＧＡを用いた一実施例の
断面図である。パッケージ内の電源配線８と信号配線３
は、可能な限り距離をとって引き、そのまま交差するこ
となく、それぞれ電源ピン７と信号用ピン２に接続され
ている。つまり電源ピンは上面のみに、信号用ピンは下
面のみに配置されている。FIG. 1 is a sectional view of an embodiment using the PGA of the present invention. Power wiring 8 and signal wiring 3 in the package
Are connected to the power supply pin 7 and the signal pin 2 respectively without pulling as far as possible and crossing each other. That is, the power supply pins are arranged only on the upper surface and the signal pins are arranged only on the lower surface.
【００１０】図２はパッケージ内配線及び電源入力信号
の電気的模式図である。チップ上での電源電圧Ｖは常に
電源電圧Ｖsourceと同一であることが理想であるが、信
号電圧Ｖsig が変化することによって、電源線、信号配
線間の寄生容量Ｃの両極の電位差に変化が起こり、電源
配線にも電流が流れる。その際、電源配線抵抗Ｒ1 、電
源配線インダクタンスＬ1 の影響でＶに変化が生じる。
また、チップが動作する際にも電源配線上に電流が流
れ、Ｖは変動する。FIG. 2 is an electrical schematic diagram of the wiring in the package and the power input signal. Ideally, the power supply voltage V on the chip is always the same as the power supply voltage Vsource. However, a change in the signal voltage Vsig causes a change in the potential difference between the two poles of the parasitic capacitance C between the power supply line and the signal wiring. , Current also flows through the power supply wiring. At that time, V changes due to the influence of the power supply wiring resistance R 1 and the power supply wiring inductance L 1 .
Further, when the chip operates, a current flows on the power supply wiring and V changes.
【００１１】ここで、Ｖsig が変動もしくは電源配線に
電流が生じた場合、Ｖの変動量を抑えるためには、
Ｒ1 、Ｌ1 、Ｃの値を小さくすることが有効であること
は広く知られている。Here, when Vsig fluctuates or a current is generated in the power supply wiring, in order to suppress the fluctuation amount of V,
It is widely known that reducing the values of R 1 , L 1 and C is effective.
【００１２】本実施例では、ピンを上下に配置し、しか
も上面に電源ピンのみを配置しているため、電源配線は
上側のパッケージ内配線領域に太い配線領域を確保でき
る。また上下にピンを配置することにより、パッケージ
面積は小さくなりその分パッケージ内の配線長は減少す
る。電源配線が太く短くなることにより、Ｌ1 は減少
し、結果Ｖの変動量は減少する。In this embodiment, since the pins are arranged vertically and only the power supply pins are arranged on the upper surface, the power supply wiring can secure a thick wiring area in the upper package wiring area. Also, by arranging the pins on the upper and lower sides, the package area is reduced and the wiring length in the package is reduced accordingly. By making the power supply wiring thick and short, L 1 is reduced, and as a result, the amount of fluctuation of V is reduced.
【００１３】通常ＰＧＡのインダクタンスは数十ナノヘ
ンリー程度であるが、本発明により例えば電源配線幅を
３倍、長さが８０％とすることが可能であり、その場
合、インダクタンスＬはおよそ１／４に減少し、電流変
化分に起因する電源ノイズも１／４になる。Normally, the inductance of PGA is about several tens of nanohenries, but according to the present invention, for example, the power supply wiring width can be tripled and the length can be 80%. In that case, the inductance L is about 1 / l. 4, and the power supply noise caused by the change in current also becomes 1/4.
【００１４】また本発明では、電源配線と信号配線間の
距離を広げることにより、Ｃの値も減少させることがで
きる。例えば、電源配線と信号配線間の距離を２倍にす
ると寄生容量はおよそ１／２に減少し、容量の充放電に
起因する電源ノイズは１／２となる。Further, in the present invention, the value of C can be reduced by increasing the distance between the power supply wiring and the signal wiring. For example, if the distance between the power supply wiring and the signal wiring is doubled, the parasitic capacitance is reduced to about 1/2, and the power supply noise due to the charge / discharge of the capacitance is reduced to 1/2.
【００１５】[0015]
【発明の効果】以上説明したように、本発明はＰＧＡの
両面にピンを設け、その片面には電源ピンを、他の片面
には信号ピンを配置することで、パッケージ内配線につ
いて、電源用配線は信号用配線から大きく離し、電源配
線を太く短かくすることを可能とする。従って、パッケ
ージ内配線のインピーダンス、インダクタンス、寄生容
量を減少させ、結果、パッケージに搭載したチップの電
源ノイズを抑られ、チップの誤動作を防ぐ効果を有す
る。As described above, according to the present invention, the pins are provided on both sides of the PGA, and the power supply pin is arranged on one side of the PGA and the signal pin is arranged on the other side thereof. The wiring can be widely separated from the signal wiring, and the power wiring can be made thick and short. Therefore, the impedance, the inductance, and the parasitic capacitance of the wiring in the package are reduced, and as a result, the power supply noise of the chip mounted in the package is suppressed and the chip malfunction is prevented.
【図１】一実施例の断面図FIG. 1 is a sectional view of an embodiment.
【図２】パッケージ内配線の電気的模式図FIG. 2 is an electrical schematic diagram of wiring inside a package.
【図３】従来例のＰＧＡ断面図FIG. 3 is a cross-sectional view of a conventional PGA.
【図４】他の従来例のＰＧＡ斜視図FIG. 4 is a perspective view of another conventional PGA.
１ パッケージ本体 ２，７ ピン ３，８ パッケージ内配線 1 Package body 2, 7 pins 3, 8 Package wiring
Claims (2)
ージにおいて、ピンをパッケージの両面に有し、その片
面に電源ピンを配置し、他の片面に信号ピンを配置した
ことを特徴とする半導体用ＰＧＡパッケージ。1. A pin grid array package for a semiconductor device, wherein pins are provided on both surfaces of the package, a power supply pin is arranged on one surface of the package, and a signal pin is arranged on the other surface of the package. .
用であることを特徴とする請求項１記載の半導体用ＰＧ
Ａパッケージ。2. The semiconductor PG according to claim 1, wherein the power supply pin is for a power supply voltage or a ground voltage.
A package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5327131A JP2550902B2 (en) | 1993-12-24 | 1993-12-24 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5327131A JP2550902B2 (en) | 1993-12-24 | 1993-12-24 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07183424A JPH07183424A (en) | 1995-07-21 |
| JP2550902B2 true JP2550902B2 (en) | 1996-11-06 |
Family
ID=18195663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5327131A Expired - Fee Related JP2550902B2 (en) | 1993-12-24 | 1993-12-24 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2550902B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11204679A (en) * | 1998-01-08 | 1999-07-30 | Mitsubishi Electric Corp | Semiconductor device |
-
1993
- 1993-12-24 JP JP5327131A patent/JP2550902B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07183424A (en) | 1995-07-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960625 |
|
| LAPS | Cancellation because of no payment of annual fees |