JP2550529B2 - Recording and playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field B Outline of invention C Conventional technology D Problems to be solved by the invention E Means for solving problems (Fig. 1) F Action G Example G ₁ Circuit configuration (Fig. 1) ) Structure of G ₂ data (Figs. 2 and 3) G ₃ Description of operation (Fig. 4) H Effect of the invention A Industrial field of application This invention is a program start identification signal indicating the start of a program and unnecessary. The present invention relates to a recording / reproducing apparatus suitable for use when erasing a skip identification signal or the like for skipping an information part.

B Summary of the Invention The present invention is a recording / reproducing apparatus for erasing various identification signals recorded on a recording medium, detects the identification signals recorded on the tape, and detects the PCM area and the subcode area on the track at that time. By storing the address signal in the PCM area and changing the content of the identification signal based on this address signal and re-recording it, various identification signals can be surely erased. .

C Conventional Technology A rotary head is known as a digital tape recorder for recording an audio signal on a tape as a PCM signal.

This is called R-DAT and has a diameter of 3
The tape is wound around a small drum of about 0 mm by 90 °, and two rotary heads having different azimuths arranged at 180 ° are rotated at, for example, 2000 rpm, and these two rotary heads are alternately rotated 90 ° on the tape. Intermittent scanning is performed for each lap.

On the other hand, when the audio signal
Sampling at kHz, each sample value is linearly quantized by 16 bits to generate a PCM audio signal, which is time-compressed to 90 ° wrap angle every 1/2 rotation time of the rotating head, Is recorded as one diagonal track. Then, during reproduction, the PCM signals from the two rotary heads are decoded and expanded to the original time axis, and then the analog audio signal is returned.

In this case, not only the PCM data but also the tracking servo signal during playback and subcodes such as the time code and the program number inserted at the beginning of the song are recorded in each track in a separate area from the PCM data. It

FIG. 5 shows the R-DAT tape format, in which each track T of the PCM audio signal has a 90 ° angle range.
Is recorded in an area PCM of a little less than 60 ゜, and two areas ATF on both sides of this area PCM (about 2.3
In ゜), a pilot signal for tracking servo is recorded. Further, a subcode is recorded in two areas SUB (each about 5 °) on both sides on the outside.

The pilot signal area ATF and the sub code area SUB for the tracking servo are thus provided at the upper and lower portions of each tracking so as to cope with the dropout and to pick up the serve code as much as possible during the high speed search. This is because

A guard area is formed between the areas PCM, ATF, and SUB, and the head and end of each track are margin areas.

In this case, eight subcode blocks are written in each serve code area SUB, but subcodes of the same content are written in the upper and lower areas of one track.

FIG. 6 shows the format of a subcode block. One block of the subcode block is composed of 288 bits like the PCM data block.

As shown in the figure, the first 8 bits of one block are the block synchronization signal, the next 8-bit data W ₁ is the subcode ID, and the next 8-bit data W ₂ is the subcode ID and its block. Address signal, the next 8 bits are data W ₁
And the parity P for error correction generated for W ₂ ,
The remaining 256 bits (consisting of 32 symbols because one symbol is formed by 8 bits) are the subcode data and the error correction parity generated for the subcode data.

More specifically, the 8-bit data W ₁ and W ₂ are as shown in FIG.

That is, the MSB of the data W ₁ is used to identify the block from the subcode block or the PCM data block, and when the block is a subcode block, this becomes “1” as shown in the figure. The lower 4 bits of data W ₂ is a block address, the LSB contents of the subcode ID are different "0" or "1". LSB of block address is "0"
In the case of, data W ₁ is a 4-bit control ID and 4
Made from the data ID of bits, upper three bits of the block address of the data W ₂ is the format ID.

Data W ₁ when LSB of block address is “1”
And the upper 3 bits of the data W ₂ indicate the program number. In this case, the program number is 3 digits
It is represented by a BCD code, and the upper 3 bits PNO-1 of the block address of the data W ₂ is the most significant digit and the upper 4 bits of the data W ₁ .
The bit PNO-2 represents the middle digit and the lower 4 bits PNO-3 represents the lowest digit. The program numbers are represented by [001] to [799]. In addition, [000]
Indicates that the program number is not recorded,
[0AA] indicates that the program number is invalid.

The subcode block whose LSB of the block address is "0" and the subcode block whose value is "1" are alternately recorded by 4 out of 8 blocks in each subcode area SUB.

The control ID is, for example, a 4-bit (4 types)
It consists of an ID (identification signal), and is a table-of-contents identification signal (TOC-ID) for indicating a table of contents, a skip identification signal (SKIP-ID) for skipping unnecessary information, and a program start identification signal for indicating the start of a program. (START-I
D), a priority identification signal (PRIORIT
Y-ID) is included. The method for recording the program start identification signal is disclosed in Japanese Patent Application No. 60-98969 and the method for recording the skip identification signal is disclosed in Japanese Patent Application No. 60-116213.

D Problem to be Solved by the Invention By the way, among such identification signals, the program start identification signal and the skip identification signal are, for example, 9 respectively.
Since only 1 second has been recorded, when trying to erase these, it is difficult to search the recorded location, and when it is erased, it is "0" data recording. However, there is a drawback that the erase start timing is difficult and a small unerased residue occurs.

The present invention has been made in view of the above point, and the trouble of searching, the timing of erasing, starting, and ending by automatically performing the search and the erasing of the position of the program start identification signal or the skip identification signal. The present invention provides a recording / reproducing apparatus that can eliminate the difficulty of the above and eliminate a small unerased portion to surely erase a desired identification signal.

E Means for Solving the Problems The recording / reproducing apparatus according to the present invention detects the identification signal recorded on the tape and stores the address signal in the PCM area on the tracks of the PCM area and the subcode area at that time. Then, the content of the identification signal is changed and re-recorded based on the address signal.

F action Detects the change point of the program start or skip identification signal recorded on the tape. Then, the address signal in the PCM area at the time of this detection, that is, the frame address is stored. Then, after reading this frame address, the after-recording mode is set, and the contents of the identification signal are changed during the after-recording mode to re-record, that is, the program start or skip identification signal is changed from "1" to "0", This "0" is recorded again. As a result, the previously recorded "1" program start or skip identification signal is erased, and the desired identification signal can be erased automatically and reliably.

G Embodiment Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.

G ₁ Circuit Configuration FIG. 1 shows the circuit configuration of this embodiment. In FIG. 1, an analog signal from an input terminal (1) is supplied to an analog-digital converter (3) through a low pass filter (2). After being converted from an analog signal to a digital signal here, it is supplied to the recording signal generating circuit (5) via the contact a side of the switch circuit (4). By switching the switch circuit (4) to the contact b side, a digital signal can be directly supplied from the terminal (6) to the recording signal generating circuit (5).

The recording signal generation circuit (5) performs signal processing such as addition of an error correction code of data, interleaving or modulation based on the timing signal from the timing generation circuit (7), and then performs switching processing on the switching circuit (5). 8). This switch circuit (8) is a rotary magnetic head (11
A) and (11B), which are switched by a switching signal from the timing signal generation circuit (7).
Half rotation period including the tape contact period of the head (11A) The half rotation period including the tape contact period of the head (11B) is alternately switched. The timing generation circuit (7) includes rotary heads (11A), (11
A 30 Hz pulse indicating the rotational transfer of the rotary heads (11A) and (11B) obtained in synchronism with the rotation of the rotary drive mode of (B) is supplied. The signals from the switch circuit (8) switched by the switching signal from the timing generation circuit (7) are amplified by the amplifiers (9A) and (9B), and then the contact points R of the switch circuits (10A) and (10B), respectively. Is supplied to the rotary heads (11A), (11B) via the side, and the reels (12),
It is recorded on the magnetic tape (14) wound between (13).
The switch circuits (10A) and (10B) are connected to the contact R side during recording and switched to the P side during reproduction.

Also, (15A) and (15B) are switch circuits (10
A) and (10B) are amplifiers to which reproduction outputs from the rotary heads (11A) and (11B) which react when they are switched to the contact P side are supplied. Each of these amplifiers (15A) and (15B) The output is supplied to the switch circuit (16). The switch circuit (16) receives a switching signal of 30 Hz from the timing signal generation circuit (7) and performs a half-rotation period including the head contact period of the head (11A) and a tape contact period of the head (11B) in the same manner as during recording. And a half-rotation period including

The output signal switched by the switch circuit (16) is passed through an equalizer (17), a comparator (18), and a PLL circuit (19), which constitute an electromagnetic conversion system, to an error correction circuit (2).
0), where error correction is performed as necessary. Then, the digital signal is further supplied to a digital-analog converter (21), where the digital signal is converted into an analog signal.
3) is taken out as the original analog signal.

When digital data is to be directly taken out, it can be derived from the output terminal (24) of the error correction circuit (20).

A subcode microcomputer (25) serving as an interface is provided on the output side of the error correction circuit (20), and a subcode microcomputer including a program number, a time code, and the like is extracted therefrom. It is supplied to the controller (26). The system controller (26) controls the entire system.

The system controller (26) is provided with a plurality of buttons necessary for operation. Here, only the program start identification signal erasing button (27) and the skip identification signal erasing button (28) are shown as representatives.

A drum servo circuit (30) is controlled by a system controller (26). The drum servo circuit (30) controls a drum (not shown) to which the rotary heads (11A) and (11B) are attached. The rotating drum motor (31) is controlled. Reel (12), (1
A reel drive circuit (32) is provided for the reel motor (3), and a drive signal from the reel drive circuit (32) is supplied to the reel motor (3).
It is supplied to the reels (12) and (13) via 3) and (34), respectively. The reel drive circuit (32) receives a reel motor (3) in response to a mode switching signal from the system controller (26).
Change the level of the drive signal applied to 3) and (34).

Reference numeral (35) denotes a capstan servo circuit controlled by the system controller (26). The capstan servo circuit (35) controls a capstan motor (37) that drives the capstan (36) to rotate. Further, a pinch roller (not shown) for the capstan (36),
A plunger circuit is provided to control this against the elastic force.

(29) is the RF provided on the output side of the switch circuit (16)
An RF envelope detection circuit for detecting an envelope of a signal, the output of the envelope detection circuit (29) being supplied to a system controller (26).

G ₂ data structure When the unit amount of recorded data, which is called 1 segment, is the whole data recorded on one track, 1 segment contains 196 blocks (7500μsec) of data. . Margins (11 blocks) are provided at both ends of one segment corresponding to the end of the track. Subcode 1 and subcode 2 are recorded adjacent to each of the margins. The two subcodes are the same data and are double-recorded. The sub code is a program number and time code. Run PLLs on both sides of the recording area of 8 blocks of subcode.
In section (2 blocks) and post amble section (1
Block) is arranged.

In addition, an inter block gamp that does not record data is provided, sandwiched by an inter block gap of 3 blocks, and pilot signals for ATF are recorded over 5 blocks. Within the 130 block length area in the center of one segment, the recorded PCM signal is recorded in the 128 block length area excluding the 2-block PLL run-in section. This PCM signal is
This is data corresponding to the audio signal during the time when the rotary head makes a half turn.

FIG. 2 shows the data structure of one block of the PCM signal. An 8-bit (1 symbol) blob sync signal is added to the head of one block, and then an 8-bit PCM-ID is added. A block address is added after the PCM-ID. The terms PCM-ID and block 2 symbol address (W ₁ and W _2), the processing of the error correction coding of a simple parity is executed, 8-bit parity is appended to the next block address. As shown in FIG. 3, the block address is composed of 7 bits excluding the most significant bit (MSB). When the most significant bit is set to "0", it indicates that the block is a PCM block.

The 7-bit block address changes sequentially from (00) to (7F) (in hexadecimal). The PCM-ID recorded in each block of the lower 3 bits of the block address is (000) (010) (100) (110) is defined. An optional code of the PC-ID can be recorded in each block address in which the lower 3 bits of the block address are (001) (011) (101) (111). Each PCM-ID has a 2-bit ID 1-
Includes ID8 and 4-bit frame address. ID1 ~ ID
Identification information is defined for each item 7. A pack is composed of 32 ID8s. For example, ID1 is a format ID, and whether it is for audio or other uses is identified by the ID. The ID identifies pre-emphasis on / off and pre-emphasis characteristics, and the ID3 identifies the sampling frequency. . The above-mentioned ID1 to ID7 and the frame address are the same data in the segment of the interleave pair.

G ₃ Operation Description Next, the operation of the present invention will be described with reference to FIG. The operation of erasing the skip identification signal of the program start identification signal is substantially the same, and will be described in parallel.

In FIG. 4, in step (a), the program start identification signal erasing button (27) or the skip identification signal button (28) is pressed to erase the first identification signal (ID). In step (b), the reverse mode of the 3x speed or 16x speed and the none tape (14) are inverted to search for the identification signal. In step (c), the system controller (26) checks whether the identification signal has changed from "1" to "0" via the subcode microcomputer (25). If it does not change, wait until it changes and then change. Then wait for 0.5 seconds in the reversed state in step (d), that is, confirm the system start-up such as ATF locked within 0.5 seconds and step (e)
To enter forward mode.

The system controller (26) checks whether or not the identification signal has changed from "0" to "1" in step (f). If it does not change, wait for it to change. If it changes, change it in step (g). The frame address at the point is stored in the system controller (26). In the case of erasing the skip identification signal, other subcodes such as a program start identification signal for one frame, a program number or a time code are also stored in addition to the frame address.

In step (h), enter the reverse mode and check the frame address stored earlier at 1x speed and return.
In step (i), the system controller (26) checks whether the identification signal changes from "1" to "0" and whether there is a frame address. If NO, continue the operation. If YES, wait 1.5 seconds at step (nu) to see the system start up, and go to forward at step (ru). Then read the frame address and send the tape (14) in the forward direction. Then, in step (wo), the system controller (26) checks whether the frame address currently being read is two frames before the previously stored harem address. If it is not two frames before, wait until two frames before, and if it is two frames before, go to step (wa).

In step (wa), the data of "0" is post-recorded for a predetermined time. That is, in the case of erasing the program start identification signal, a total of 332 frames of the preamble, 300 frames of the program start identification signal, and 30 frames of the postamble are combined.
Data of "0" is post-recorded to the frame. In the case of erasing the skip identification signal, data of "0" is post-recorded for the preamble 2 frames, the skip identification signal 30 frames, and the postamble 3 frames combined 35 frames. In the case of erasing the skip identification signal, the other identification signals stored are post-recorded as they are, and the time code is incremented by interpolation.

In step (f), the system controller (26) determines whether 332 frames have passed if the program start identification signal has been erased, and 35 frames have passed if the skip identification signal had been erased. Then step (Yo) to stop post-recording. Then, in a step (ta), an arbitrary mode such as stop or forward is entered, and a return is made in step (re).

Further, although the frame address is read as described in the erasing operation suspension, the operation cannot be continued because the signal cannot be read in the portion where the signal is not recorded. Therefore, in the present embodiment, the operation in the signalless portion is enabled by immediately entering the forward mode when the signal enters the signalless portion. That is, when the RF signal supplied from the envelope detection circuit (29) to the system controller (26) in step (SO) disappears,
It is confirmed in the system controller (26) whether or not the step (z) identification signal is being erased, and if so, whether or not the forward mode is immediately entered in step (ne) and the ATF lock is performed in step (na). It is judged by the system controller (26) and if it is not ATF locked, it waits until it locks, and when it locks, it proceeds to step (wa) and thereafter the same operation as described above is repeated. If the identification signal is not being erased in step (tsu), the process immediately proceeds to step (ra) and returns.

H Effect of the Invention As described above, according to the present invention, the identification signal recorded on the tape is detected, the address signal in the PCM area at that time is recorded, and the content of the identification signal is changed based on this address signal. Since the data is re-recorded by the above, the identification signal can be automatically and surely erased, and a small unerased residue does not occur.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a data configuration used in the present invention, and FIG. 4 is a flow chart for operation of the present invention. FIG. 5 is a diagram showing an example of a table format used in a rotary head type PCM audio signal recording / reproducing apparatus, and FIG. 6 is a diagram showing an example of a format of a configuration recorded in a subcode area of a recording track. (5) is a recording signal generating circuit, (11A) and (11B) are rotary heads, (12) and (13) are reels, (14) is a magnetic tape,
(20) is an error correction circuit, (25) is a subcode microcomputer, (26) is a system controller, (27) is a program start identification signal erasing button, (28) is a skip identification signal erasing button, (29). Is an RF envelope detection circuit, (30) is a drum servo circuit, (31) is a drum motor, (32) is a reel drive circuit, (33) and (34) are reel motors, (35) is a capstan servo circuit, ( 37)
Is a capstan motor.

Claims (1)

(57) [Claims] 1. A recording / reproducing apparatus for erasing the identification signal from a recording medium on which an information program and an identification signal of the information program are recorded, and a detecting means for detecting a head address where the identification signal is recorded. A transfer means for transferring the recording medium until a leading address of the identification signal is detected by the detecting means, a storage means for storing the leading address of the identification signal detected by the detecting means, A recording / reproducing apparatus comprising: an identification signal erasing means for erasing the identification signal for a predetermined time based on the start address of the identification signal stored in the storage means.