JP2546472B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2546472B2 JP2546472B2 JP4257759A JP25775992A JP2546472B2 JP 2546472 B2 JP2546472 B2 JP 2546472B2 JP 4257759 A JP4257759 A JP 4257759A JP 25775992 A JP25775992 A JP 25775992A JP 2546472 B2 JP2546472 B2 JP 2546472B2
- Authority
- JP
- Japan
- Prior art keywords
- tab
- hole
- resin
- semiconductor element
- element mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明はリードフレーム及び半導
FIELD OF THE INVENTION The present invention relates to lead frames and semiconductors.
【産業上の利用分野】本発明はリードフレーム及び半導
体装置に係り、特にリフロー半田付け時の加熱による樹
脂クラック防止に好適な半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a lead frame and a semiconductor device, and more particularly to a semiconductor device suitable for preventing resin cracks due to heating during reflow soldering.
【０００２】[0002]
【従来の技術】樹脂封止型の半導体装置では従来のピン
挿入タイプに代わり、基板に直接リードを半田付けする
面付け実装タイプが主流になりつつある。このようなパ
ッケージでは、高温高湿環境で保存すると樹脂が水分を
吸収し、半田付け加熱時（リフロー時）に水分がタブ
（素子搭載部のこと。以下本願において同じ。）と樹脂
部との界面で蒸気になり、タブ下面コーナ部にクラック
が生じ易い。このクラックは、半田リフロー時に発生す
る為、俗にリフロークラックと呼ばれている。2. Description of the Related Art In a resin-encapsulated semiconductor device, an imposition mounting type in which leads are directly soldered to a substrate is becoming the mainstream instead of the conventional pin insertion type. In such a package, when stored in a high-temperature, high-humidity environment, the resin absorbs moisture, and when soldering is heated (during reflow), the moisture is spread between the tab (the element mounting portion; the same applies to the present application in the following). It becomes steam at the interface, and cracks are likely to occur at the corners on the lower surface of the tab. This crack is generally called a reflow crack because it occurs during solder reflow.
【０００３】このようなリフロークラックを防止する従
来技術としては、特開昭６０−２０８８４７号公報に記
載のようにパッケージの裏面に穴をあけ、発生する蒸気
を逃がす方法がある。As a conventional technique for preventing such a reflow crack, there is a method of making a hole in the back surface of a package and releasing generated steam as described in Japanese Patent Application Laid-Open No. 60-208847.
【０００４】また、樹脂部とタブの界面の接着強さを向
上させ、すきまを防止する技術として、タブの反素子搭
載面（素子搭載側面の裏側に当たる面のこと。以下同
じ。）に凹凸を設ける方法として特開昭５８−１９９５
４８号公報、同６０−１８６０４４号公報に示される技
術、更にタブ相当部に穴を形成したものとして同５９−
１６３５７号公報、実開昭６０−１１８２５２号公報に
する課題】上記従来技術のうち、パッケージ下面に穴を
あける方法は、リフロークラックは妨げるもののパッケ
ージ外部と内部に水分の通路を作ることになり、チップ
電極の腐食が生じる可能性がある。As a technique for improving the adhesive strength at the interface between the resin portion and the tab and preventing the clearance, unevenness is formed on a surface opposite to the element mounting surface of the tab (the surface which is on the back side of the element mounting side surface; the same applies hereinafter). Japanese Patent Application Laid-Open No. 58-1995 describes
No. 48, No. 60-186044, and Japanese Patent Application Laid-Open No.
Among the above-mentioned conventional techniques, the method of making a hole in the lower surface of the package, although it prevents reflow cracks, creates moisture passages inside and outside the package. Corrosion of the tip electrode may occur.
【０００６】また、タブの反素子搭載面に単純な凹凸を
設ける方法は、タブと樹脂部との接着面内の変位を拘束
する効果はあるものの、両者を引き離す方向の変位につ
いては、凹部に入り込んだ樹脂部が簡単に抜けるために
効果が期待できない。Further, the method of providing the concave and convex portions on the opposite element mounting surface of the tab has an effect of restraining the displacement in the bonding surface between the tab and the resin portion. The effect cannot be expected because the resin part which has entered easily comes off.
【０００７】樹脂封止半導体をリフロー半田付けする際
に、樹脂中に含まれた水分が気化して、この蒸気圧がタ
ブ〜樹脂界面にあるボイド又は非接着部等の空孔作用を
し、タブ〜樹脂界面の剥離を進行させる。剥離進行によ
って空孔が大きくなっても、周囲の水分が拡散により供
給され、この結果、空孔の圧力は緩和されず、樹脂部は
変形し、タブ端部の最大応力発生個所を起点にクラック
を生じる（図４のクラック１０参照。）。When the resin-encapsulated semiconductor is reflow-soldered, water contained in the resin is vaporized, and the vapor pressure acts as a void such as a void or a non-adhesion portion at the interface between the tab and the resin. The separation between the tab and the resin interface is advanced. Even if the pores become large due to the progress of peeling, the surrounding moisture is supplied by diffusion, as a result, the pressure in the pores is not relaxed, the resin part deforms, and cracks start from the point where the maximum stress occurs at the tab end. (See crack 10 in FIG. 4).
【０００８】前記の特開昭５９−１６３５７号公報では
タブの一部を抜き去り、この部分に樹脂を充填する技術
が開示されている。この技術を用いて熱応力による剥離
を防ぐとともに、等価的に樹脂部の厚さを増大させるこ
とにより、耐湿性の向上がある程度は図れる。しかし、
リフロー半田付け時の蒸気圧により、樹脂部がタブから
剥離した場合に生ずる変形により、最大応力発生個所の
応力はタブの一部が抜き去られない場合と大差なく、こ
の構造では、リフロー半田付けの際の樹脂部割れに対す
る効果は充分ではない。The above-mentioned Japanese Patent Laid-Open No. 59-16357 discloses a technique of removing a part of the tab and filling the part with resin. By using this technique to prevent peeling due to thermal stress and by equivalently increasing the thickness of the resin portion, the moisture resistance can be improved to some extent. But,
Due to the deformation that occurs when the resin part peels off from the tab due to the vapor pressure during reflow soldering, the stress at the point of maximum stress generation is not much different from the case where a part of the tab is not removed. In this case, the effect on cracking of the resin part is not sufficient.
【０００９】実開昭６０−１１８２５２号公報に記載の
技術では封止樹脂を係止する貫通穴として裏面側から表
面側に向かって広くなる構造が示されているが、このよ
うな単純構造では貫通穴の板厚内に確実に樹脂を係止す
ることは難しい。In the technique disclosed in Japanese Utility Model Application Laid-Open No. 60-118252, a structure is shown in which a through hole for locking the sealing resin is widened from the back side to the front side. It is difficult to reliably lock the resin within the thickness of the through hole.
【００１０】本発明の目的は蒸気圧により生じる樹脂ク
ラックを防止することにある。An object of the present invention is to prevent resin black caused by vapor pressure.
【００１１】[0011]
【課題を解決するための手段】上記目的は、タブに特殊
な形状の貫通穴を設け、この穴により樹脂部をタブに拘
束し、リフロークラックが生じるタブ下面コーナ部の樹
脂部に発生する応力を低減することにより達成される。SUMMARY OF THE INVENTION It is an object of the present invention to provide a through-hole having a special shape in a tab, by which the resin portion is restrained by the tab, and a stress generated in a resin portion of a tab lower surface corner portion where a reflow crack occurs. Is achieved by reducing
【００１２】リフロー半田付けの際の樹脂クラックを防
ぐには、樹脂部とタブが剥離しても、タブ端の最大応力
発生個所に大きな応力が生じないようにする必要があ
る。この要求は、樹脂部とタブに付着力がなくなった場
合でも、樹脂部の変形を防ぎ得る構造、すなわち樹脂部
が蒸気圧によりタブから抜け出ない係止構造にすること
により達成できる。In order to prevent a resin crack during reflow soldering, it is necessary to prevent a large stress from being generated at the maximum stress generating portion at the tab end even when the resin portion and the tab are separated. This requirement can be achieved by providing a structure that can prevent deformation of the resin portion even when the adhesive force between the resin portion and the tab is lost, that is, a locking structure in which the resin portion does not come out of the tab due to vapor pressure.
【００１３】[0013]
【００１４】[0014]
【００１５】 本願第１番目の半導体装置の発明は、半
導体素子と、半導体素子を搭載しかつ半導体素子が搭載
される部位直下に形成された１個或いは複数個の貫通穴
付きのタブと、タブの周辺に配置したリード群と、リー
ド群の内のインナーリード部及びタブ並びに半導体素子
を封止する樹脂部とを備えた半導体装置において、貫通
穴内に、封止されるべき樹脂の移動を抑制できる程度に
素子搭載面側開口部面積及び素子搭載面とは反対側の開
口部面積の何れよりも断面積が小さくなる部分を有する
ことを特徴とする。 The first semiconductor device invention of the present application is
Conductor element and semiconductor element are mounted and semiconductor element is mounted
One or more through holes formed directly below
Tabs with leads, leads arranged around the tabs, and leads
Of inner leads and tabs in semiconductor group and semiconductor element
A semiconductor device having a resin portion for sealing
To the extent that the movement of the resin to be sealed can be suppressed in the hole
Element mounting surface side opening area and opening on the side opposite to the element mounting surface
It is characterized by having a portion whose cross-sectional area is smaller than any of the mouth area .
【００１６】 本願第２番目の半導体装置の発明は、半
導体素子と、半導体素子を搭載しかつ半導体素子搭載面
側開口部面積が反素子搭載面側開口部面積よりも大きい
１個或いは複数個の貫通穴付きのタブと、タブの周辺に
配置したリード群と、リード群の内のインナーリード部
及びタブ並びに半導体素子を封止する樹脂部とを備えた
半導体装置において、貫通穴内に、封止されるべき樹脂
の移動を抑制できる程度に、段部を形成したことを特徴
とする。 A second semiconductor device invention of the present application is
Conductor element and semiconductor element mounting surface and semiconductor element mounting surface
Side opening area is larger than the counter element mounting surface side opening area
One or more tabs with through holes and around the tabs
The arranged lead group and the inner lead part of the lead group
And a tab and a resin portion for sealing the semiconductor element.
Resin to be sealed in the through hole in a semiconductor device
Characterized by forming a step to the extent that movement of the
And
【００１７】この貫通穴は、タブの板厚方向に対して全
体に傾斜している（テーパ部を有する）態様、タブの板
厚内にくびれ部を形成している態様等が挙げられる。ま
た、タブの少なくとも一箇所に素子搭載面側開口面積が
素子搭載面の裏側面の開口面積よりも大となるような貫
通穴に限られず、板厚内に封止樹脂の一部が確実に係止
されれば有効である。The through hole may be inclined (having a tapered portion) with respect to the plate thickness direction of the tab, or may be formed with a constricted portion within the plate thickness of the tab. Further, the opening area on the element mounting surface side is not limited to at least one portion of the tab that is larger than the opening area on the back side surface of the element mounting surface. It is effective if locked.
【００１８】貫通穴の素子搭載面側面積はタブの素子搭
載面側面積の２４％以上からタブと素子との接合面積の
８０％以下の範囲にあることが望ましく、またタブの素
子搭載面の貫通穴の周囲には溝を設けることが好まし
い。The area of the through hole on the element mounting surface side is preferably in the range of 24% or more of the area on the element mounting surface side of the tab to 80% or less of the joining area of the tab and the element. It is preferable to provide a groove around the through hole.
【００１９】[0019]
【作用】リフロークラックが生じるタブ下面コーナ部の
樹脂部の応力を概略的に求めるには、タブ下方の樹脂部
を図３に示すように一様の圧力がかかる周辺拘束の長方
形平板にモデル化すれば良い。このとき、最大の応力
は、長辺中央に発生し、その値は次式（数１）で与えら
れる。[Function] In order to roughly determine the stress of the resin portion at the corner portion of the tab lower surface where the reflow crack occurs, the resin portion under the tab is modeled as a rectangular flat plate with peripheral restraint to which uniform pressure is applied as shown in FIG. Just do it. At this time, the maximum stress occurs at the center of the long side, and its value is given by the following equation (Equation 1).
【００２０】[0020]
【数１】 [Equation 1]
【００２１】ここで、βは長辺と短辺の長さの比で決ま
る応力係数、ａは短辺の長さ、ｈは板厚、ｐは水蒸気の
圧力を表わす。（数１）式から明らかなように、タブサ
イズａの２乗で発生応力は増加する。従って素子寸法が
大きくなると、半田リフロークラック（図４符号１０）
が生じ易くなる。それ故、応力を低減するには、短辺の
長さを短くするか、或いは板厚を厚くすれば良い。Here, β is a stress coefficient determined by the ratio of the length of the long side to the length of the short side, a is the length of the short side, h is the plate thickness, and p is the pressure of water vapor. As is clear from equation (1), the generated stress increases with the square of the tab size a. Therefore, when the element size becomes large, solder reflow crack (10 in Fig. 4)
Is more likely to occur. Therefore, in order to reduce the stress, the length of the short side may be reduced or the plate thickness may be increased.
【００２２】ところが、板厚を厚くするということは、
パッケージを厚くすることになり、例えばフラットパッ
ケージのように薄型を特徴とするパッケージには適用で
きない。また、タブの寸法は、チップの寸法より小さく
できないので、チップ寸法により決定される。However, increasing the plate thickness means that
This means that the package is made thicker and cannot be applied to a package that is characterized by being thinner, for example, a flat package. In addition, the size of the tab cannot be smaller than the size of the chip, and thus is determined by the chip size.
【００２３】そこで本発明では、タブの一部に樹脂拘束
部を設け、タブの剥離部分を分割した。これにより、実
効的なタブ寸法ａが小さくなるので、タブ下面コーナ部
の樹脂の応力が低減し、この部分の樹脂に発生するリフ
ロークラックを防止することができる。Therefore, in the present invention, a resin restraining portion is provided on a part of the tab and the peeled portion of the tab is divided. Thus, since the effective tab size a becomes small, the tab lower surface corner portion
The stress of the resin is reduced, and it is possible to prevent the reflow crack generated in the resin in this portion .
【００２４】また、本発明では反素子搭載側のタブから
貫通穴に入る角度が大きくなるので、リフロー時にこの
部分の樹脂に発生する応力も大きくならず、この部分か
ら発生する樹脂クラックも防止することができる。 Further , in the present invention, from the tab on the side opposite to the element mounting side
Since the angle entering the through hole becomes large, this
The stress generated in the resin of the part does not become large,
It is also possible to prevent resin cracks from occurring.
【００２５】[0025]
【実施例】以下、本発明のリードフレーム及び半導体装
置の実施例をその原理、比較例とともに図面に従って説
明する。Embodiments of the lead frame and semiconductor device of the present invention will be described below with reference to the drawings along with their principles and comparative examples.
【００２６】図１は実施例に係るリードフレームを用い
た面付け実装型半導体装置の断面図である。◆タブ１は
その両端をタブ吊りリード３にて支吊され、略中央に貫
通穴２を形成している。この貫通穴２は図１の断面から
も明らかなように素子４方向に次第に広がり、素子４と
は反対の側にくびれている。尚、図１において符号５は
樹脂部、６は水蒸気、７はリード、８は半田、９は基板
を示す。FIG. 1 is a sectional view of a surface-mounting type semiconductor device using a lead frame according to an embodiment. The tab 1 has both ends thereof suspended by tab suspension leads 3, and a through hole 2 is formed substantially at the center. As is clear from the cross section of FIG. 1, this through hole 2 gradually expands in the direction of the element 4 and is constricted on the side opposite to the element 4. In FIG. 1, reference numeral 5 is a resin portion, 6 is water vapor, 7 is a lead, 8 is solder, and 9 is a substrate.
【００２７】タブ１と樹脂部５の界面に水蒸気６が発生
し、この圧力により、樹脂部５が膨らんでいる。このと
き、タブ下面コーナ部の樹脂部５に応力が発生するが、
本例によるタブ１の貫通穴２が樹脂部５を拘束するの
で、図１と図４（従来図）を比較してわかるように、ａ
寸法は従来のタブの２分の１以下になる。従って、（数
１）式より発生する応力を４分の１以下に低減すること
ができ、リフロークラックが防止できる。Water vapor 6 is generated at the interface between the tab 1 and the resin portion 5, and the pressure causes the resin portion 5 to swell. At this time, stress is generated in the resin portion 5 in the corner portion of the lower surface of the tab.
Since the through hole 2 of the tab 1 according to this example restrains the resin portion 5, as shown in a comparison between FIG. 1 and FIG. 4 (conventional view), a
The dimensions are less than half that of a conventional tab. Therefore, the stress generated from the equation (1) can be reduced to a quarter or less, and reflow crack can be prevented.
【００２８】本発明の第１実施例を図２に示す。本実施
例では、貫通穴２の反素子搭載面における面積よりも小
さい面積の部分が貫通穴２の内部に設けられている。実
施例においては樹脂部が貫通穴２に入り込んでタブ１に
樹脂部が拘束されるので、リフロークラックの防止が確
実に図れることになる。A first embodiment of the present invention is shown in FIG. In the present embodiment, a portion having an area smaller than the area of the through hole 2 on the surface opposite to the element mounting surface is provided inside the through hole 2. In the embodiment, the resin portion enters the through hole 2 and is restrained by the tab 1, so that the reflow crack can be surely prevented.
【００２９】本発明の貫通穴の平面形状は、図１から図
２に示すような円形である必要はなく、楕円形、矩形、
十字型でも同様の効果がある。また、貫通穴の数は、タ
ブ１に必要な剛性を損なわない程度に複数個設けること
により、より一層の効果を上げることができる。The planar shape of the through hole of the present invention does not have to be circular as shown in FIGS. 1 and 2, but may be elliptical, rectangular,
The same effect can be obtained with a cross shape. Further, by providing a plurality of through holes so that the tab 1 does not impair the required rigidity, the effect can be further enhanced.
【００３０】貫通穴に入り込んだ樹脂部に生じる応力σ
hは、（数２）式で表わされる。Stress σ generated in the resin portion that has entered the through hole
h is represented by the equation (2).
【００３１】[0031]
【数２】 [Equation 2]
【００３２】ここで、Ａtはタブの面積、Ａhは穴の内側
の面積の最小値である。この応力が樹脂部の破壊応力σ
Bを超えると、樹脂部が破壊するので、（数３）式、従
って（数４）式が成り立たなくてはならない。Here, A t is the area of the tab and A h is the minimum value of the area inside the hole. This stress is the fracture stress σ of the resin part
If B is exceeded, the resin portion is destroyed, so that equation (3), and therefore equation (4), must be satisfied.
【００３３】[0033]
【数３】 (Equation 3)
【００３４】[0034]
【数４】 [Equation 4]
【００３５】通常、半田リフロー時には、パッケージは
約２２０℃に加熱され、この温度における水の飽和蒸気
圧は０．２４ｋｇｆ／ｍｍ2である。また、この温度に
おける樹脂部の破壊応力は約１ｋｇｆ／ｍｍ2であるか
ら、これらの値を（数４）式に代入すると（数５）式と
なる。Normally, during solder reflow, the package is heated to about 220 ° C., and the saturated vapor pressure of water at this temperature is 0.24 kgf / mm 2 . Further, since the breaking stress of the resin portion at this temperature is about 1 kgf / mm 2 , when these values are substituted into Expression (4), Expression (5) is obtained.
【００３６】[0036]
【数５】 (Equation 5)
【００３７】すなわち、穴の最小面積は、タブの面積の
２４％以上にすることが望ましい。◆また貫通穴が過度
に大きくなるとタブの剛性が低下するので、チップ搭載
面に凹凸が生じ、チップとタブとの接合が困難となる。
更にワイヤボンディングの際に、タブの反素子搭載面か
ら加える熱が、チップに伝わりにくなる。従って貫通穴
の大きさに最適には上限があり、本発明者等の実験確認
によれば貫通穴の面積は搭載するチップの８０％以下が
望ましい。上記穴の範囲は各貫通穴毎にもまた貫通穴の
合計に対しても適用し得る。That is, the minimum area of the holes is preferably 24% or more of the area of the tab. ◆ Also, if the through hole becomes too large, the rigidity of the tab will decrease, and the chip mounting surface will become uneven, making it difficult to bond the chip and the tab.
Further, during wire bonding, the heat applied from the surface of the tab opposite to the element mounting becomes difficult to be transferred to the chip. Therefore, there is an upper limit to the size of the through hole, and according to experiments confirmed by the present inventors, the area of the through hole is desirably 80% or less of the mounted chip. The above range of holes can be applied to each through hole as well as to the total of the through holes.
【００３８】次に、本発明による貫通穴の製造方法につ
いて述べる。Next, a method of manufacturing a through hole according to the present invention will be described.
【００３９】図５にエッチング技術でタブに貫通穴をあ
ける方法を示す。タブの両側に同一形状のエッチングパ
ターン１４ａ，１４ｂを密着し、エッチング液１５の中
に浸漬する。エッチングは、タブの両面から進行する
が、その進行具合によっては図６のように、わずかに中
央部が狭い穴となり、これでは、穴の内側の面積はほと
んど一様なので、樹脂が入り込んでも、これを拘束する
には至らない。これに対し、本発明は確実に係止穴が形
成されるべきである。FIG. 5 shows a method of forming a through hole in the tab by the etching technique. Etching patterns 14a and 14b having the same shape are adhered to both sides of the tab and immersed in the etching solution 15. Although the etching progresses from both sides of the tab, depending on the progress thereof, a slightly narrow hole is formed at the center as shown in FIG. 6, and since the inner area of the hole is almost uniform, even if resin enters, There is no way to restrain this. On the other hand, in the present invention, the locking hole should be surely formed.
【００４０】そこで、図６の工程をベースとして両面か
らのエッチングを途中で止めればその処理（エッチング
の処理液の濃度や時間）の程度によってくびれ部を板厚
内に形成することも可能となり、本発明の実施例に係る
リードフレームの製造にも流用可能である。Therefore, by stopping the etching from both sides based on the process of FIG. 6, it is possible to form the constricted portion within the plate thickness depending on the degree of the treatment (concentration and time of the treating liquid for etching). It can also be used for manufacturing the lead frame according to the embodiment of the present invention.
【００４１】図７，図８に、本発明の第２実施例とその
貫通穴をあける方法を示す。図７のタブ上面のエッチン
グパターン１４ｃの穴は、下面のエッチングパターン１
４ｄの穴より大きい。このような状態でエッチング液１
５に浸漬すると、図８のようなくびれ部のある穴があく
ので、本実施例の貫通穴を実現することができる。FIG. 7 and FIG. 8 show a second embodiment of the present invention and a method of making a through hole. The holes of the etching pattern 14c on the upper surface of the tab in FIG.
Larger than 4d hole. Etching solution 1 in this state
When immersed in No. 5, a hole having a constriction is formed as shown in FIG. 8 , so that the through hole of this embodiment can be realized.
【００４２】図９，図１０に、本発明の第３実施例とそ
の貫通穴をあける方法を示す。図９のタブ上面のエッチ
ングパターン１４ｅ，１４ｆの穴の大きさは等しいが、
位置がずれている。従って、図１０のように、タブに対
して斜めにあいたくびれ部のある穴、すなわち本実施例
の貫通穴を実現することができる。FIGS. 9 and 10 show a third embodiment of the present invention and a method of forming a through hole. Although the size of the holes of the etching patterns 14e and 14f on the tab upper surface of FIG.
The position is incorrect. Therefore, as shown in FIG. 10, it is possible to realize a hole having a constricted portion that is oblique to the tab, that is, the through hole of the present embodiment.
【００４３】図１１に、本発明の第４の実施例とその貫
通穴をあける方法を示す。本実施例はプレスにより本発
明を実現する方法である。まず、従来の技術により、タ
ブに貫通穴を開け、この部分に凸型のプレス金型１６ａ
をプレスする。この方法により、図１２に示すように、
反素子搭載面における穴の内側の面積よりも大きな面積
の部分を持つ段付きの穴を設けることができる。FIG. 11 shows a fourth embodiment of the present invention and a method of making a through hole. The present embodiment is a method for realizing the present invention by pressing. First, according to the conventional technique, a through hole is formed in the tab, and a convex press die 16a is formed in this portion.
To press. By this method, as shown in FIG.
It is possible to provide a stepped hole having a portion having an area larger than the area inside the hole on the anti-element mounting surface.
【００４４】次に本発明の第５実施例を図１３及び図１
４に基づいて説明する。タブの貫通穴は、素子搭載面側
は反素子搭載面側よりも穴径が大きい。また本実施例で
は減肉部１７が形成され、これが板厚内で段付き部とな
り、封止樹脂を確実に係止している。更に穴は複数設け
られている。尚、符号１８はダイボンディング材であ
る。Next, a fifth embodiment of the present invention will be described with reference to FIGS.
4 will be described. The through hole of the tab has a larger hole diameter on the element mounting surface side than on the non-element mounting surface side. Further, in this embodiment, a thinned portion 17 is formed, which becomes a stepped portion within the plate thickness, and securely locks the sealing resin. Further, a plurality of holes are provided. Reference numeral 18 is a die bonding material.
【００４５】図１３はタブ１に貫通穴２を設け、かつ、
タブ１上部に減肉部１７を設けて段付き部を形成したも
のである。この構造によれば、ダイボンディング材１８
が素子４とタブ１の間を完全に埋めていても樹脂部５は
タブ上部に充填される。リフロー半田付けの際にタブ１
と樹脂部５が剥離しても、タブ上部に充填された樹脂部
の為、樹脂部５はタブ１から抜け出ることはなく、蒸気
圧による変形は図１４のようになる。ここで、タブ残存
部の最大幅ｄを次の式で与えられる値以下にすれば、樹
脂部にクラックは生じない。FIG. 13 shows a tab 1 provided with a through hole 2 and
A stepped portion is formed by providing a thinned portion 17 above the tab 1. According to this structure, the die bonding material 18
Fills the space between the element 4 and the tab 1 completely, the resin portion 5 fills the upper portion of the tab. Tab 1 for reflow soldering
Even if the resin part 5 is peeled off, the resin part 5 does not come out of the tab 1 because it is the resin part filled in the upper part of the tab, and the deformation due to the vapor pressure is as shown in FIG. Here, if the maximum width d of the tab remaining portion is set to be equal to or less than the value given by the following equation, no crack is generated in the resin portion.
【００４６】[0046]
【数６】 (Equation 6)
【００４７】ここで、ＫICはリフロー温度における樹脂
の破壊靭性値であり、ｐはリフロー時に発生する蒸気圧
である。Here, K IC is the fracture toughness value of the resin at the reflow temperature, and p is the vapor pressure generated during the reflow.
【００４８】以上の各実施例等において述べた貫通穴２
は円形でもよいが、矩形に近い形または図１５に示すよ
うな長円に近い形の方が補強効果は大である。Through hole 2 described in each of the above embodiments
May have a circular shape, but a shape closer to a rectangle or a shape close to an ellipse as shown in FIG. 15 has a larger reinforcing effect.
【００４９】[0049]
【発明の効果】本発明によれば、タブと樹脂部が剥離し
たときのタブ下方の樹脂部を拘束する距離が短くなるの
で、水蒸気の圧力による樹脂部の応力が低減し、リフロ
ークラックを防止することができる。また、エッチング
やプレス加工により簡単に封止樹脂の係止部を備える貫
通穴を作成することができる。そして、その貫通穴をく
びれ形状或いは段付き形状としたことにより、反素子搭
載面側のタブから貫通穴に入る角度が緩やかになり、蒸
気圧により封止樹脂が反素子搭載面側に引っ張られたと
きの、反素子搭載面側の開口部付近の樹脂への応力集中
が小さくなり、この部分の樹脂が破壊されることが他の
形状と比べ少なくなる。According to the present invention, when the tab and the resin portion are separated, the distance for restraining the resin portion under the tab is shortened, so that the stress of the resin portion due to the pressure of water vapor is reduced and reflow cracks are prevented. can do. Moreover, the through hole provided with the locking portion of the sealing resin can be easily formed by etching or pressing. Then, by forming the through hole into a constricted shape or a stepped shape, anti-element mounting is performed.
When the sealing resin enters the through hole from the tab on the mounting surface side and the sealing resin is pulled by the vapor pressure toward the anti-element mounting surface side , stress concentration on the resin near the opening on the anti-element mounting surface side Is smaller, and the resin in this portion is less likely to be destroyed than other shapes.
【図１】本発明の実施例に係るリードフレームを用いた
面付け実装型半導体装置の断面図である。FIG. 1 is a cross-sectional view of an imposition mounting type semiconductor device using a lead frame according to an embodiment of the present invention.
【図２】本発明の実施例に係るリードフレームの断面図
である。FIG. 2 is a sectional view of a lead frame according to an embodiment of the present invention.
【図３】リードフレームの応力計算に用いる計算モデル
の斜視図である。FIG. 3 is a perspective view of a calculation model used for stress calculation of a lead frame.
【図４】従来例に係る半導体装置の断面図である。FIG. 4 is a sectional view of a semiconductor device according to a conventional example.
【図５】リードフレームの貫通穴形成工程を示す部分断
面図である。FIG. 5 is a partial cross-sectional view showing a step of forming a through hole of a lead frame.
【図６】図５の貫通穴形成工程を経て得られるリードフ
レームの部分断面図である。6 is a partial cross-sectional view of a lead frame obtained through the through hole forming step of FIG.
【図７】本発明の実施例に係るリードフレームの貫通穴
形成工程を示す部分断面図である。FIG. 7 is a partial cross-sectional view showing a through-hole forming step of the lead frame according to the example of the present invention.
【図８】図７の貫通穴形成工程を経て得られるリードフ
レームの部分断面図である。8 is a partial cross-sectional view of a lead frame obtained through the through hole forming step of FIG.
【図９】本発明の実施例に係るリードフレームの貫通穴
形成工程を示す部分断面図である。FIG. 9 is a partial cross-sectional view showing a step of forming a through hole in a lead frame according to the embodiment of the present invention.
【図１０】図９の貫通穴形成工程を経て得られるリード
フレームの部分断面図である。FIG. 10 is a partial cross-sectional view of the lead frame obtained through the through hole forming step of FIG. 9;
【図１１】本発明の実施例に係るリードフレームの貫通
穴形成工程をプレス金型とともに示す部分断面図であ
る。FIG. 11 is a partial cross-sectional view showing the through-hole forming step of the lead frame according to the embodiment of the present invention together with a press die.
【図１２】図１１の貫通穴形成工程を経て得られるリー
ドフレームの部分断面図である。12 is a partial cross-sectional view of a lead frame obtained through the through hole forming step of FIG.
【図１３】本発明の実施例に係る半導体装置の断面図で
ある。FIG. 13 is a sectional view of a semiconductor device according to an example of the present invention.
【図１４】本発明の実施例に係る半導体装置の断面図で
ある。FIG. 14 is a sectional view of a semiconductor device according to an example of the present invention.
【図１５】本発明の実施例に係るリードフレームの斜視
図である。FIG. 15 is a perspective view of a lead frame according to an embodiment of the present invention.
１…タブ、２…貫通穴、３…タブ吊りリード、４…素
子、５…樹脂部、６…水蒸気、７…リード、８…半田、
９…基板、１８…ダイボンディング材、１９…接着剤流
出防止溝。DESCRIPTION OF SYMBOLS 1 ... Tab, 2 ... Through-hole, 3 ... Tab suspension lead, 4 ... Element, 5 ... Resin part, 6 ... Water vapor, 7 ... Lead, 8 ... Solder,
9: substrate, 18: die bonding material, 19: adhesive outflow prevention groove.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 三浦 英生 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 立道 昭弘 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 北林 千加子 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 清水 一男 群馬県高崎市西横手町111番地 株式会 社 日立製作所 高崎工場内 (72)発明者 初田 俊雄 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 尾崎 敏範 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 服部 敏雄 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 (72)発明者 坂田 荘司 茨城県土浦市神立町502番地 株式会社 日立製作所 機械研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hideo Miura 502 Kandate-cho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratory, Hitachi, Ltd. In-house (72) Inventor Chikako Kitabayashi 502, Kandamachi, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratory, Hitachi, Ltd. (72) Inventor Kazuo Shimizu 111, Nishiyokote-cho, Takasaki-shi, Gunma Pref. Hitachi, Ltd. Inventor Toshio Hatsuda 502 Kandate-cho, Tsuchiura-shi, Ibaraki Pref.Hitachi, Ltd.Mechanical Laboratory (72) Inventor Toshinori Ozaki 502, Tsuchiura-City, Tsuchiura-City, Ibaraki Pref.Hitachi, Ltd. 502, Kandachi-cho, Tsuchiura-shi, Japan Machinery Research Laboratory, Hitachi, Ltd. (72) Inventor Shoji Sakata 502, Kamidate-cho, Tsuchiura-shi, Ibaraki Hitachi Co., Ltd. Mechanical Engineering Laboratory
Claims (2)
前記半導体素子が搭載される部位直下に形成された１個
或いは複数個の貫通穴付きのタブと、該タブの周辺に配
置したリード群と、該リード群の内のインナーリード部
及び前記タブ並びに前記半導体素子を封止する樹脂部と
を備えた半導体装置において、 前記貫通穴内に、封止されるべき樹脂の移動を抑制でき
る程度に前記素子搭載面側開口部面積及び前記素子搭載
面とは反対側の開口部面積の何れよりも断面積が小さく
なる部分を有する半導体装置。 1. A semiconductor element, and a semiconductor element mounted on the semiconductor element,
One formed just below the part where the semiconductor element is mounted
Alternatively, a tab with a plurality of through holes and
Placed lead group and the inner lead portion of the lead group
And a resin portion for sealing the tab and the semiconductor element
In the semiconductor device including, it is possible to suppress the movement of the resin to be sealed in the through hole.
To the extent that the element mounting surface side opening area and the element mounting
The cross-sectional area is smaller than any of the opening areas on the side opposite the surface
Device having a portion to be formed.
前記半導体素子搭載面側開口部面積が素子搭載面とは反
対側の開口部面積よりも大きい１個或いは複数個の貫通
穴付きのタブと、該タブの周辺に配置したリード群と、
該リード群の内のインナーリード部及び前記タブ並びに
前記半導体素子を封止する樹脂部とを備えた半導体装置
において、 前記貫通穴内に、封止されるべき樹脂の移動を抑制でき
る程度に、段部を形成した半導体装置。 2. A semiconductor element, and a semiconductor element mounted on the semiconductor element,
The opening area of the semiconductor element mounting surface side is opposite to the element mounting surface.
One or more penetrations larger than the opening area on the opposite side
A tab with a hole and a lead group arranged around the tab,
An inner lead portion of the lead group, the tab, and
A semiconductor device including a resin portion for encapsulating the semiconductor element
In, the movement of the resin to be sealed can be suppressed in the through hole.
A semiconductor device in which a step is formed to the extent that
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4257759A JP2546472B2 (en) | 1992-09-28 | 1992-09-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4257759A JP2546472B2 (en) | 1992-09-28 | 1992-09-28 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7101905A Division JP2570209B2 (en) | 1995-04-26 | 1995-04-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0629448A JPH0629448A (en) | 1994-02-04 |
| JP2546472B2 true JP2546472B2 (en) | 1996-10-23 |
Family
ID=17310706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4257759A Expired - Lifetime JP2546472B2 (en) | 1992-09-28 | 1992-09-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2546472B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW410452B (en) * | 1999-04-28 | 2000-11-01 | Siliconware Precision Industries Co Ltd | Semiconductor package having dual chips attachment on the backs and the manufacturing method thereof |
| JP4567297B2 (en) * | 2003-03-27 | 2010-10-20 | セイコーインスツル株式会社 | Reinforcement |
| DE10352349B4 (en) | 2003-11-06 | 2006-11-16 | Infineon Technologies Ag | Semiconductor chip with flip-chip contacts and method for producing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253665A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Semiconductor device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60118252U (en) * | 1984-01-18 | 1985-08-09 | 沖電気工業株式会社 | Lead frame for resin-sealed semiconductor devices |
| JPS60181051U (en) * | 1984-05-14 | 1985-12-02 | 日立電線株式会社 | Structure of lead frame |
-
1992
- 1992-09-28 JP JP4257759A patent/JP2546472B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5253665A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0629448A (en) | 1994-02-04 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |