JP2545986B2 - Logical path multiplexing method - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logical path multiplexing system, and more particularly to a system for configuring a coupling path between logical circuits in an information processing device.

2. Description of the Related Art In general, the time required for a logic signal output from a flip-flop (hereinafter abbreviated as FF) to propagate through a logic circuit element or conductor and reach the input of the next-stage FF is called delay time It is the most important parameter in circuit design.

Since this delay time is a variable factor such as manufacturing variations, it is not necessarily the same even in the same circuit, and it is necessary to consider it as a statistical value. An upper limit value and a lower limit value are defined as the normal range of the delay time that is statistically distributed, and these are called the maximum delay time and the minimum delay time, respectively.

In the synchronous logic circuit that operates in synchronization with the clock pulse, the time condition for transmitting information from one FF to the next FF is the maximum time required for the signal to pass through the logical path between both FFs. The value, that is, the maximum delay time is smaller than the period of the clock pulse. As long as this condition is met, the logic circuit can handle signals that change with each clock pulse.

Actually, in addition to the maximum delay time, it is necessary to take into consideration the time limit for the input of FF, clock skew, etc., but in this specification, these are also considered as a part of the delay time for discussion. Proceed.

Conventionally, as a solution when the maximum delay time of a certain logic path in a logic circuit is longer than the cycle of the clock pulse, a method of lengthening the cycle of the clock pulse of the entire logic circuit as necessary, a problem Pulse passing through the logic path of
One or more times, or a difference between the maximum delay time and the minimum delay time of the logical path is set to 1 of the clock pulse.
A method is adopted in which a signal that changes with each clock pulse can be sent by one pass by guaranteeing the period of time or less.

The above-described method of lengthening the period of the clock pulse or the method of sending the signal only once for every two or more clock pulses slows down the signal processing speed of the entire logic circuit and lowers the performance. Further, in the method of limiting the difference between the maximum delay time and the minimum delay time to one clock pulse period or less, it is commonly mounted and used in a circuit having a large maximum and minimum difference and a device having a different clock pulse period. In the circuit, there are problems that the constraint conditions are severe and the design is difficult, and even if the circuit can be designed, the circuit has a small operation margin and becomes relatively unstable.

OBJECT OF THE INVENTION It is an object of the present invention to provide a logical path multiplexing system that realizes continuous operation for each clock pulse without lengthening the cycle of the clock pulse.

According to the present invention, a multiplexing method of logic paths for supplying the output of the preceding logic circuit that operates in synchronization with the clock pulse to the subsequent logic circuit that also operates in synchronization with the clock pulse. The first and second registers that alternately take in the output of the preceding logic circuit for each clock pulse and the outputs of the first and second registers are switched alternately by the clock pulse. A logical path multiplexing system is obtained which includes a third register for taking in and supplies the output of the third register to the latter-stage logic circuit.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, clock pulses having a period T synchronized with each other are input to all the registers. Logic stage A including registers 10 and 11 and logic stage B including register 15
Between the register 10 and the register 15, the logic gate 12 between the register 10 and the register 15 and the logic gate 13 between the register 11 and the register 15 are exactly the same from the outside. Also, the maximum delay times D1 and D2 of the paths b and c are both D <2T with respect to the period T of the clock pulse.
It is assumed that

The signal a from the previous stage is commonly input to the registers 10 and 11 of the stage A. On the other hand, the set signal register 16 for the registers 10 and 11 is supplied with an inverted signal of its own output by the inversion gate 18, and its contents are inverted at each time pulse. Since the negative polarity output and the positive polarity output of the set signal register 16 are given to the set signals e and f of the registers 10 and 11, respectively, as a result, the inputs a from the previous stage are alternately input to the registers 10 and 11. The contents that have been set once will be retained for 2T.

The outputs of these registers 10 and 11 are the logic gate 1 respectively.
Register 1 during less than 2T after passing paths b and c including 2 and 13 respectively
Reach the entrance of 5. Selector 14 is input to register 15
Therefore, one of the paths b and c is selected.

The selector 14 is controlled by the output signal g of the selector signal register 17, which is also inverted every clock pulse, and as a result, the path b and the path c are alternately selected as the input of the register 15.

The select signal g is controlled in synchronization with the set signals of the registers 10 and 11 so that the path b is input 2T after the register 10 is set and the path c is input 2T after the register 11 is set. For example, pass b and pass c alternate
Each 2T is used so that the register 15 can receive the information from the previous stage at every clock pulse. Therefore, the inversion signal of its own output is input to the select signal register 17 by the inversion gate 19, and its content is inverted at each time pulse.

Such synchronization control between the stage A and the stage B can be easily realized by first resetting the set signal register 16 and the select signal register 17 to 0 at the same time.

FIG. 2 is a time chart describing changes in main registers and control signals in FIG. 1 with time. Parallel vertical lines represent the timing of the clock pulse,
The interval corresponds to 1T.

First, the contents of the set signal register 16 and the select signal register 17 are always the same value, and they are inverted every clock pulse. The contents of register 16 in register 10 is "0"
When the content of the register 16 is "1", the set signal f is sent to the register 11.
The contents of each register set by these set signals are held for 2T until the next set signal.

The outputs of registers 10 and 11 are selectors after 2T via paths b and c.
When it reaches 14, the signal is alternately selected by the select signal g sent from the register 17 and is fixed in the register 15. As a result, the information from the register 10 and the information from the register 11 are alternately fetched into the register 15 every 1T.

In this embodiment, it is assumed that the path between the registers has some combinational logic, but the situation is the same even if the conductor has no logic. Also, it is clear that even if the maximum delay time of the path between the registers exceeds 2T, it can be dealt with by increasing the multiplicity of the logical path.

EFFECTS OF THE INVENTION As described above, according to the present invention, processing in which the maximum delay time exceeds the cycle of the clock pulse can be stably executed for each clock pulse without lengthening the cycle. Even when the same circuit is used for different models having a long clock pulse cycle, there is an effect that they can be used as they are without being restricted by the minimum delay time.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart showing the operation of FIG. Explanation of symbols of main parts 10,11 …… Register 14 …… Selector 15 …… Register 16 …… Set signal register 17 …… Select signal register a, b …… Logical path

Claims (1)

(57) [Claims] 1. A multiplexing method of logic paths for supplying an output of a preceding logic circuit which operates in synchronization with a clock pulse to a subsequent logic circuit which also operates in synchronization with the clock pulse. A first and a second register that alternately take in the output of the preceding logic circuit for each time pulse, and a third register that alternately take the output of the first and second registers by the time pulse. Of the third register, and the output of the third register is supplied to the latter-stage logic circuit.