JP2024127607A - Photoelectric conversion device and photoelectric conversion system - Google Patents

Abstract

[Problem] To provide a technology for further improving the functions and characteristics of a stacked photoelectric conversion device. [Solution] The photoelectric conversion device is formed by stacking a plurality of substrates including a first substrate and a second substrate, and has a pixel that outputs a signal according to incident light. The pixel has a photoelectric conversion element that generates a charge according to the amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of its source and drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node. The first substrate has a first semiconductor layer in which the photoelectric conversion element, the first transistor, and the second transistor are provided, and the second substrate has a second semiconductor layer in which the third transistor is provided. [Selected Figure] Figure 5

Description

The present invention relates to a photoelectric conversion device and a photoelectric conversion system.

In response to demands for even higher performance and functionality in photoelectric conversion devices such as CMOS image sensors, stacked photoelectric conversion devices have been proposed in which photoelectric conversion elements and other circuit elements are arranged on separate substrates. Patent Document 1 describes a stacked imaging device in which a first substrate on which photoelectric conversion elements are provided, a second substrate on which pixel circuits are provided, and a third substrate on which signal processing circuits are provided are stacked.

International Publication No. 2019/130702

However, in the technology described in Patent Document 1, the circuit elements on each board are not necessarily appropriately arranged, and it cannot be said that miniaturization or noise suppression is adequately achieved.

The object of the present invention is to provide technology to further improve the functions and characteristics of stacked photoelectric conversion devices.

According to one disclosure of the present specification, a photoelectric conversion device is provided in which a plurality of substrates including a first substrate and a second substrate are stacked, and the pixel has a signal that corresponds to incident light, the pixel has a photoelectric conversion element that generates a charge corresponding to the amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of a source and a drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node, the first substrate has a first semiconductor layer in which the photoelectric conversion element, the first transistor, and the second transistor are provided, and the second substrate has a second semiconductor layer in which the third transistor is provided.

According to another disclosure of this specification, there is provided a photoelectric conversion device having a pixel that outputs a signal according to incident light, the pixel having a photoelectric conversion element that generates a charge according to the amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of a source and a drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node, the first substrate having a first semiconductor layer in which the photoelectric conversion element and the first transistor are provided, the second substrate having a second semiconductor layer in which the second transistor and the third transistor are provided, and the gate of the first transistor does not overlap an element that constitutes a capacitance between the first node and the first substrate in a plan view.

The present invention can further improve the functionality and characteristics of stacked photoelectric conversion devices.

1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment of the present invention. 1 is a schematic diagram showing a configuration example of a photoelectric conversion device according to a first embodiment of the present invention. 1 is an equivalent circuit diagram (part 1) of a pixel in a photoelectric conversion device according to a first embodiment of the present invention. FIG. FIG. 2 is an equivalent circuit diagram (part 2) of a pixel in the photoelectric conversion device according to the first embodiment of the present invention. 1 is a schematic cross-sectional view (part 1) showing a configuration example of a photoelectric conversion device according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view (part 2) showing an example of the configuration of the photoelectric conversion device according to the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view (part 3) showing a configuration example of the photoelectric conversion device according to the first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view (part 4) showing a configuration example of the photoelectric conversion device according to the first embodiment of the present invention. 1 is a plan view showing an example of the configuration of a photoelectric conversion device according to a first embodiment of the present invention. FIG. 11 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a second embodiment of the present invention. FIG. 4 is a schematic cross-sectional view showing an example of the configuration of a photoelectric conversion device according to a second embodiment of the present invention. FIG. 11 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a third embodiment of the present invention. FIG. 11 is a schematic cross-sectional view showing an example of the configuration of a photoelectric conversion device according to a third embodiment of the present invention. FIG. 11 is a plan view (part 1) showing a configuration example of a photoelectric conversion device according to a fourth embodiment of the present invention. FIG. 11 is a schematic cross-sectional view (part 1) showing a configuration example of a photoelectric conversion device according to a fourth embodiment of the present invention. FIG. 13 is a schematic cross-sectional view (part 2) showing a configuration example of a photoelectric conversion device according to a fourth embodiment of the present invention. FIG. 13 is a plan view (part 2) showing a configuration example of a photoelectric conversion device according to a fourth embodiment of the present invention. 13A to 13C are cross-sectional views illustrating steps in a method for manufacturing a photoelectric conversion device according to a fifth embodiment of the present invention. FIG. 13 is a schematic cross-sectional view showing a photoelectric conversion device according to a fifth embodiment of the present invention. FIG. 13 is a block diagram showing a schematic configuration of a photoelectric conversion system according to a sixth embodiment of the present invention. FIG. 13 is a diagram showing a configuration example of a photoelectric conversion system and a moving object according to a seventh embodiment of the present invention. FIG. 13 is a block diagram showing a schematic configuration of an apparatus according to an eighth embodiment of the present invention.

The embodiments shown below are intended to embody the technical ideas of the present invention, but are not intended to limit the present invention. The sizes and positional relationships of the components shown in each drawing may be exaggerated for clarity. In the following description, terms indicating specific directions or positions (e.g., "upper," "lower," "right," "left," and other terms that include these terms) are used as necessary. The use of these terms is intended to facilitate understanding of the invention with reference to the drawings, and the technical scope of the present invention is not limited by the meaning of these terms. In other words, even a configuration in which the top and bottom are inverted falls within the technical scope of the present invention.

In addition, in each of the embodiments described below, an imaging device will be mainly described as an example of a photoelectric conversion device. However, each of the embodiments is not limited to imaging devices, and can also be applied to other examples of photoelectric conversion devices. Other examples of photoelectric conversion devices include, for example, distance measuring devices (devices that measure distance using focus detection or TOF (Time Of Flight)), photometric devices (devices that measure the amount of incident light, etc.), etc.

[First embodiment]
A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to Figs. 1 to 9. Fig. 1 is a block diagram showing a schematic configuration of the photoelectric conversion device according to this embodiment. Fig. 2 is a schematic diagram showing a configuration example of the photoelectric conversion device according to this embodiment. Figs. 3 and 4 are equivalent circuit diagrams of pixels in the photoelectric conversion device according to this embodiment. Figs. 5 to 8 are schematic cross-sectional views showing a configuration example of the photoelectric conversion device according to this embodiment. Fig. 9 is a plan view showing a configuration example of the photoelectric conversion device according to this embodiment.

As shown in FIG. 1, the photoelectric conversion device according to this embodiment may be configured with a pixel array section 10, a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60. The photoelectric conversion device 100 is a semiconductor device formed on a semiconductor substrate such as a silicon substrate, and may be, for example, a CMOS image sensor.

In the pixel array section 10, a plurality of pixels 12, each of which includes a photoelectric conversion section, are two-dimensionally arranged in a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion element such as a photodiode, and is configured to output a pixel signal according to the amount of incident light. The number of rows and columns of the pixel array arranged in the pixel array section 10 is not particularly limited. In addition to effective pixels that output pixel signals according to the amount of incident light, the pixel array section 10 may also include optical black pixels in which the photoelectric conversion section is shielded from light, dummy pixels that do not output signals, and the like.

In each row of the pixel array section 10, a control line 14 is arranged, extending in a first direction (horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 arranged in the first direction, and serves as a signal line common to these pixels 12. The first direction in which the control lines 14 extend is sometimes called the row direction or horizontal direction. The control lines 14 are connected to a vertical scanning circuit 20.

In each column of the pixel array section 10, an output line 16 is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each output line 16 is connected to the pixels 12 aligned in the second direction, and serves as a common signal line for these pixels 12. The second direction in which the output lines 16 extend is sometimes called the column direction or vertical direction. The output lines 16 are connected to a readout circuit 30.

The vertical scanning circuit 20 is a control circuit that generates control signals for driving the pixels 12 in response to control signals from the control circuit 60 and supplies the control signals to the pixels 12 via the control lines 14. The vertical scanning circuit 20 can be configured using logic circuits such as shift registers and address decoders. The vertical scanning circuit 20 drives the pixels 12 of the pixel array section 10 on a row-by-row basis using control signals supplied via the control lines 14. The signals read out from the pixels 12 on a row-by-row basis are input to the readout circuit 30 via the output lines 16 arranged in each column of the pixel array section 10.

The readout circuit 30 is a circuit section that performs predetermined processing on the pixel signals read out from the pixel array section 10, such as signal processing such as correction processing using correlated double sampling, amplification processing, and analog-to-digital conversion processing. The readout circuit 30 may include a signal holding circuit for holding the pixel signals output from the pixel array section 10 and the pixel signals after signal processing.

The horizontal scanning circuit 40 is a control circuit that has the function of supplying a control signal to the readout circuit 30 for transferring the pixel signals processed by the readout circuit 30 to the output circuit 50 sequentially for each column in response to a control signal from the control unit 70. The horizontal scanning circuit 40 can be configured using logic circuits such as a shift register and an address decoder.

The output circuit 50 may be configured to include a buffer amplifier or a differential amplifier for performing predetermined signal processing on the pixel signals read out from the readout circuit 30, and an external interface circuit for outputting the pixel signals after signal processing to the outside. Examples of the signal processing performed by the output circuit 50 include correction processing using correlated double sampling and amplification processing. The external interface circuit provided in the output circuit 50 is not particularly limited. For example, a SerDes (SERializer/DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be used as the external interface circuit.

The control circuit 60 is a circuit section for supplying control signals to functional blocks such as the vertical scanning circuit 20, the readout circuit 30, the horizontal scanning circuit 40, and the output circuit 50, which control their operation and timing. Some or all of the control signals supplied to each functional block may be supplied from outside the photoelectric conversion device 100.

The photoelectric conversion device 100 of this embodiment is configured as a stacked photoelectric conversion device in which the circuit elements constituting the above-mentioned multiple functional blocks are made on multiple substrates and these multiple substrates are stacked. FIG. 2(a) is a schematic diagram of a case in which a photoelectric conversion device is configured by stacking a first substrate 110 and a second substrate 140. In this case, for example, at least the photoelectric conversion elements of each of the multiple pixels 12 constituting the pixel array section 10 can be arranged on the first substrate 110, and other circuit elements and other functional blocks of the multiple pixels 12 can be arranged on the second substrate 140. FIG. 2(b) is a schematic diagram of a case in which a photoelectric conversion device is configured by stacking a first substrate 110, a second substrate 140, and a third substrate 170. In this case, for example, at least the photoelectric conversion elements of each of the multiple pixels 12 constituting the pixel array section 10 can be arranged on the first substrate 110, other circuit elements of the multiple pixels 12 can be arranged on the second substrate 140, and other functional blocks can be arranged on the third substrate 170. The number of substrates constituting the photoelectric conversion device 100 may be four or more. Also, the circuit elements constituting one functional block do not necessarily have to be placed on the same substrate, and may be placed on separate substrates.

By constructing a stacked photoelectric conversion device in this manner, it is possible to miniaturize the photoelectric conversion device without sacrificing the area of the photoelectric conversion section. In addition, by using separate substrates for forming the pixel circuit and the logic circuit, each substrate can be manufactured using a wafer process that is suitable for each. This makes it possible to achieve even higher performance and functionality. The effects of producing the circuit elements that make up the pixel 12 on multiple substrates will be described later.

Next, configuration examples of each pixel 12 constituting the pixel array section 10 will be described with reference to Figures 3 and 4. Here, two equivalent circuit diagrams are shown as configuration examples of the pixel 12, but the pixel 12 is not limited to these circuits.

The pixel 12 illustrated in FIG. 3 is composed of a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The photoelectric conversion element PD may be composed of, for example, a photodiode, and the transfer transistor M1, the reset transistor M2, the amplification transistor M3, and the selection transistor M4 may be composed of MOS transistors. The pixel 12 may further have a microlens and a color filter arranged on the optical path along which incident light is guided to the photoelectric conversion element PD. The microlens focuses the incident light on the photoelectric conversion element PD. The color filter selectively transmits light of a predetermined color.

The dotted line in FIG. 3 indicates the boundary between the first substrate 110 and the second substrate 140. That is, of the above components of the pixel 12, the photoelectric conversion element PD, the transfer transistor M1, and the reset transistor M2 are provided on the first substrate 110, and the amplification transistor M3 and the selection transistor M4 are provided on the second substrate 140.

The photoelectric conversion element PD has an anode electrically connected to a reference voltage line (e.g., a ground voltage line) and a cathode electrically connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is electrically connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion portion. The floating diffusion portion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance may include the gate capacitance of the transistor, the pn junction capacitance of the source/drain portion, the wiring capacitance, and the like. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are electrically connected to a power supply voltage line (e.g., voltage VDD). The source of the amplification transistor M3 is electrically connected to the drain of the selection transistor M4. The source of the selection transistor M4 is electrically connected to the output line 16.

Note that pixel 12 does not necessarily have to have selection transistor M4, and selection transistor M4 can be omitted. Selection transistor M4 may also be provided between the power supply voltage line and amplification transistor M3. In this case, the drain of selection transistor M4 is connected to the power supply voltage line, the source of selection transistor M4 is connected to the drain of amplification transistor M3, and the source of the amplification transistor is connected to output line 16.

In the case of the circuit configuration of FIG. 3, the control line 14 of each row includes three signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, and the gate of the selection transistor M4. A control signal PTX is supplied from the vertical scanning circuit 20 to the gate of the transfer transistor M1. A control signal PRES is supplied from the vertical scanning circuit 20 to the gate of the reset transistor M2. A control signal PSEL is supplied from the vertical scanning circuit 20 to the gate of the selection transistor M4. When each transistor is an N-type MOS transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned on. Also, when a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned off.

In this embodiment, the description will be made assuming that, of the electron-hole pairs generated in the photoelectric conversion element PD by the incidence of light, the electrons are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be composed of an N-type MOS transistor. However, the signal charge is not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is the opposite conductivity type to that described in this embodiment. In addition, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the opposite names. In addition, the source and drain may be distinguished from one another. For example, when one of the source and drain is a source, the other of the source and drain is a drain.

The photoelectric conversion element PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and accumulates the resulting charge. When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric conversion element PD to the node FD. The charge transferred from the photoelectric conversion element PD is held by the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD through charge-voltage conversion by the floating diffusion capacitance.

When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the output line 16. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to the drain and a bias current is supplied to the source from a current source (not shown) via the selection transistor M4, forming an amplification section (source follower circuit) with the gate as the input node. As a result, the amplification transistor M3 outputs a signal based on the potential of the node FD to the output line 16 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the node FD.

The reset transistor M2 has the function of controlling the supply of a voltage (voltage VDD) to the FD node to reset the node FD, which serves as a charge storage unit. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to the voltage VDD.

The pixel 12 illustrated in FIG. 4 is a configuration example in which the node FD, the reset transistor M2, the amplification transistor M3, and the selection transistor M4 are shared among four pixels 12A, 12B, 12C, and 12D. Here, the pixel 12A is composed of a photoelectric conversion element PDA, a transfer transistor M1A, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The pixel 12B is composed of a photoelectric conversion element PDB, a transfer transistor M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The pixel 12C is composed of a photoelectric conversion element PDC, a transfer transistor M1C, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. The pixel 12D is composed of a photoelectric conversion element PDD, a transfer transistor M1D, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

The photoelectric conversion element PDA has an anode electrically connected to a reference voltage line and a cathode electrically connected to the source of the transfer transistor M1A. The photoelectric conversion element PDB has an anode electrically connected to a reference voltage line and a cathode electrically connected to the source of the transfer transistor M1B. The photoelectric conversion element PDC has an anode electrically connected to a reference voltage line and a cathode electrically connected to the source of the transfer transistor M1C. The photoelectric conversion element PDD has an anode electrically connected to a reference voltage line and a cathode electrically connected to the source of the transfer transistor M1D. The drains of the transfer transistors M1A, M1B, M1C, and M1D are electrically connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node FD to which the drains of the transfer transistors M1A, M1B, M1C, and M1D, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a floating diffusion portion. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are electrically connected to the power supply voltage line. The source of the amplification transistor M3 is electrically connected to the drain of the selection transistor M4. The source of the selection transistor M4 is electrically connected to the output line 16.

By configuring pixels 12A, 12B, 12C, and 12D to share node FD, reset transistor M2, amplification transistor M3, and selection transistor M4, the area occupied by the pixel circuit in the entire photoelectric conversion device can be reduced. Note that the number of pixels 12 that share node FD, reset transistor M2, amplification transistor M3, and selection transistor M4 does not necessarily have to be four, and may be two or three, or five or more.

The dotted line in FIG. 4 indicates the boundary between the first substrate 110 and the second substrate 140. That is, of the above components of the pixel 12, the photoelectric conversion elements PDA, PDB, PDC, and PDD, the transfer transistors M1A, M1B, M1C, and M1D, and the reset transistor M2 are provided on the first substrate 110. Furthermore, the amplification transistor M3 and the selection transistor M4 are provided on the second substrate 140.

The operation of pixel 12 shown in FIG. 4 is basically the same as that of pixel 12 shown in FIG. 3. That is, when transfer transistor M1A is turned on, it transfers the charge held by photoelectric conversion element PDA to node FD. When transfer transistor M1B is turned on, it transfers the charge held by photoelectric conversion element PDB to node FD. When transfer transistor M1C is turned on, it transfers the charge held by photoelectric conversion element PDC to node FD. When transfer transistor M1D is turned on, it transfers the charge held by photoelectric conversion element PDD to node FD. The operations of reset transistor M2, amplification transistor M3, and selection transistor M4 are the same as those of pixel 12 shown in FIG. 3.

Next, specific configuration examples of the photoelectric conversion device according to this embodiment will be described with reference to Figs. 5 to 9. Here, a stacked photoelectric conversion device formed by stacking three substrates is taken as an example, and several configuration examples of the photoelectric conversion device 100 according to this embodiment are shown.

As shown in FIG. 5, the photoelectric conversion device 100 according to this embodiment is a stacked photoelectric conversion device in which a first substrate 110, a second substrate 140, and a third substrate 170 are stacked. The first substrate 110, the second substrate 140, and the third substrate 170 are stacked in this order.

The first substrate 110 has a semiconductor layer 112 having a first surface 114 and a second surface 116, and a wiring structure layer 130 arranged on the first surface 114 side of the semiconductor layer 112. Among the components of the pixel 12, the photoelectric conversion element PD, the transfer transistor M1, and the reset transistor M2 are provided on the first substrate 110. Of these, FIG. 5 shows the components of the photoelectric conversion element PD and the transfer transistor M1.

The photoelectric conversion element PD may be configured to include a first conductive type semiconductor region 118 and second conductive type semiconductor regions 122, 124 provided in the semiconductor layer 112. The semiconductor region 118 is, for example, an N-type semiconductor region and serves as a cathode of the photoelectric conversion element PD. The semiconductor regions 122, 124 are, for example, P-type semiconductor regions and serve as an anode of the photoelectric conversion element PD. The semiconductor region 122 is connected to a through electrode (not shown) on the first surface 114 side, and a reference potential (for example, a ground potential) is supplied to the semiconductor regions 122, 124 from the second substrate 140 side through this through electrode. The semiconductor regions 122, 124 are arranged to surround the second surface 116 side and side portions of the semiconductor region 118, and also serve to separate the photoelectric conversion elements PD of other pixels 12 arranged adjacent to each other. A pixel separator 126 may be further provided inside the semiconductor region 122. The pixel separator 126 is, for example, a deep trench isolation (DTI) provided to penetrate the semiconductor layer 112, and may be configured by filling an opening that penetrates the semiconductor layer 112 with an insulating material, a metal material, or the like. A first conductivity type semiconductor region 120 is provided on the surface portion of the first face 114 of the semiconductor layer 112, separated from the semiconductor region 118.

On the first surface 114 of the semiconductor layer 112, a wiring structure layer 130 including an insulating layer 132 and a gate electrode 128 of the transfer transistor M1 arranged therein is provided. The gate electrode 128 is provided on the first surface 114 of the semiconductor layer 112 via a gate insulating film so as to overlap the region between the semiconductor region 118 and the semiconductor region 120 in a plan view. The transfer transistor M1 has a role of transferring the signal charge accumulated in the semiconductor region 118 to the semiconductor region 120, and it can be said that the semiconductor region 118 constitutes the source of the transfer transistor M1 and the semiconductor region 120 constitutes the drain of the transfer transistor M1. The semiconductor region 120 also constitutes a part of the node FD. A control signal PTX is supplied to the gate electrode 128 of the transfer transistor M1 from the second substrate 140 side via a through electrode (not shown).

On the second surface 116 side of the semiconductor layer 112, a pinning layer 192, a planarization film 194, and a microlens 196 are provided in this order. The pinning layer 192 is, for example, a film containing a negative fixed charge, and specifically, may be composed of hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, or the like. By exciting holes on the second surface 116 side of the semiconductor layer 112 by the pinning layer 192, even if dark electrons are generated in the semiconductor region 124, the dark electrons can be recombined with holes, and the dark electrons that contribute to the noise signal can be eliminated. A color filter layer (not shown) may be further provided between the pinning layer 192 and the microlens 196. The microlens 196 is configured to focus light incident from the surface (back surface) opposite to the element formation surface of the semiconductor layer 112 onto the photoelectric conversion element PD. That is, the photoelectric conversion device of this embodiment is a so-called back-illuminated photoelectric conversion device.

The second substrate 140 has a semiconductor layer 142 having a first surface 144 and a second surface 146, and a wiring structure layer 150 arranged on the first surface 144 side of the semiconductor layer 142. The second substrate 140 is bonded to the first substrate 110 so that the second surface 146 faces the wiring structure layer 130 side of the first substrate 110. In other words, the second substrate 140 is bonded to the first substrate 110 so that the back surface (second surface 146) of the semiconductor layer 142 faces the front surface (first surface 114) of the semiconductor layer 112. In other words, the second substrate 140 is bonded to the first substrate 110 face-to-back. At least the amplification transistor M3 and the selection transistor M4, which are among the components of the pixel 12, are provided on the second substrate 140. Of these, FIG. 5 shows the components of the amplification transistor M3.

On the first surface 144 side of the semiconductor layer 142, a semiconductor region constituting the source and drain of the amplification transistor M3 and the selection transistor M4 is provided. On the first surface 144 of the semiconductor layer 142, a wiring structure layer 150 including an insulating layer 152 and electrodes and wirings arranged therein is provided. The wiring structure layer 150 includes a gate electrode 154 of the amplification transistor M3, a through electrode 156, and wirings 162 and 164. The gate electrode 154 is provided on the first surface 144 of the semiconductor layer 142 via a gate insulating film. The gate electrode 154 is electrically connected to the semiconductor region 120 via the through electrode 156. The through electrode 156 is arranged in the insulating layer 152 and reaches the semiconductor region 120 by penetrating the semiconductor layer 142 and the insulating layer 132. The semiconductor layer 142 and the through electrode 156 are insulated by the insulating layer 148. The insulating layer 148 can be formed, for example, by forming an opening in a part of the semiconductor layer 142 and filling the opening with an insulating material. Although FIG. 5 shows an example in which the wiring structure layer 150 is composed of four wiring layers including a gate layer, the number of wiring layers that compose the wiring structure layer 150 can be set arbitrarily.

The third substrate 170 has a semiconductor layer 172 having a first surface 174 and a second surface 176, and a wiring structure layer 180 arranged on the first surface 174 side of the semiconductor layer 172. The third substrate 170 is bonded to the second substrate 140 so that the wiring structure layer 180 faces the wiring structure layer 150 side of the second substrate 140. In other words, the third substrate 170 is bonded to the second substrate 140 so that the surface (first surface 174) of the semiconductor layer 172 faces the surface (first surface 144) of the semiconductor layer 142. In other words, the third substrate 170 is bonded to the second substrate 140 face-to-face. A driving circuit for the pixel 12, a processing circuit for processing an output signal from the pixel 12, and the like may be arranged on the third substrate 170. For example, the third substrate 170 may be provided with functional blocks such as a vertical scanning circuit 20, a readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60, or parts of these functional blocks.

Elements such as transistors constituting functional blocks arranged on the third substrate 170 may be provided on the first surface 174 of the semiconductor layer 172. FIG. 5 shows an example of a transistor having a gate electrode 178. A salicide process may be applied to transistors constituting logic circuits such as the vertical scanning circuit 20, readout circuit 30, horizontal scanning circuit 40, output circuit 50, and control circuit 60, and low-resistance silicide regions may be provided on the surface of the source/drain or gate. For example, nickel silicide (NiSi) or cobalt silicide (CoSi) may be used as the silicide.

On the first surface 174 of the semiconductor layer 172, a wiring structure layer 180 including an insulating layer 182 and electrodes and wiring arranged therein is provided. The wiring structure layer 180 includes a gate electrode 178 and wiring 184. Although FIG. 5 shows the wiring structure layer 180 including a gate layer and four wiring layers, the number of wiring layers constituting the wiring structure layer 180 can be set arbitrarily.

The semiconductor layers 112, 142, 172 constituting each substrate may be made of, for example, single crystal silicon. The insulating layers 132, 152, 182 may be made of, for example, silicon oxide (SiO). At least a portion of the insulating layers 132, 152, 182 may contain silicon carbide (SiC) or silicon nitride (SiN) to suppress metal diffusion from the conductive layer. The gate electrodes 128, 154, 178 may be made of a single layer structure of polycrystalline silicon, a polycide structure, a polymetal structure, or the like. The wiring layer may be made of metal materials such as aluminum (Al) and copper (Cu). When using intermetallic bonding of the metal materials constituting the wiring layer to bond the substrates together, it is desirable to make at least the topmost wiring layer using copper or gold (Au). A barrier layer having a metal diffusion prevention function may be appropriately provided around these wiring materials.

The photoelectric conversion device 100 shown in FIG. 6 is similar to the photoelectric conversion device shown in FIG. 5, except for the configuration of the gate electrode 128 of the transfer transistor M1. That is, the transfer transistor M1 of the photoelectric conversion device shown in FIG. 5 has a planar gate electrode 128, whereas the transfer transistor M1 of the photoelectric conversion device shown in FIG. 6 has a vertical gate electrode 128.

As in the case where the transfer transistor M1 has a vertical gate electrode 128 or a planar gate electrode 128, the gate electrode 128 is disposed adjacent to the semiconductor region 120 that constitutes the node FD. In addition, the gate electrode 128 is disposed so as to overlap at least a portion of the semiconductor region 118, and is configured so that the signal charge accumulated in the semiconductor region 118 can be transferred to the node FD by the transfer transistor M1.

As shown in FIG. 6, the gate electrode 128 is provided so as to extend into the semiconductor layer 112 from the first surface 114 side of the semiconductor layer 112 toward the second surface 116. By configuring in this manner, even if the semiconductor region 118 constituting the cathode of the photoelectric conversion element PD is disposed in a deep region away from the first surface 114 of the semiconductor layer 112, the signal charge accumulated in the semiconductor region 118 can be transferred to the node FD. This makes it possible to form other elements on the first surface 114 side of the semiconductor layer 112 without interfering with the photoelectric conversion element PD. In addition, the vertical gate electrode 128 can change the potential in the semiconductor region 118 more greatly than the planar gate electrode 128, so that the number of saturated electrons can be increased while the remaining charge can be reduced.

The photoelectric conversion device 100 shown in FIG. 7 is a configuration example corresponding to the equivalent circuit diagram shown in FIG. 4. FIG. 7 shows corresponding portions of two of the four pixels 12 that share one node FD. Each of the semiconductor regions 120 of each pixel 12 can be electrically connected to the gate electrode 154 of the amplification transistor M3, for example, via the through electrode 156 and the first metal wiring layer of the wiring structure layer 150.

The photoelectric conversion device 100 shown in FIG. 8 is another example of a configuration corresponding to the equivalent circuit diagram shown in FIG. 4. FIG. 8 shows the corresponding portions of two pixels 12 among the four pixels 12 sharing one node FD. In this example, the semiconductor regions 120 of the four pixels 12 sharing one node FD are arranged adjacent to each other with the semiconductor region 122 in between, and are electrically connected to each other by the wiring 134 arranged on the first surface 114. The wiring 134 can be made of polycrystalline silicon doped with impurities or a conductive material with high heat resistance, such as tungsten or titanium. Each of the semiconductor regions 120 of each pixel 12 can be electrically connected to the gate electrode 154 of the amplification transistor M3 via the wiring 134, the through electrode 156, and the first metal wiring layer of the wiring structure layer 150.

Figure 9 is a plan view of a pixel 12 in the configuration example shown in Figure 6. Figure 9(a) is a plan view of the semiconductor layer 112 viewed from the first surface 114 side, and Figure 9(b) is a plan view of the semiconductor layer 142 viewed from the first surface 144 side. Figures 9(a) and 9(b) show two groups of four pixels 12 sharing one node FD, for a total of eight pixels 12.

9(a) shows the pixel separation section 126, the gate electrode 128 of the transfer transistor M1, the gate electrode 136 of the reset transistor M2, and the through electrodes 156 and 168. Also, FIG. 9(a) shows the source regions of the transfer transistor M1 and the reset transistor M2 to which the through electrode 156 is connected, and the drain region of the reset transistor M2 to which the through electrode 168 is connected. The circular regions shown in these regions are schematic representations of the portions to which the through electrodes are electrically connected from the second substrate 140 side. FIG. 9(b) shows the gate electrode 154 of the amplification transistor M3 and the gate electrode 166 of the selection transistor M4. Also, the circular region shown in FIG. 9(b) corresponds to the circular region in FIG. 9(a). The amplification transistor M3 and the selection transistor M4 are provided in the semiconductor layer 142, avoiding the region in which the insulating layer 148 is arranged.

In the photoelectric conversion device of this embodiment, as described above, the transfer transistor M1 and the reset transistor M2 are disposed in the semiconductor layer 112 of the first substrate 110, and the amplification transistor M3 and the selection transistor M4 are disposed in the semiconductor layer 142 of the second substrate 140. By disposing the reset transistor M2 in the semiconductor layer 112, there is more room in the area of the element formation region of the semiconductor layer 142 compared to when the reset transistor M2 is disposed in the semiconductor layer 142. This improves the degree of freedom of layout in the semiconductor layer 142, and for example, the area of the amplification transistor M3 can be increased, and noise such as random telegraph signal (RTS) noise and 1/f noise can be suppressed.

When adopting a configuration in which some elements of the pixel circuit, such as the reset transistor M2, are arranged in the semiconductor layer 112, it is particularly preferable to adopt a vertical gate electrode as shown in FIG. 6 as the gate electrode 128 of the transfer transistor M1. By configuring the transfer transistor M1 with a vertical gate electrode 128, the semiconductor region 118 can be arranged away from the first surface 114, so that elements such as transistors can be easily arranged in the semiconductor layer 112 without interfering with the photoelectric conversion element PD.

When the reset transistor M2 is disposed in the semiconductor layer 112, the power supply voltage supplied to the drain of the reset transistor M2 can be supplied from the second substrate 140 side via the through electrode 168. By configuring it in this way, it becomes possible to supply power to the reset transistor M2 without placing power supply wiring on the first substrate 110, which is subject to a large thermal load during the manufacturing process.

In this way, according to this embodiment, the functionality and characteristics of a stacked photoelectric conversion device can be further improved.

[Second embodiment]
A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to Fig. 10 and Fig. 11. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 10 is an equivalent circuit diagram showing a configuration example of a pixel of the photoelectric conversion device according to this embodiment. Fig. 11 is a schematic cross-sectional view showing a configuration example of the photoelectric conversion device according to this embodiment.

The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the first embodiment, except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion device of the first embodiment will be mainly described, and descriptions of the parts that are similar to the photoelectric conversion device of the first embodiment will be omitted as appropriate.

As shown in FIG. 10, the pixel 12 of the photoelectric conversion device according to this embodiment further includes a storage transistor M5 in addition to the photoelectric conversion element PD, the transfer transistor M1, the reset transistor M2, the amplification transistor M3, and the selection transistor M4. The source of the storage transistor M5 is connected to the drain of the transfer transistor M1 and the gate of the amplification transistor M3. The drain of the storage transistor M5 is connected to the source of the reset transistor M2. In the pixel 12 of this embodiment, the connection node of the drain of the transfer transistor M1, the source of the storage transistor M5, and the gate of the amplification transistor M3 is the node FD. The storage transistor M5 can be controlled by a control signal FDINC supplied from the vertical scanning circuit 20 via the control line 14, for example. The connection relationship of the other components of the pixel 12 of this embodiment is the same as that of the pixel 12 of the first embodiment.

In general, the signal level of the pixel signal is small when shooting in a dark place. When charge-to-voltage conversion is performed at node FD based on the relationship Q=CV, if the floating diffusion capacitance is too large, the voltage converted to a voltage by amplifying transistor M3 will be small. Conversely, the signal level of the pixel signal is high when shooting in a bright place, so if the floating diffusion capacitance is not large, node FD will not be able to receive all of the signal charge generated by photoelectric conversion element PD. Furthermore, a large floating diffusion capacitance is required so that the voltage level does not become too high when converted to a voltage by amplifying transistor M3.

The storage transistor M5 meets these requirements, and is used when switching the charge-voltage conversion efficiency of pixel 12. That is, when the storage transistor M5 is turned on, the gate capacitance of the storage transistor M5 increases, and therefore the capacitance of the node FD to which the gate capacitance of the storage transistor M5 is connected in parallel, i.e., the floating diffusion capacitance, also increases. On the other hand, when the storage transistor M5 is turned off, the gate capacitance of the storage transistor M5 decreases, and therefore the floating diffusion capacitance also decreases. In this way, by switching the storage transistor M5 on and off, the floating diffusion capacitance can be made variable, and the charge-voltage conversion efficiency can be switched.

Figure 11 is a plan view of a pixel 12 in the configuration example shown in Figure 10. Figure 11(a) is a plan view of the semiconductor layer 112 viewed from the first surface 114 side, and Figure 11(b) is a plan view of the semiconductor layer 142 viewed from the first surface 144 side. Figures 11(a) and 11(b) show two groups of four pixels 12 sharing one node FD, for a total of eight pixels 12.

11(a) shows the pixel separation section 126, the gate electrode 128 of the transfer transistor M1, the gate electrode 138 of the storage transistor M5, and the through electrode 156. FIG. 11(a) also shows the source regions of the transfer transistor M1 and the storage transistor M5 to which the through electrode 156 is connected, and the drain region of the storage transistor M5. The circular regions shown in these regions are schematic representations of the portions to which the through electrodes are electrically connected from the second substrate 140 side. FIG. 11(b) shows the gate electrode 136 of the reset transistor M2, the gate electrode 154 of the amplification transistor M3, and the gate electrode 166 of the selection transistor M4. The circular regions shown in FIG. 11(b) correspond to the circular regions in FIG. 11(a). The reset transistor M2, the amplification transistor M3, and the selection transistor M4 are provided in the semiconductor layer 142, avoiding the region in which the insulating layer 148 is disposed.

In this embodiment, in a pixel configuration including a storage transistor M5, a photoelectric conversion element PD, a transfer transistor M1, and a storage transistor M5 are disposed in the semiconductor layer 112 of the first substrate 110. A reset transistor M2, an amplification transistor M3, and a selection transistor M4 are disposed in the semiconductor layer 142 of the second substrate 140.

The storage transistor M5 is required to have a capacity sufficient to transfer signal charges even during high-illumination shooting, but it is difficult to secure the area for arranging a storage transistor M5 with sufficient capacity, especially in fine pixels. In this regard, in this embodiment, the storage transistor M5 is arranged in the semiconductor layer 112 of the first substrate 110, rather than in the semiconductor layer 142 of the second substrate 140 in which the reset transistor M2, the amplification transistor M3, and the selection transistor M4 are arranged. Therefore, a layout with more area for the storage transistor M5 is possible compared to when the storage transistor M5 is arranged in the semiconductor layer 142, and it becomes possible to realize a photoelectric conversion device with, for example, a larger floating diffusion capacitance.

Note that although FIG. 10 and FIG. 11 show a configuration example in which one storage transistor M5 is connected to node FD, multiple storage transistors M5 may be connected to node FD. In this case, the multiple storage transistors M5 may be connected in series or in parallel to node FD.

In this way, according to this embodiment, the functionality and characteristics of a stacked photoelectric conversion device can be further improved.

[Third embodiment]
A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to Fig. 12 and Fig. 13. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 12 is an equivalent circuit diagram showing a configuration example of a pixel of the photoelectric conversion device according to this embodiment. Fig. 13 is a schematic cross-sectional view showing a configuration example of the photoelectric conversion device according to this embodiment.

The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion device according to the second embodiment, except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion device of the second embodiment will be mainly described, and descriptions of the parts that are similar to the photoelectric conversion device of the second embodiment will be omitted as appropriate.

The pixel 12 of this embodiment is similar to the pixel 12 of the second embodiment in that it has a storage transistor M5 connected between the node FD and the source of the reset transistor M2. On the other hand, the pixel 12 of this embodiment differs from the pixel 12 of the second embodiment in that the reset transistor M2 is disposed in the semiconductor layer 112 of the first substrate 110 as shown in FIG. 12, in that the reset transistor M2 is disposed in the semiconductor layer 142 of the second substrate 140.

Figure 13 is a plan view of a pixel 12 in the configuration example shown in Figure 12. Figure 13(a) is a plan view of the semiconductor layer 112 viewed from the first surface 114 side, and Figure 13(b) is a plan view of the semiconductor layer 142 viewed from the first surface 144 side. Figures 13(a) and 13(b) show two groups of four pixels 12 sharing one node FD, for a total of eight pixels 12.

13(a) shows the pixel separation section 126, the gate electrode 128 of the transfer transistor M1, the gate electrode 136 of the reset transistor M2, the gate electrode 138 of the storage transistor M5, and the through electrode 156. Also, FIG. 13(a) shows the source regions of the transfer transistor M1 and the storage transistor M5 to which the through electrode 156 is connected, the drain region of the reset transistor M2, and the drain region of the storage transistor M5. The circular regions shown in these regions are schematic representations of the portions to which the through electrodes are electrically connected from the second substrate 140 side. FIG. 13(b) shows the gate electrode 154 of the amplification transistor M3 and the gate electrode 166 of the selection transistor M4. Also, the circular region shown in FIG. 13(b) corresponds to the circular region in FIG. 13(a). The amplification transistor M3 and the selection transistor M4 are provided in the semiconductor layer 142, avoiding the region in which the insulating layer 148 is arranged.

By disposing the storage transistor M5 in the semiconductor layer 112 of the first substrate 110, even when the storage transistor M5 is connected to the node FD to configure the floating diffusion capacitance as variable, the area of elements such as the amplification transistor M3 disposed in the semiconductor layer 142 is not compressed. This makes it possible to suppress noise such as random telegraph signal (RTS) noise and 1/f noise that occurs when the area of the amplification transistor M3 is reduced.

In this way, according to this embodiment, the functionality and characteristics of a stacked photoelectric conversion device can be further improved.

[Fourth embodiment]
A photoelectric conversion device according to a fourth embodiment of the present invention will be described with reference to Figs. 14 to 17. Components similar to those of the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Figs. 14 and 17 are plan views showing a configuration example of the photoelectric conversion device according to this embodiment. Figs. 15 and 16 are schematic cross-sectional views showing a configuration example of the photoelectric conversion device according to this embodiment.

The photoelectric conversion device according to this embodiment differs from the photoelectric conversion devices according to the first to third embodiments in that the gate electrode 128 of the transfer transistor M1 is arranged so as not to overlap with the elements constituting the floating diffusion capacitance in a planar view. The other configurations of the photoelectric conversion device according to this embodiment may be similar to those of the photoelectric conversion device described in any of the first to third embodiments. In addition to the configuration examples shown in the first to third embodiments, the present invention can also be applied to a case where the reset transistor M2 is arranged on the second substrate 140.

Figure 14 is a plan view of a pixel 12 in a photoelectric conversion device according to this embodiment. Figure 14(a) is a plan view of the semiconductor layer 112 viewed from the first surface 114 side, and Figure 14(b) is a plan view of the semiconductor layer 142 viewed from the first surface 144 side. Figures 14(a) and 14(b) show two groups of four pixels 12 sharing one node FD, for a total of eight pixels 12.

In the configuration example shown in FIG. 14, the photoelectric conversion element PD and the transfer transistor M1 are arranged on the first substrate 110, and the reset transistor M2, the amplification transistor M3, and the selection transistor M4 are arranged on the second substrate 140. FIG. 14(a) shows the pixel separation section 126, the semiconductor regions 118 and 120, the gate electrode 128 of the transfer transistor M1, the semiconductor regions 118 and 120, the wiring 134, and the through electrode 156, among the elements arranged on the first substrate 110. The circular regions shown in these regions are schematic representations of the portions to which the through electrodes are electrically connected from the second substrate 140 side. FIG. 14(b) shows the gate electrode 136 of the reset transistor M2, the gate electrode 154 of the amplification transistor M3, the gate electrode 166 of the selection transistor M4, and the source and drain regions of these transistors, among the elements arranged on the second substrate. The circular regions shown in FIG. 14(b) correspond to the circular regions in FIG. 14(a). The reset transistor M2, the amplification transistor M3, and the selection transistor M4 are provided in the semiconductor layer 142, avoiding the area where the insulating layer 148 is arranged.

14, the semiconductor region 120 constituting the node FD in the first substrate 110 is assumed to have the same structure as the configuration example shown in FIG. 8. As shown in FIG. 14(a), the semiconductor region 120 is arranged adjacent to the gate electrode 128 of the transfer transistor M1 in a plan view. The signal charge accumulated in the cathode (semiconductor region 118) of the photoelectric conversion element PD is transferred to the semiconductor region 120 when the transfer transistor M1 is turned on. The semiconductor region 120 is led to the second substrate 140 via the wiring 134 and the through electrode 156, and is electrically connected to the source of the reset transistor M2 and the gate of the amplification transistor M3 arranged on the second substrate 140. In other words, a part of the floating diffusion capacitance, which is the parasitic capacitance of the node FD, is also formed on the second substrate 140 side. For example, in the configuration example of FIG. 14, the source region of the reset transistor M2 is arranged in the semiconductor layer 142, but the PN junction capacitance formed by the source region of this reset transistor M2 also becomes part of the floating diffusion capacitance.

In such a configuration, if the gate electrode 128 of the transfer transistor M1 and the element constituting the floating diffusion capacitance are arranged so as to overlap in a planar view, potential fluctuations due to the control signal PTX of the transfer transistor M1 may affect the stabilization of the potential of the node FD. If the influence of the potential fluctuations of the node FD due to the control signal PTX becomes too large to be ignored, the signal level of the pixel signal cannot be read accurately. In particular, in a configuration in which one node FD is shared by multiple pixels 12, multiple transfer transistors M1 are arranged near the node FD. Since the influence of the potential fluctuations due to the control signal PTX changes depending on the positional relationship between each transfer transistor M1 and the node FD, the stabilization characteristics vary from pixel 12 to pixel 12.

From this perspective, in the photoelectric conversion device of this embodiment, the gate electrode 136 of the transfer transistor M1 and the element that constitutes the floating diffusion capacitance are arranged so as not to overlap in a planar view.

Figure 15 is a cross-sectional view taken along line XV-XV' in Figure 14, and Figure 16 is a cross-sectional view taken along line XVI-XVI' in Figure 14. Figure 17 is a plan view in which the pattern of the gate electrode 128 of the transfer transistor M1 is superimposed on the plan view of Figure 14(b) so as to clarify the positional relationship between the gate electrode 128 of the transfer transistor M1 and the elements arranged on the second substrate 140. As shown in Figures 15 to 17, in the photoelectric conversion device of this embodiment, the gate electrode 128 of the transfer transistor M1 and elements constituting the floating diffusion capacitance such as the source region of the reset transistor M2 are not positioned so as to overlap with each other in a plan view. Therefore, according to the photoelectric conversion device of this embodiment, the effect of potential fluctuation due to the control signal PTX of the transfer transistor M1 on the potential of the node FD can be reduced.

In this way, according to this embodiment, the functionality and characteristics of a stacked photoelectric conversion device can be further improved.

[Fifth embodiment]
A photoelectric conversion device and a manufacturing method thereof according to a fifth embodiment of the present invention will be described with reference to Fig. 18 and Fig. 19. Components similar to those of the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 18 is a process cross-sectional view showing a manufacturing method of the photoelectric conversion device according to this embodiment. Fig. 19 is a schematic cross-sectional view showing the photoelectric conversion device according to this embodiment.

In this embodiment, an example of a method for manufacturing the photoelectric conversion device according to the first to fourth embodiments will be described. In the manufacturing method of this embodiment, the semiconductor layer 142 of the second substrate 140 is formed using an SOI (Semiconductor-On-Insulator) wafer. The manufacturing process of the semiconductor layer 142 will be described below with reference to FIG. 18.

First, a first substrate 110 is formed, which has a semiconductor layer 112 in which a photoelectric conversion element PD, a transfer transistor M1, etc. are formed, and an insulating layer 132 (Figure 18 (a)).

In addition to the first substrate 110, an SOI (Semiconductor On Insulator) substrate 250 is prepared, in which a buried insulating layer 254 and a semiconductor layer 256 are provided on a semiconductor substrate 252. Then, after forming an insulating layer 258 on the semiconductor layer 256 of the SOI substrate 250, the SOI substrate 250 is bonded onto the first substrate 110 so that the insulating layer 132 and the insulating layer 258 face each other (FIG. 18(b)).

Next, the semiconductor substrate 252 and the buried insulating layer 254 are polished from the back surface side of the SOI substrate 250, and the semiconductor substrate 252 and the buried insulating layer 254 are removed. The semiconductor layer 256 thus left on the first substrate 110 becomes the semiconductor layer 142 of the second substrate 140 (FIG. 18(c)). In the following explanation, the insulating layer 258 will be described as part of the insulating layer 132 of the first substrate 110.

Next, an insulating layer 148, an amplifying transistor M3, and the like are formed on the semiconductor layer 142 thus formed (FIG. 18(d)). Then, an insulating layer 152 is formed on the semiconductor layer 142 (FIG. 18(e)).

Next, wiring including a through electrode 156 that penetrates the insulating layer 148 and the insulating layer 132 and is connected to the gate electrode 128 is formed in the insulating layer 152, forming a wiring structure layer 150 (Figure 18 (f)).

A typical manufacturing process that does not use an SOI substrate is to bond a bulk substrate that is not an SOI substrate onto the insulating layer 132, and then thin the bulk substrate by polishing it from the back side to form the semiconductor layer 142. In this method, the thickness of the semiconductor layer 142 is determined by the amount of polishing in the process of polishing the bulk substrate. At this time, the amount of polishing in the process of polishing the bulk substrate is set with a margin of thickness, taking into account the variation in characteristics, etc.

In contrast, when an SOI substrate is used, the thickness of the semiconductor layer 142 is determined by the thickness of the SOI layer (semiconductor layer 256), making it easier to control the thickness of the semiconductor layer 142 and making it thinner than when a bulk substrate is used. Therefore, by forming the semiconductor layer 142 using an SOI substrate, the thickness of the semiconductor layer 142 can be made thinner, for example, as shown in FIG. 19.

Thinning the semiconductor layer 142 has the effect of reducing parasitic capacitance, and is expected to improve operating speed, reduce power consumption, and reduce noise. In addition, the amount of etching required when forming the through electrode 156 can be reduced. This has the advantage of making it easier to form the through electrode 156. On the other hand, it can also be said that a thinner semiconductor layer 142 makes it more susceptible to potential fluctuations from the transfer transistor M1. However, as explained in the fourth embodiment, it is possible to suppress the effects of potential fluctuations by using a layout in which the transfer transistor M1 and the elements that make up the floating diffusion capacitance do not overlap in a planar view.

In this way, according to this embodiment, the functionality and characteristics of a stacked photoelectric conversion device can be further improved.

Sixth Embodiment
A photoelectric conversion system according to a sixth embodiment of the present invention will be described with reference to Fig. 20. Fig. 12 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

The photoelectric conversion device 100 described in the first to fifth embodiments above is applicable to various photoelectric conversion systems. Examples of applicable photoelectric conversion systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in photoelectric conversion systems. Figure 12 shows a block diagram of a digital still camera as an example of these.

The photoelectric conversion system 200 illustrated in FIG. 20 includes an image capture device 201, a lens 202 that forms an optical image of a subject on the image capture device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the image capture device 201. The image capture device 201 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments, and converts the optical image formed by the lens 202 into image data.

The photoelectric conversion system 200 also has a signal processing unit 208 that processes the output signal output from the imaging device 201. The signal processing unit 208 generates image data from the digital signal output by the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output the image data. The imaging device 201 may be equipped with an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I/F unit) 212 for communicating with an external computer or the like. The photoelectric conversion system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I/F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200, or may be removable.

The photoelectric conversion system 200 further includes an overall control/calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from the outside, and the photoelectric conversion system 200 only needs to include at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs a predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

In this way, according to this embodiment, a photoelectric conversion system can be realized that applies the photoelectric conversion device 100 according to the first to fifth embodiments.

[Seventh embodiment]
A photoelectric conversion system and a moving object according to a seventh embodiment of the present invention will be described with reference to Fig. 21. Fig. 21 is a diagram showing the configuration of the photoelectric conversion system and the moving object according to this embodiment.

Figure 21 (a) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fifth embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on multiple image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from multiple image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to the object. In other words, the distance information is information on the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may use any of these pieces of distance information to determine the possibility of a collision. The distance information acquisition means may be realized by dedicated hardware or by a software module. It may also be realized by a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), or by a combination of these.

The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, if the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 applies the brakes, releases the accelerator, suppresses engine output, etc., to avoid the collision and reduce damage by performing vehicle control. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

In this embodiment, the photoelectric conversion system 300 captures the surroundings of the vehicle, for example the front or rear. Figure 21 (b) shows a photoelectric conversion system for capturing an image of the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

Although the above describes an example of control to prevent collisions with other vehicles, the system can also be applied to control of automatic driving to follow other vehicles, and control of automatic driving to avoid straying from lanes. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the system can be applied not only to moving bodies, but also to a wide range of equipment that uses object recognition, such as intelligent transport systems (ITS).

[Eighth embodiment]
An apparatus according to an eighth embodiment of the present invention will be described with reference to Fig. 22. Fig. 22 is a block diagram showing a schematic configuration of the apparatus according to this embodiment.

Figure 22 is a schematic diagram showing an equipment EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 of any one of the first to fifth embodiments. All or a part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used, for example, as an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

The photoelectric conversion device APR may have a structure (chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may also be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected by through-hole vias (TSVs), inter-chip wiring by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

The photoelectric conversion device APR may include, in addition to the semiconductor device IC, a package PKG that houses the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connection members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device IC.

The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes the signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application-specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as SRAM or DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, or transmitted to the outside by a communication device (not shown) provided in the device EQP. For this reason, it is preferable that the device EQP further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and arithmetic circuit unit provided in the photoelectric conversion device APR.

The equipment EQP shown in FIG. 22 can be an electronic device such as an information terminal with a shooting function (e.g., a smartphone or a wearable terminal) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, a surveillance camera). The mechanical device MCHN in the camera can drive parts of the optical device OPT for zooming, focusing, and shutter operation. The equipment EQP can also be transportation equipment (mobile body) such as a vehicle, a ship, or an aircraft. The equipment EQP can also be medical equipment such as an endoscope or a CT scanner. The equipment EQP can also be medical equipment such as an endoscope or a CT scanner.

The mechanical device MCHN in the transport equipment can be used as a moving device. The equipment EQP as a transport equipment is suitable for transporting the photoelectric conversion device APR and for assisting and/or automating driving (piloting) using a photographing function. The processing device PRCS for assisting and/or automating driving (piloting) can perform processing to operate the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser and/or user. Therefore, by installing the photoelectric conversion device APR in equipment EQP, the value of the equipment EQP can also be increased. Therefore, when manufacturing and selling equipment EQP, deciding to install the photoelectric conversion device APR of this embodiment in the equipment EQP is advantageous in terms of increasing the value of the equipment EQP.

[Modified embodiment]
The present invention is not limited to the above-described embodiment, and various modifications are possible.

For example, adding part of the configuration of one embodiment to another embodiment, or replacing part of the configuration of another embodiment, are also embodiments of the present invention.

The circuit configurations of the pixels 12 shown in Figures 3, 4, 10, and 12 are examples and can be modified as appropriate. For example, each pixel 12 may have two or more photoelectric conversion elements. In this case, a configuration in which multiple photoelectric conversion elements share one FD node may be used. A configuration in which multiple photoelectric conversion elements share one microlens to detect a phase difference may also be used as a pupil-splitting pixel. The selection transistor M4 may be provided between the power supply voltage line and the amplification transistor M3. The pixel 12 does not necessarily have to have the selection transistor M4.

The photoelectric conversion systems shown in the sixth and seventh embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 20 and 21.

The present invention can also be realized by supplying a program that realizes one or more of the functions of the above-mentioned embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that realizes one or more functions.

The above embodiments are merely examples of how the present invention can be implemented, and the technical scope of the present invention should not be interpreted in a limiting manner. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

The disclosure of the above embodiment includes the following configurations.
(Configuration 1)
A photoelectric conversion device including a plurality of substrates including a first substrate and a second substrate stacked on top of each other, the photoelectric conversion device having pixels that output signals in response to incident light,
The pixel includes a photoelectric conversion element that generates a charge according to an amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of a source and a drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node,
the first substrate has a first semiconductor layer in which the photoelectric conversion element, the first transistor, and the second transistor are provided;
the second substrate has a second semiconductor layer on which the third transistor is provided.
(Configuration 2)
2. The photoelectric conversion device according to configuration 1, wherein the second transistor is a reset transistor for resetting a potential of the first node.
(Configuration 3)
the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to configuration 2, characterized in that a power supply wiring is electrically connected to the other of the source and the drain of the second transistor via a first through electrode provided to penetrate the second semiconductor layer.
(Configuration 4)
2. The photoelectric conversion device according to configuration 1, wherein the second transistor is a storage transistor for switching a capacitance of the first node.
(Configuration 5)
5. The photoelectric conversion device according to claim 4, wherein the pixel further includes a reset transistor to which one of a source and a drain of the second transistor is electrically connected.
(Configuration 6)
The photoelectric conversion device according to configuration 5, wherein the reset transistor is provided in the first semiconductor layer.
(Configuration 7)
the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to configuration 6, wherein a power supply wiring is electrically connected to the other of the source and the drain of the reset transistor via a first through electrode provided to penetrate the second semiconductor layer.
(Configuration 8)
The photoelectric conversion device according to configuration 5, wherein the reset transistor is provided in the second semiconductor layer.
(Configuration 9)
the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to configuration 8, wherein the reset transistor is electrically connected to the other of the source and the drain of the second transistor via a first through electrode provided to penetrate the second semiconductor layer.
(Configuration 10)
the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to any one of structures 1 to 9, wherein the third transistor is electrically connected to the first node via a second through electrode provided to penetrate the second semiconductor layer.
(Configuration 11)
a plurality of pixels sharing the first node and the third transistor;
The photoelectric conversion device according to configuration 10, wherein the second through electrode is common to the plurality of pixels.
(Configuration 12)
12. The photoelectric conversion device according to any one of Structures 1 to 11, wherein the first substrate does not include wiring containing Al or Cu.
(Configuration 13)
13. The photoelectric conversion device according to any one of Structures 1 to 12, wherein a gate of the first transistor does not overlap an element forming a capacitance between the first node and the gate of the first transistor in a plan view.
(Configuration 14)
A photoelectric conversion device including a plurality of substrates including a first substrate and a second substrate stacked on top of each other, the photoelectric conversion device having pixels that output signals in response to incident light,
The pixel includes a photoelectric conversion element that generates a charge according to an amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of a source and a drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node,
the first substrate has a first semiconductor layer in which the photoelectric conversion element and the first transistor are provided,
the second substrate has a second semiconductor layer in which the second transistor and the third transistor are provided,
a gate of the first transistor does not overlap an element forming a capacitance between the first node and the gate of the first transistor in a plan view.
(Configuration 15)
15. The photoelectric conversion device according to configuration 14, wherein the element is one of the source and the drain of the second transistor.
(Configuration 16)
15. The photoelectric conversion device according to claim 14, wherein the element is a gate of the third transistor.
(Configuration 17)
17. The photoelectric conversion device according to any one of structures 1 to 16, wherein the pixel further includes a selection transistor provided in the second semiconductor layer and electrically connected to one of a source and a drain of the third transistor.
(Configuration 18)
18. The photoelectric conversion device according to any one of Structures 1 to 17, wherein the plurality of substrates further include a third substrate provided with a signal processing circuit that processes the signal output from the pixel.
(Configuration 19)
A photoelectric conversion device according to any one of structures 1 to 18,
and a signal processing device that processes a signal output from the photoelectric conversion device.
(Configuration 20)
A mobile object,
A photoelectric conversion device according to any one of structures 1 to 18,
a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device;
and a control means for controlling the moving body based on the distance information.
(Configuration 21)
A photoelectric conversion device according to any one of structures 1 to 18,
an optical device corresponding to the photoelectric conversion device;
A control device for controlling the photoelectric conversion device;
a processing device that processes a signal output from the photoelectric conversion device;
a mechanical device controlled based on information obtained by the photoelectric conversion device;
A display device that displays information obtained by the photoelectric conversion device; and
and a storage device that stores information obtained by the photoelectric conversion device.

M1, M1A, M1B, M1C, M1D...transfer transistor M2...reset transistor M3...amplification transistor M4...selection transistor M5...storage transistors PD, PDA, PDB, PDC, PDD...photoelectric conversion element 110...first substrate 112...first semiconductor layer 140...second substrate 142...second semiconductor layer 170...third substrate 172...third semiconductor layer

Claims (21)

A photoelectric conversion device including a plurality of substrates including a first substrate and a second substrate stacked on top of each other, the photoelectric conversion device having pixels that output signals in response to incident light,
The pixel includes a photoelectric conversion element that generates a charge according to an amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of a source and a drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node,
the first substrate has a first semiconductor layer in which the photoelectric conversion element, the first transistor, and the second transistor are provided;
the second substrate has a second semiconductor layer on which the third transistor is provided. The photoelectric conversion device according to claim 1 , wherein the second transistor is a reset transistor for resetting a potential of the first node. the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to claim 2 , characterized in that a power supply wiring is electrically connected to the other of the source and the drain of the second transistor via a first through electrode provided to penetrate the second semiconductor layer. The photoelectric conversion device according to claim 1 , wherein the second transistor is a storage transistor for switching a capacitance of the first node. The photoelectric conversion device according to claim 4 , wherein the pixel further comprises a reset transistor to which one of a source and a drain of the second transistor is electrically connected. The photoelectric conversion device according to claim 5 , wherein the reset transistor is provided in the first semiconductor layer. the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to claim 6 , characterized in that a power supply wiring is electrically connected to the other of the source and the drain of the reset transistor via a first through electrode provided to penetrate the second semiconductor layer. The photoelectric conversion device according to claim 5 , wherein the reset transistor is provided in the second semiconductor layer. the second substrate is bonded to the first substrate face-to-back;
The photoelectric conversion device according to claim 8 , characterized in that the reset transistor is electrically connected to the other of the source and the drain of the second transistor via a first through electrode provided to penetrate the second semiconductor layer. the second substrate is bonded to the first substrate face-to-back;
10. The photoelectric conversion device according to claim 1 , wherein the third transistor is electrically connected to the first node via a second through electrode provided to penetrate the second semiconductor layer. a plurality of pixels sharing the first node and the third transistor;
The photoelectric conversion device according to claim 10 , wherein the second through electrode is common to the plurality of pixels. The photoelectric conversion device according to claim 1 , wherein the first substrate does not include wiring containing Al or Cu. 10 . The photoelectric conversion device according to claim 1 , wherein a gate of the first transistor does not overlap an element forming a capacitance between the first node and the gate of the first transistor in a plan view. A photoelectric conversion device including a plurality of substrates including a first substrate and a second substrate stacked on top of each other, the photoelectric conversion device having pixels that output signals in response to incident light,
The pixel includes a photoelectric conversion element that generates a charge according to an amount of incident light, a first transistor that transfers the charge held by the photoelectric conversion element to a first node, a second transistor having one of a source and a drain electrically connected to the first node, and a third transistor having a gate electrically connected to the first node,
the first substrate has a first semiconductor layer in which the photoelectric conversion element and the first transistor are provided,
the second substrate has a second semiconductor layer in which the second transistor and the third transistor are provided,
a gate of the first transistor does not overlap an element forming a capacitance between the first node and the gate of the first transistor in a plan view. The photoelectric conversion device according to claim 14 , wherein the element is the one of the source and the drain of the second transistor. The photoelectric conversion device according to claim 14 , wherein the element is a gate of the third transistor. 10. The photoelectric conversion device according to claim 1, wherein the pixel further includes a selection transistor provided in the second semiconductor layer and electrically connected to one of a source and a drain of the third transistor. 10. The photoelectric conversion device according to claim 1, wherein the plurality of substrates further include a third substrate provided with a signal processing circuit that processes the signal output from the pixel. The photoelectric conversion device according to claim 1 ,
and a signal processing device that processes a signal output from the photoelectric conversion device. A mobile object,
The photoelectric conversion device according to claim 1 ,
a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device;
and a control means for controlling the moving body based on the distance information. The photoelectric conversion device according to claim 1 ,
an optical device corresponding to the photoelectric conversion device;
A control device for controlling the photoelectric conversion device;
a processing device that processes a signal output from the photoelectric conversion device;
a mechanical device controlled based on information obtained by the photoelectric conversion device;
A display device that displays information obtained by the photoelectric conversion device; and
and a storage device that stores information obtained by the photoelectric conversion device.