JP2024031747A - Driving circuit and switching power supply - Google Patents

Abstract

To reduce switching losses (Ron losses).SOLUTION: A driving circuit 10 includes: a first transistor 11 and a second transistor 12, configured to be connected in parallel between a control end (i.e., an application end of an upper-side gate signal HG) of a transistor to be driven and an application end of ON-state voltage BST; and a controller 13 configured to turn on the first transistor 11 at beginning of an on-transition period of the transistor to be driven, and also turn on the second transistor 12 in middle of the on-transition period.SELECTED DRAWING: Figure 4

Description

The present disclosure relates to a drive circuit and a switching power supply.

Switching power supplies are installed in various devices (see, for example, Patent Document 1).

Japanese Patent Application Publication No. 2021-191109

However, with conventional switching power supplies (particularly the drive circuits used therein), there is room for consideration in reducing switching loss.

For example, the drive circuit disclosed in this specification includes a first transistor and a second transistor configured to be connected in parallel between a control terminal of a transistor to be driven and an application terminal of an on-voltage; The controller includes a controller configured to turn on the first transistor at the beginning of an on-transition period of the transistor to be driven, and then turn on the second transistor halfway through.

Note that other features, elements, steps, advantages, and characteristics will become clearer from the detailed description that follows and the accompanying drawings related thereto.

According to the present disclosure, it is possible to provide a drive circuit that can reduce switching loss and a switching power supply using the drive circuit.

FIG. 1 is a diagram showing an example of a configuration of a switching power supply. FIG. 2 is a diagram showing an example of the operation of the switching power supply. FIG. 3 is a diagram showing switching loss (Ron loss). FIG. 4 is a diagram showing a first embodiment of the drive circuit. FIG. 5 is a diagram illustrating an example of loss reduction operation in the first embodiment. FIG. 6 is a diagram showing a second embodiment of the drive circuit. FIG. 7 is a diagram illustrating an example of loss reduction operation in the second embodiment. FIG. 8 is a diagram showing a third embodiment of the drive circuit. FIG. 9 is a diagram showing how ringing occurs in the gate signal. FIG. 10 is a diagram showing how ringing of a gate signal is suppressed. FIG. 11 is a diagram showing how a trade-off occurs in on-timing control. FIG. 12 is a diagram showing a fourth embodiment of the drive circuit. FIG. 13 is a diagram showing how the conflict in on-timing control is resolved.

<Switching power supply>
FIG. 1 is a diagram showing an example of a configuration of a switching power supply. The switching power supply 1 of this configuration example is a non-insulated DC/DC converter that steps down the input voltage IN and generates the output voltage OUT. Referring to this figure, the switching power supply 1 includes an output transistor N1 (for example, an NMOSFET [N-channel type metal oxide semiconductor field effect transistor]), a synchronous rectifier transistor N2 (for example, an NMOSFET), a capacitor C1, and an inductor. L1 and a drive circuit 10.

The drain of the output transistor N1 is connected to the application terminal of the input voltage IN. The source of the output transistor N1, the drain of the synchronous rectifier transistor N2, and the first end of the inductor L1 are all connected to the application end of the switch voltage SW. The second end of the inductor L1 and the first end of the capacitor C1 are both connected to the application end of the output voltage OUT. The source of the synchronous rectifier transistor N2 and the second end of the capacitor C2 are both connected to a ground terminal (=terminal to which ground voltage GND is applied). The gates of the output transistor N1 and the synchronous rectifier transistor N2 are connected to the output end of the drive circuit 10 (the application end of the upper gate signal HG and the lower gate signal LG, respectively).

In the switching power supply 1 of this configuration example, when the upper gate signal HG is at a high level and the lower gate signal LG is at a low level, the output transistor N1 is turned on and the synchronous rectification transistor N2 is turned off. At this time, the switch voltage SW becomes high level (≈IN).

On the other hand, when the upper gate signal HG is at a low level and the lower gate signal LG is at a high level, the output transistor N1 is turned off and the synchronous rectification transistor N2 is turned on. At this time, the switch voltage SW becomes low level (≈GND).

In this way, the output transistor N1 and the synchronous rectification transistor N2 forming the half-bridge output stage are turned on and off in a complementary manner according to the upper gate signal HG and the lower gate signal LG. As a result, switch voltage SW is pulsed between input voltage IN and ground voltage GND. Inductors L1 and C1 rectify and smooth the rectangular waveform switch voltage SW to generate an output voltage OUT.

Note that in the switching power supply 1 having a half-bridge output stage, switching loss (Ron loss) occurs in both the output transistor N1 and the synchronous rectification transistor N2.

FIG. 2 is a diagram showing an example of the operation of the switching power supply 1 (low duty condition). In this figure, an upper gate signal HG, a lower gate signal LG, and a switch voltage SW are depicted in order from the top.

In recent years, as an advanced technology to improve the power density of step-down DC/DC converters, the applicant has developed an ultra-high-speed pulse control technology (Nano Pulse Control (registered trademark)) that can set an extremely low on-duty Don. is proposed. Note that the on-duty Don is defined as the ratio of the on-time Ton of the output transistor N1 to the switching period T (=Ton/T).

Furthermore, GaN devices are emerging as an approach to meet the large power requirements in the recent power supply IC market. For example, GaN devices are used as the aforementioned output transistor N1 and synchronous rectifier transistor N2. Note that the gate-source breakdown voltage of a GaN device is generally 10V or less.

For example, when the drive control of the output transistor N1 using a GaN device is performed using the ultra-high-speed pulse control technology described above, the minimum on-time Ton of the output transistor N1 is set to less than 20 ns (several ns to 20 ns). can be done.

By the way, the gate capacitance of a GaN device is smaller than that of a Si device. Therefore, GaN devices have smaller switching losses due to gate capacitance than Si devices. Therefore, in GaN devices, switching loss (Ron loss) due to on-resistance tends to become apparent. In particular, when a GaN device is driven under low duty conditions, the Ron loss may appear particularly large.

FIG. 3 is a diagram showing switching loss (Ron loss) of the switching power supply 1. As shown in FIG. In this figure, from the top, the switch voltage SW, the gate-source voltage VgsH of the output transistor N1, the drain-source voltage VdsH, the drain-source current IdsH, and the on-resistance RonH (=VdsH/IdsH) are depicted. has been done.

Note that the drain-source voltage VdsH and the on-resistance RonH are depicted enlarged in the vertical axis direction. Furthermore, the left side of the figure shows behavior under high duty conditions. On the other hand, the right side of the figure shows behavior under low duty conditions.

First, the behavior under high duty conditions will be explained with reference to the left side of the figure. At time t11, when the gate-source voltage VgsH of the output transistor N1 begins to rise, the drain-source current IdsH begins to flow. On the other hand, at this point, the switch voltage SW is maintained at a low level (≈GND).

At time t12, when the drain-source current IdsH stops increasing, the drain-source voltage VdsH begins to decrease. Note that as the drain-source voltage VdsH decreases, the switch voltage SW increases and the on-resistance RonH decreases.

Further, at time t12, the gate-source voltage VgsH reaches a state where it temporarily stagnates near the plateau voltage Vp. The operating region (=times t12 to t13) in which the gate-source voltage VgsH increases slowly in this way is generally called a plateau region. Note that the plateau region can be understood as a charging period of the gate capacitance associated between the gate and drain of the output transistor N1.

At time t13, when the plateau region of the output transistor N1 expires, the gate-source voltage VgsH starts to rise again. Furthermore, the drain-source voltage VdsH continues to decrease more slowly than in the plateau region described above. Note that as the drain-source voltage VdsH decreases, the on-resistance RonH also decreases relatively slowly.

At time t14, the gate-source voltage VgsH reaches the bootstrap voltage BST, and the drain-source voltage VdsH and on-resistance RonH reach their respective minimum values. That is, the output transistor N1 becomes fully on.

By the way, during the Ron loss period T1 (=time t13 to t14) in this figure, the drain-source current IdsH flows while the on-resistance RonH has not completely decreased to the minimum value. Therefore, a switching loss (Ron loss) occurs in the output transistor N1.

However, under high duty conditions, the high level period T2 (=from time t13) of the switch voltage SW is much longer than the Ron loss period T1 (T1<<T2). In other words, the ratio of the Ron loss period T1 to the high level period T2 (=T1/T2) is extremely small. Therefore, the above-mentioned switching loss (Ron loss) is less likely to become apparent.

Next, the behavior under low duty conditions will be explained with reference to the right side of the figure. Note that the behavior from time t21 to t23 (=behavior until the plateau region expires) is similar to the behavior from time t11 to t13 described above. Therefore, below, the behavior after time t23 will be described in detail.

At time t23, when the plateau region of the output transistor N1 expires, the on-resistance RonH also decreases relatively gently as the drain-source voltage VdsH decreases. This behavior is no different from the behavior under high duty conditions.

However, under low duty conditions, the off transition of output transistor N1 may begin before output transistor N1 reaches a fully on state. Referring to the figure, at time t24, the high level period T2 of the switch voltage SW has expired before the drain-source voltage VdsH and the on-resistance RonH reach their respective minimum values. Therefore, in the example of this figure, the Ron loss period T1 coincides with the high level period T2 of the switch voltage SW (T1=T2).

In this way, under the low duty condition, the ratio of the Ron loss period T1 to the high level period T2 (=T1/T2) increases. Therefore, the above-mentioned switching loss (Ron loss) becomes more likely to become apparent.

In view of the above considerations, a drive circuit 10 that can reduce switching loss (Ron loss) under low duty conditions will be proposed below.

<Drive circuit (first embodiment)>
FIG. 4 is a diagram showing a first embodiment of the drive circuit 10. The drive circuit 10 of the present embodiment includes a transistor 11 (=corresponds to a first transistor, for example, an NMOSFET), a transistor 12 (=corresponds to a second transistor, for example, a PMOSFET [P-channel type MOSFET]), a controller 13, including.

The drain of the transistor 11 and the source of the transistor 12 are both connected to an application terminal of a bootstrap voltage BST (=SW+Vc, where Vc is a charging voltage of a bootstrap capacitor (not shown)). The source of the transistor 11 and the drain of the transistor 12 are both connected to the application terminal of the upper gate signal HG.

Thus, transistors 11 and 12 are connected in parallel between the gate of output transistor N1 and the terminal to which bootstrap voltage BST is applied. Note that the output transistor N1 corresponds to a transistor to be driven when viewed from the drive circuit 10. Further, the bootstrap voltage BST corresponds to the on-voltage of the output transistor N1.

The transistor 11 may be an N-channel type (corresponding to a first channel type). The transistor 12 may be of a P-channel type (corresponding to a second channel type different from the first channel type).

A drive input signal DRVIN is applied to the gate of the transistor 11. Therefore, the transistor 11 is turned on when the drive input signal DRVIN is at a high level (for example, BST), and is turned off when the drive input signal DRVIN is at a low level (for example, HG). Note that the drive input signal DRVIN is generated by an output feedback circuit (not shown) so that a desired output voltage OUT can be obtained from the input voltage IN.

A NAND signal S2 (details will be described later) is applied to the gate of the transistor 12. Therefore, the transistor 12 is turned off when the NAND signal S2 is at a high level (for example, BST), and is turned on when the NAND signal S2 is at a low level (for example, HG).

The controller 13 generates the aforementioned NAND signal S2 so that the transistor 11 is turned on at the beginning of the on-transition period of the output transistor N1, and the transistor 12 is also turned on in the middle.

Referring to the figure, the controller 13 includes a comparator CMP and a negative AND gate NAND.

The comparator CMP generates a comparison signal by comparing the switch voltage SW input to the non-inverting input terminal (+) and a predetermined threshold voltage Vref (for example, IN-5V) input to the inverting input terminal (-). Generate S1. Therefore, the comparison signal S1 becomes a high level when the switch voltage SW is higher than the threshold voltage Vref, and becomes a low level when the switch voltage SW is lower than the threshold voltage Vref.

The NAND gate NAND (=corresponding to a logic gate) outputs a NAND signal S2 so as to turn on/off the transistor 12 according to the comparison signal S1 and the upper gate signal HG (=corresponding to the control signal of the transistor to be driven). generate. The NAND signal S2 becomes a high level when at least one of the comparison signal S1 and the upper gate signal HG is at a low level, and becomes a low level when both the comparison signal S1 and the upper gate signal HG are at a high level. .

In this manner, the controller 13 of this configuration example determines the on-timing of the transistor 12 according to the comparison result between the switch voltage SW appearing at one end (source) of the output transistor N1 and the predetermined threshold voltage Vref.

Referring to this figure, the controller 13 turns on the transistor 12 when the switch voltage SW is higher than the threshold voltage Vref and the upper gate signal HG is at a high level (=logic level when on). shall be.

FIG. 5 is a diagram illustrating an example of loss reduction operation in the first embodiment. In this figure, from top to bottom, the drive input signal DRVIN, switch voltage SW, gate-source voltage VgsH of output transistor N1, drain-source voltage VdsH, drain-source current IdsH, and on-resistance RonH (=VdsH /IdsH) is depicted.

Note that the drain-source voltage VdsH and the on-resistance RonH are depicted enlarged in the vertical axis direction. Further, in this figure, like the right side of FIG. 3 described above, behavior under a low duty condition is shown.

At time t31, when the drive input signal DRVIN is raised to a high level, the transistor 11 is turned on. As a result, when the gate-source voltage VgsH of the output transistor N1 begins to rise, the drain-source current IdsH begins to flow. On the other hand, at this point, the switch voltage SW is maintained at a low level (≈GND<Vref). Therefore, transistor 12 remains off.

At time t32, when the drain-source current IdsH stops increasing, the drain-source voltage VdsH begins to decrease. Note that as the drain-source voltage VdsH decreases, the switch voltage SW increases and the on-resistance RonH decreases.

Further, at time t32, the gate-source voltage VgsH reaches a state where it temporarily stagnates near the plateau voltage Vp (plateau region).

At time t33, when the plateau region of the output transistor N1 expires, the gate-source voltage VgsH starts to rise again. At this point, switch voltage SW has reached threshold voltage Vref. Therefore, not only transistor 11 but also transistor 12 is turned on. As a result, the gate-source voltage VgsH rises steeply compared to the previous behavior shown by the broken line (corresponding to the right side of FIG. 3). Furthermore, the drain-source voltage VdsH and the on-resistance RonH also decrease sharply compared to the previous behavior shown by the broken line.

At time t34, the gate-source voltage VgsH reaches the bootstrap voltage BST, and the drain-source voltage VdsH and on-resistance RonH reach their respective minimum values. That is, the output transistor N1 becomes fully on.

At time t35, when the drive input signal DRVIN falls to a low level, both transistors 11 and 12 are turned off, and the high level period T2 of the switch voltage SW ends.

In the series of loss reduction operations described above, only the transistor 11 is turned on at the beginning of the on-transition period of the output transistor N1 (=time t31 to t33), and from the middle of the on-transition period of the output transistor N1 (=time t33) Transistor 12 is also turned on.

As a result, the on-resistance RonH is minimized in a shorter time after the plateau region expires. Therefore, the Ron loss period T1' (=time t33 to t34) is shortened compared to the previous Ron loss period T1 (=time t33 to t35). In other words, the Ron loss period T1' is shorter than the high level period T2 (=times t33 to t35) of the switch voltage SW (T1'<T2=T1). Therefore, the aforementioned switching loss (Ron loss) is less likely to become apparent.

<Drive circuit (second embodiment)>
FIG. 6 is a diagram showing a second embodiment of the drive circuit 10. The drive circuit 10 of this embodiment includes a transistor 14 (corresponding to a third transistor, for example, an NMOSFET) and diodes 15 and 16, in addition to the transistors 11 and 12 and the controller 13 described above.

The drain of the transistor 14 is connected to the application terminal of the upper gate signal HG (=gate of the output transistor N1). The source of the transistor 14 is connected to the application terminal of the switch voltage SW. The gate of the transistor 14 is connected to the application terminal of the inverted drive input signal xDRVIN.

The transistor 14 connected in this manner is turned on when the inverted drive input signal xDRVIN is at a high level, and turned off when the inverted drive input signal xDRVIN is at a low level.

Note that the inverted drive input signal xDRVIN is basically a logical inversion signal of the drive input signal DRVIN. Therefore, transistors 11 and 14 are controlled on/off in a complementary manner. However, in order to prevent an excessive through current from flowing through the transistors 11 and 14, a so-called dead time (=simultaneous OFF period of the transistors 11 and 14) is provided in the drive input signal DRVIN and the inverted drive input signal xDRVIN. good.

The cathode of the diode 15 is connected to the application terminal of the bootstrap voltage BST (=on voltage). The anode of the diode 15 is connected to the application end of the upper gate signal HG. The diode 15 connected in this manner functions as a voltage clamp element between BST and HG.

The cathode of the diode 16 is connected to the application end of the upper gate signal HG. The anode of the diode 16 is connected to the application end of the switch voltage SW. The diode 16 connected in this manner functions as a voltage clamp element between HG and SW.

Furthermore, in the drive circuit 10 of this embodiment, the internal configuration of the controller 13 has been changed. Referring to the figure, the controller 13 includes transistors N11 to N15 (for example, NMOSFET), transistors P11 to P14 (for example, PMOSFET), resistors R1 and R2, and inverters INV1 and INV2.

The sources of transistors P11 to P14 are all connected to the application terminal of bootstrap voltage BST. The sources of the transistors N12 to N14 are all connected to the application terminal of the switch voltage SW.

The drains of transistors P11 and N11 are both connected to the terminal to which node voltage V1 is applied. The gates of transistors P11 and N11 are both connected to the application terminal of upper gate signal HG. The source of transistor N11 is connected to the drains of transistors N12 and N13. The gate of transistor N12 is connected to the drain of transistor N12. The gate of transistor N13 is connected to the drain of transistor N14. The gates of transistors P12 and N14 are both connected to the application terminal of node voltage V1. The drains of transistors P12 and N14 are both connected to the terminal to which node voltage V2 is applied.

A first end of the resistor R1 is connected to an application end of the input voltage IN. The second end of the resistor R1 is connected to the drain of the transistor N15. The gates of transistors N15 and P13 are both connected to the application terminal of node voltage V2. The drain of transistor P14 is connected to the first end of resistor R2. The source of the transistor N15, the drain of the transistor P13, the second end of the resistor R2, and the input end of the inverter INV1 are all connected to the application end of the node voltage V3. The gate of the transistor P14, the output terminal of the inverter INV1, and the input terminal of the inverter INV2 are all connected to the application terminal of the node voltage V4. The output end of the inverter INV2 and the gate of the transistor 12 are both connected to the application end of the node voltage V5.

Note that among the above components, the transistor N15 corresponds to an N-channel transistor connected between the application terminal of the input voltage IN and the internal node (=the application terminal of the node voltage V3). Further, the transistor P13 corresponds to a P-channel transistor connected between the application end of the on-voltage (=bootstrap voltage BST) and the internal node (=the application end of the node voltage V3).

When the drive input signal DRVIN rises to a high level (=BST), the upper gate signal HG becomes a high level (=BST−Vth(11), where Vth(11) is the on-threshold voltage of the transistor 11). At this time, the transistor P11 is turned off, and the transistor N11 is turned on. Therefore, the node voltage V1 becomes a low level (=SW+Vth(N12), where Vth(N12) is the on-threshold voltage of the transistor N12).

When the node voltage V1 falls to a low level, the transistor P12 is turned on and the transistor N14 is turned off. As a result, the node voltage V2 becomes high level (=BST). In this way, when the drive input signal DRVIN is at a high level, that is, when the transistor 11 is in the on state, the bootstrap voltage BST (=on voltage) is applied to the gates of each of the transistors N15 and P13.

Here, when the bootstrap voltage BST becomes higher than the input voltage IN, the node voltage V3 becomes a low level (≈IN). Therefore, the node voltage V4 becomes high level and the node voltage V5 becomes low level. As a result, transistor 12 is turned on.

In this way, in the drive circuit 10 of this embodiment, the controller 13 controls the voltage of the transistor 12 according to the comparison result between the input voltage IN applied to the drain of the output transistor N1 and the bootstrap voltage BST (=ON voltage). Determine the on timing.

FIG. 7 is a diagram illustrating an example of loss reduction operation in the second embodiment. In this figure, in order from the top, the drive input signal DRVIN, bootstrap voltage BST (solid line), node voltage V3 (small broken line), switch voltage SW (large broken line), and gate-source voltage of output transistor N1 VgsH, drain-source voltage VdsH, drain-source current IdsH, and on-resistance RonH (=VdsH/IdsH) are depicted.

Note that the drain-source voltage VdsH and the on-resistance RonH are depicted enlarged in the vertical axis direction. Further, this figure shows the behavior under low duty conditions, as in the right side of FIG. 3 and FIG. 5 mentioned earlier. Furthermore, an enlarged view of the area α is depicted in the speech bubble frame.

At time t41, when the drive input signal DRVIN is raised to a high level, the transistor 11 is turned on. As a result, when the gate-source voltage VgsH of the output transistor N1 begins to rise, the drain-source current IdsH begins to flow. On the other hand, at this point, the switch voltage SW is maintained at a low level (≈GND), so the bootstrap voltage BST (=SW+Vc) is lower than the input voltage IN. Further, the node voltage V3 becomes a high level (=BST-Vth(N15), where Vth(N15) is the on-threshold voltage of the transistor N15). Therefore, transistor 12 remains off.

At time t42, when the drain-source current IdsH stops increasing, the drain-source voltage VdsH begins to decrease. Note that as the drain-source voltage VdsH decreases, the switch voltage SW increases and the on-resistance RonH decreases.

Further, at time t42, the gate-source voltage VgsH reaches a state where it temporarily stagnates near the plateau voltage Vp (plateau region).

At time t43, when the plateau region of the output transistor N1 expires, the gate-source voltage VgsH starts to rise again.

Note that at time tx, the bootstrap voltage BST exceeds the input voltage IN prior to the expiration of the above-described plateau region. Therefore, since the node voltage V3 becomes a low level (≈IN), not only the transistor 11 but also the transistor 12 is turned on. As a result, the gate-source voltage VgsH rises steeply compared to the previous behavior shown by the broken line (corresponding to the right side of FIG. 3). Furthermore, the drain-source voltage VdsH and the on-resistance RonH also decrease sharply compared to the previous behavior shown by the broken line.

In this way, in the drive circuit 10 (particularly the controller 13) of this embodiment, instead of the configuration of the first embodiment (FIG. 4) in which the switch voltage SW and the threshold voltage Vref are compared using the comparator CMP (FIG. 4), Therefore, a configuration is adopted in which the bootstrap voltage BST and the input voltage IN are compared using the transistor N15. According to this configuration, the node voltage V3 is switched to a low level (≈IN) before the bootstrap voltage BST rises completely. Therefore, unlike the first embodiment mentioned earlier, there is no need to consider signal delay in the comparator CMP.

At time t44, the gate-source voltage VgsH reaches the bootstrap voltage BST, and the drain-source voltage VdsH and on-resistance RonH reach their respective minimum values. That is, the output transistor N1 becomes fully on.

At time t45, when the drive input signal DRVIN falls to a low level, both transistors 11 and 12 are turned off, and the high level period T2 of the switch voltage SW ends.

According to the series of loss reduction operations described above, as in the first embodiment, only the transistor 11 is turned on at the beginning of the on-transition period of the output transistor N1 (=times t41 to t43), and the output transistor N1 The transistor 12 is also turned on from the middle of the on-transition period (=time t43).

As a result, the on-resistance RonH is minimized in a shorter time after the plateau region expires. Therefore, the Ron loss period T1' (=time t43 to t44) is shortened compared to the previous Ron loss period T1 (=time t43 to t45). In other words, the Ron loss period T1' is shorter than the high level period T2 (=times t43 to t45) of the switch voltage SW (T1'<T2=T1). Therefore, the aforementioned switching loss (Ron loss) is less likely to become apparent.

Note that the loss reduction operations in the first and second embodiments described above are always performed regardless of the on-duty Don. Therefore, not only a loss reduction effect under low duty conditions but also a considerable loss reduction effect under high duty conditions can be expected.

<Modified example>
In the above embodiment, a configuration is exemplified in which the on-resistance of the output transistor N1 forming the half-bridge output stage is minimized to reduce switching loss (Ron loss) under low duty conditions. However, the scope of application of the present disclosure is not limited to this.

For example, one possible modification is a configuration in which the on-resistance of the synchronous rectifier transistor N2 is minimized to reduce switching loss (Ron loss) under high duty conditions.

Further, the present disclosure is useful not only when driving GaN devices but also when driving Si devices.

<Drive circuit (third embodiment)>
FIG. 8 is a diagram showing a third embodiment of the drive circuit 10. The drive circuit 10 of this embodiment includes the aforementioned transistors 11 and 12, a controller 13, and a transistor 14 as components of the upper driver DRVH that drives the output transistor N1. Note that the controller 13 includes an inverter INV3.

The drain of the transistor 11 and the source of the transistor 12 are both connected to the application terminal of the bootstrap voltage BST (=the drain of the output transistor N1). The source of the transistor 11 and the drains of the transistors 12 and 14 are both connected to the application terminal of the upper gate signal HG (=gate of the output transistor N1). The source of the transistor 14 is connected to the application terminal of the switch voltage SW (=the source of the output transistor N1). The gate of the transistor 11 and the input terminal of the inverter INV3 are both connected to the application terminal of the upper drive input signal DINH. The gates of the transistors 12 and 14 are both connected to the application terminal of the inverted upper drive input signal xDINH (=the output terminal of the inverter INV3).

The transistor 11 is turned on when the upper drive input signal DINH is at a high level. Further, the transistor 11 is turned off when the upper drive input signal DINH is at a low level.

The transistor 12 is turned off when the inverted upper drive input signal xDINH is at a high level. Further, the transistor 12 is turned on when the inverted upper drive input signal xDINH is at a low level.

The transistor 14 is turned on when the inverted upper drive input signal xDINH is at a high level. Further, the transistor 14 is turned off when the inverted upper drive input signal xDINH is at a low level.

Inverter INV3 inverts the logic level of upper drive input signal DINH to generate an inverted upper drive input signal xDINH. The inverted upper drive input signal xDINH is at a low level when the upper drive input signal DINH is at a high level. Further, the inverted upper drive input signal xDINH is at a high level when the upper drive input signal DINH is at a low level.

Note that the inverted upper drive input signal xDINH falls to a low level with a delay corresponding to the signal delay at the inverter INV3 after the upper drive input signal DINH rises to a high level. Therefore, during the on-transition period of the output transistor N1, initially only the transistor 11 is in the on state, and later on, the transistor 12 is also in the on state.

Further, the drive circuit 10 of the present embodiment includes a transistor 17 (corresponding to the first transistor of the lower driver DRVL, for example, an NMOSFET) and a transistor 18 ( =corresponding to the second transistor of the lower driver DRVL, for example, a PMOSFET), a controller 19, and a transistor 1A (=corresponding to the third transistor of the lower driver DRVL, for example, an NMOSFET). Note that the controller 19 includes an inverter INV4.

The drain of the transistor 17 and the source of the transistor 18 are both connected to the application terminal of the internal power supply voltage VREG (=the drain of the synchronous rectification transistor N2). The source of the transistor 17 and the drains of the transistors 18 and 1A are both connected to the application terminal of the lower gate signal LG (=gate of the synchronous rectification transistor N2). The source of the transistor 1A is connected to a ground terminal, that is, an application terminal of the ground voltage GND (=source of the synchronous rectification transistor N2). The gate of the transistor 17 and the input terminal of the inverter INV4 are both connected to the application terminal of the lower drive input signal DINL. The gates of the transistors 18 and 1A are both connected to the application terminal of the inverted lower drive input signal xDINL (=the output terminal of the inverter INV4).

The transistor 17 is turned on when the lower drive input signal DINL is at a high level. Furthermore, the transistor 17 is turned off when the lower drive input signal DINL is at a low level.

The transistor 18 is turned off when the inverted lower drive input signal xDINL is at a high level. Further, the transistor 18 is turned on when the inverted lower drive input signal xDINL is at a low level.

The transistor 1A is turned on when the inverted lower drive input signal xDINL is at a high level. Further, the transistor 1A is turned off when the inverted lower drive input signal xDINL is at a low level.

Inverter INV4 inverts the logic level of lower drive input signal DINL to generate an inverted lower drive input signal xDINL. The inverted lower drive input signal xDINL is at a low level when the lower drive input signal DINL is at a high level. Further, the inverted lower drive input signal xDINL is at a high level when the lower drive input signal DINL is at a low level.

Note that the inverted lower drive input signal xDINL falls to a low level with a delay corresponding to the signal delay at the inverter INV4 after the lower drive input signal DINL rises to a high level. Therefore, during the on-transition period of the synchronous rectifier transistor N2, only the transistor 17 is initially turned on, and halfway through, the transistor 18 is also turned on.

<Considerations regarding gate signal ringing>
FIG. 9 is a diagram showing how ringing occurs in the upper gate signal HG when it is assumed that the previously mentioned transistor 11 is not introduced. Note that the rising behavior (ideal behavior) of the upper gate signal HG without ringing is depicted on the left side of the figure. On the other hand, on the right side of the figure, the rising behavior of the upper gate signal HG accompanied by ringing is depicted.

If the N-channel type transistor 11 is not introduced, the upper gate signal HG is raised to a high level using only the P-channel type transistor 12 during the on-transition period of the output transistor N1. In this case, the upper gate signal HG is pulled up to the bootstrap voltage BST via the transistor 12 (see the left side of the figure).

Therefore, if ringing occurs in the upper gate signal HG for some reason, there is a risk that the upper gate signal HG will exceed the gate breakdown voltage of the output transistor N1 and overshoot (see the right side of the figure). In particular, GaN devices have a lower gate breakdown voltage than typical Si devices, so countermeasures against overshoot can be important.

FIG. 10 is a diagram showing how ringing of the upper gate signal HG is suppressed by introducing the transistor 11 mentioned above. Similar to the previous FIG. 9, the rising behavior (ideal behavior) of the upper gate signal HG without ringing is depicted on the left side of this figure. On the other hand, on the right side of the figure, the rising behavior of the upper gate signal HG accompanied by ringing is depicted.

When the N-channel type transistor 11 is introduced, only the transistor 11 is initially in the on state during the on period of the output transistor N1. In this case, the upper gate signal HG rises only to a voltage (=BST-Vth) lower than the bootstrap voltage BST by the on-threshold voltage Vth of the transistor 11 (see the right side of the figure). Therefore, even if ringing occurs in the upper gate signal HG, the upper gate signal HG is less likely to exceed the gate breakdown voltage of the output transistor N1 and overshoot.

Note that although the explanation in FIGS. 9 and 10 focuses on the upper gate signal HG, the same can be said for the lower gate signal LG.

<Considerations regarding PMOSFET on-timing control>
As described above, in a configuration in which the NMOSFET and PMOSFET connected in parallel are sequentially turned on, it is important to appropriately set the turn-on timing of the PMOSFET.

For example, the plateau region (=region where the gate-source voltage VgsL temporarily stagnates near the plateau voltage Vp) of the synchronous rectifier transistor N2 is different between heavy load and light load. More specifically, the plateau region of the synchronous rectifier transistor N2 tends to become longer as the load becomes lighter.

However, if the on-timing of the transistor 18 is fixedly set according to the optimum timing under light load, the on-timing of the transistor 18 is delayed from the optimum timing under heavy load when the load is heavy. As a result, Ron loss cannot be suppressed sufficiently.

Conversely, if the on-timing of the transistor 18 is fixed in accordance with the optimum timing under heavy load, the on-timing of the transistor 18 during light load will be earlier than the optimum timing under light load. As a result, ringing cannot be suppressed sufficiently.

FIG. 11 is a diagram illustrating how conflicts occur in the on-timing control of the transistor 18 depending on the weight and weight of the load. In this figure, from the top, the switch voltage SW, the gate-source voltage VgsL of the synchronous rectifier transistor N2, the drain-source voltage VdsL, the drain-source current IdsL, and the on-resistance RonL (=VdsL/IdsL) are shown. Depicted.

Note that the drain-source voltage VdsL and the on-resistance RonL are depicted enlarged in the vertical axis direction. Furthermore, the left side of this figure shows the behavior under heavy load. On the other hand, the right side of the figure shows the behavior under light load.

Sections T11 (=times t54 to t56) and T21 (=times t64 to t66) each indicate sections in which the on-resistance RonL of the synchronous rectification transistor N2 is relatively high. That is, sections T11 and T21 correspond to the Ron loss sections mentioned above.

Sections T12 (=times t53 to t55) and T22 (=times t62 to t65) respectively indicate periods in which the transistor 17 is in the on state and the transistor 18 is in the off state (=NMOS drive period). ing.

Section T13 (=time t56 to t57) indicates an NMOS drive extension section during heavy load, which is set in consideration of the plateau region during light load. Section T23 (=time t63 to t64) indicates a plateau region during light load.

In periods T11 and T21, the gate-source voltage VgsL increases only to a voltage value (=VREG−Vth) obtained by subtracting the on-threshold voltage Vth of the transistor 18 from the internal power supply voltage VREG. Therefore, in sections T11 and T21, the synchronous rectifier transistor N2 is not fully turned on.

By the way, when the on-timing of the transistor 18 is fixedly set to match the optimum timing under light load, the on-timing of the transistor 18 is delayed from the optimum timing under heavy load when the load is heavy.

Referring to the figure, the on-timing of the transistor 18 is not the timing at which the interval T11 expires, but the timing at which the interval T13 corresponding to the plateau region at the time of light load has elapsed. That is, section T11 can be extended to section T11' (=time t54 to t57). As a result, Ron loss increases. In particular, as the switching frequency increases, the proportion of the period T11' in the low level period of the switch voltage SW increases. Therefore, Ron loss becomes more apparent.

<Drive circuit (fourth embodiment)>
FIG. 12 is a diagram showing a fourth embodiment of the drive circuit 10. In the drive circuit 10 of this embodiment, the controller 19 included in the lower driver DRVL initially turns the transistor 17 on during the on-transition period of the synchronous rectification transistor N2 (=the high-level transition period of the lower gate signal LG). The on-timing of the transistor 18 is controlled so that the transistor 18 is also turned on from the middle of the process.

Referring to the figure, the controller 19 includes a comparator CMP2 and a negative AND gate NAND2.

The comparator CMP2 generates a comparison signal by comparing the switch voltage SW input to the inverting input terminal (-) and a predetermined threshold voltage Vref (for example, VREG/2) input to the non-inverting input terminal (+). Generate S21. Therefore, the comparison signal S21 becomes a high level when the switch voltage SW is lower than the threshold voltage Vref, and becomes a low level when the switch voltage SW is higher than the threshold voltage Vref.

The NAND gate NAND2 (=corresponding to a logic gate) controls the transistor 18 according to the comparison signal S21 and the lower gate signal LG (=corresponding to the control signal of the synchronous rectifier transistor N2, which is the drive target of the lower driver DRVL). A NAND signal S22 is generated to turn on/off. The NAND signal S22 becomes a high level when at least one of the comparison signal S21 and the lower gate signal LG is at a low level, and becomes a low level when both the comparison signal S21 and the lower gate signal LG are at a high level. becomes.

In this manner, the controller 19 of this configuration example determines the on-timing of the transistor 18 according to the comparison result between the switch voltage SW appearing at one end (source) of the synchronous rectifier transistor N2 and the predetermined threshold voltage Vref.

Referring to this figure, the controller 19 turns on the transistor 18 when the switch voltage SW is lower than the threshold voltage Vref and the lower gate signal LG is at a high level (=logic level when turned on). state.

FIG. 13 is a diagram showing how conflicts depending on the weight and weight of the load are resolved in the on-timing control of the transistor 18. In this figure, as in FIG. 11 mentioned earlier, from the top, the switch voltage SW, the gate-source voltage VgsL of the synchronous rectifier transistor N2, the drain-source voltage VdsL, the drain-source current IdsL, and the on-resistance. RonL (=VdsL/IdsL) is depicted.

Note that the drain-source voltage VdsL and the on-resistance RonL are depicted enlarged in the vertical axis direction. Furthermore, the left side of this figure shows the behavior under heavy load. On the other hand, the right side of the figure shows the behavior under light load.

At times t5x and t6x newly depicted in this figure, it is detected that the switch voltage SW is lower than the threshold voltage Vref, and the lower gate signal LG is at a high level (=logic level when turned on). It shows the timing.

The on-timing of the transistor 18 is preferably set to the timing at which signal delay sections T14 and T24 of the NAND gate NAND2 and the pre-driver (not shown) following it elapse after the arrival of times t5x and t6x.

In the drive circuit 10 of this embodiment, the on-timing of the transistor 18 is variably set depending on the weight of the load. Therefore, there is no need to extend section T11 to section T11' when the load is heavy. Therefore, it is possible to reduce Ron loss and suppress ringing at the same time.

<Summary>
Below, the various embodiments described above will be described in general.

For example, the drive circuit disclosed in this specification includes a first transistor and a second transistor configured to be connected in parallel between a control terminal of a transistor to be driven and an application terminal of an on-voltage; The controller is configured to turn on the first transistor at the beginning of an on-transition period of the transistor to be driven and to turn on the second transistor halfway through (a first configuration). .

Note that in the drive circuit according to the first configuration, the first transistor is of a first channel type, and the second transistor is of a second channel type different from the first channel type (a second transistor). configuration).

Further, in the drive circuit according to the first or second configuration, the controller may be configured to turn on the second transistor after the plateau region of the transistor to be driven has expired (third configuration). .

In the drive circuit according to any one of the first to third configurations, the controller determines the on-timing of the second transistor according to a comparison result between a switch voltage appearing at one end of the driven transistor and a predetermined threshold voltage. A configuration (fourth configuration) may also be used.

Further, in the drive circuit according to the fourth configuration, the controller includes a comparator configured to compare the switch voltage and the threshold voltage to generate a comparison signal, and a comparator configured to generate a comparison signal by comparing the switch voltage and the threshold voltage, and a comparison signal between the comparison signal and the transistor to be driven. A configuration (fifth configuration) including a logic gate configured to turn on/off the second transistor according to a control signal may be adopted.

In the drive circuit according to the fifth configuration, the transistor to be driven is connected between an input voltage application terminal and a switch voltage application terminal, and the controller is configured such that the switch voltage is higher than the threshold voltage. A configuration (sixth configuration) may be adopted in which the second transistor is turned on when the control signal is high and the control signal is at the on-state logic level.

Further, in the drive circuit according to the fifth configuration, the transistor to be driven is connected between an application end of the switch voltage and an application end of the reference voltage, and the controller is configured such that the switch voltage is higher than the threshold voltage. A configuration (seventh configuration) may be adopted in which the second transistor is turned on when the control signal is at the on-state logic level.

In the drive circuit according to any one of the first to third configurations, the controller controls the on-timing of the second transistor according to a comparison result between the input voltage applied to one end of the driven transistor and the on-voltage. A configuration (eighth configuration) may also be used.

In the drive circuit according to the eighth configuration, the controller includes an N-channel transistor connected between the input voltage application terminal and the internal node, and an N-channel transistor connected between the on-voltage application terminal and the internal node. and a P-channel transistor connected between the transistors, and the on-voltage is applied to the control ends of each of the N-channel transistor and the P-channel transistor when the first transistor is in the on state, and The second transistor may be configured to be turned on/off depending on the node voltage appearing at the internal node (ninth configuration).

Further, in the drive circuit according to any one of the first to ninth configurations, the transistor to be driven may be a GaN device (a tenth configuration).

Further, in the drive circuit according to any one of the first to tenth configurations, the minimum on-time of the transistor to be driven may be less than 20 ns (an eleventh configuration).

Further, for example, the switching power supply disclosed in this specification has a configuration (twelfth configuration) including a drive circuit according to any one of the first to eleventh configurations.

<Other variations>
Note that the various technical features disclosed in this specification can be modified in addition to the above-described embodiments without departing from the gist of the technical creation. That is, the above embodiments should be considered to be illustrative in all respects and not restrictive. Further, the technical scope of the present disclosure is defined by the claims, and it should be understood that all changes within the meaning and range equivalent to the claims are included.

1 Switching power supply 10 Drive circuit 11, 17 First transistor (NMOSFET)
12, 18 Second transistor (PMOSFET)
13, 19 Controller 14, 1A 3rd transistor (NMOSFET)
15, 16 Diode C1 Capacitor CMP, CMP2 Comparator DRVH Upper driver DRVL Lower driver INV1, INV2, INV3, INV4 Inverter L1 Inductor N1 Output transistor (NMOSFET)
N2 Synchronous rectifier transistor (NMOSFET)
N11~N15 Transistor (NMOSFET)
NAND, NAND2 NAND gate P11 to P14 Transistor (PMOSFET)
R1, R2 resistance

Claims (12)

a first transistor and a second transistor configured to be connected in parallel between a control end of the driven transistor and an on-voltage application end;
a controller configured to turn on the first transistor at the beginning of an on-transition period of the transistor to be driven, and turn on the second transistor halfway;
A drive circuit comprising: The drive circuit according to claim 1, wherein the first transistor is a first channel type, and the second transistor is a second channel type different from the first channel type. The drive circuit according to claim 1, wherein the controller turns on the second transistor after a plateau region of the driven transistor expires. 2. The drive circuit according to claim 1, wherein the controller determines the on-timing of the second transistor according to a comparison result between a switch voltage appearing at one end of the driven transistor and a predetermined threshold voltage. The controller includes:
a comparator configured to compare the switch voltage and the threshold voltage to generate a comparison signal;
a logic gate configured to turn on/off the second transistor according to the comparison signal and the control signal of the driven transistor;
The drive circuit according to claim 4, comprising: The transistor to be driven is connected between an input voltage application terminal and a switch voltage application terminal, and the controller is configured to control a logic state when the switch voltage is higher than the threshold voltage and the control signal is on. 6. The drive circuit according to claim 5, wherein the second transistor is turned on when the second transistor is at a certain level. The transistor to be driven is connected between the application terminal of the switch voltage and the application terminal of the reference voltage, and the controller controls the logic when the switch voltage is lower than the threshold voltage and the control signal is on. 6. The drive circuit according to claim 5, wherein the second transistor is turned on when the second transistor is at a certain level. The drive circuit according to claim 1, wherein the controller determines the turn-on timing of the second transistor according to a comparison result between an input voltage applied to one end of the driven transistor and the turn-on voltage. The controller includes an N-channel transistor connected between the input voltage application terminal and an internal node, and a P-channel transistor connected between the on-voltage application terminal and the internal node. including,
The on-voltage is applied to the control terminals of each of the N-channel transistor and the P-channel transistor when the first transistor is in an on-state,
9. The drive circuit according to claim 8, wherein the second transistor is turned on/off depending on a node voltage appearing at the internal node. The drive circuit according to claim 1, wherein the transistor to be driven is a GaN device. The drive circuit according to claim 1, wherein the minimum on-time of the driven transistor is less than 20 ns. A switching power supply comprising the drive circuit according to any one of claims 1 to 11.

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