JP2024067299A - Semiconductor device ad manufacturing method thereof - Google Patents

Abstract

To provide a technique for improving a tolerance dose when an IGBT structure is turned off in a semiconductor device comprising a semiconductor substrate including an IGBT region and a diode region.SOLUTION: A semiconductor device 1 comprises: a plurality of first trench gates 50 positioned in an IGBT region 20A; a plurality of first dummy trenches 60 positioned in a diode region 20B; and a plurality of second dummy trenches 70 positioned in a boundary 20C between the IGBT region and the diode region. The plurality of second dummy trenches is disposed while being spaced apart from each other in a direction of connecting the IGBT region with the diode region. The plurality of second dummy trenches includes a deep portion 76, which is formed deeper than the plurality of trench gates and the plurality of first dummy trenches, at least in a part thereof.SELECTED DRAWING: Figure 2

Description

The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

Patent Document 1 discloses a semiconductor device having a semiconductor substrate including an IGBT (insulated gate bipolar transistor) region and a diode region. In this semiconductor device, an upper electrode is provided to cover the upper surface of the semiconductor substrate, and a lower electrode is provided to cover the lower surface of the semiconductor substrate. In the IGBT region, an IGBT structure is provided such that the upper electrode serves as an emitter electrode and the lower electrode serves as a collector electrode. In the diode region, a diode structure is provided such that the upper electrode serves as an anode electrode and the lower electrode serves as a cathode electrode. The diode structure is connected in inverse parallel to the IGBT structure, and can operate as a freewheeling diode.

In addition, in the semiconductor device of Patent Document 1, multiple trench gates are provided in the IGBT region, and multiple dummy trenches are provided in the diode region. Furthermore, in the semiconductor device of Patent Document 1, a single boundary trench is provided at the boundary between the IGBT region and the diode region, which is formed to be deeper than the multiple trench gates and the multiple dummy trenches. The boundary trench is provided to suppress the inflow of carriers from the IGBT region toward the diode region. As a result, it is said that the semiconductor device of Patent Document 1 has an increased tolerance during recovery operation of the diode structure.

JP 2021-190657 A

This type of semiconductor device also requires technology to improve the tolerance when the IGBT structure is turned off. This specification provides technology to improve the tolerance when the IGBT structure is turned off.

The semiconductor device disclosed in this specification may include a semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B), a lower electrode (44) provided on the lower surface (10b) of the semiconductor substrate, an upper electrode (42) provided on the upper surface (10a) of the semiconductor substrate, a plurality of trench gates (50) extending from the upper surface of the semiconductor substrate located in the IGBT region toward a deeper portion, a plurality of first dummy trenches (60) extending from the upper surface of the semiconductor substrate located in the diode region toward a deeper portion, and a plurality of second dummy trenches (70) extending from the upper surface of the semiconductor substrate toward a deeper portion at a boundary (20C) between the IGBT region and the diode region. Each of the plurality of second dummy trenches may be arranged at intervals from one another along a direction connecting the IGBT region and the diode region. Each of the second dummy trenches may have, at least in part, a deep portion (76) formed deeper than the trench gates and the first dummy trenches. With this semiconductor device, when the IGBT structure is turned off, avalanche occurs preferentially at the bottom of the second dummy trench because at least a portion of the second dummy trench is formed deep, and the occurrence of avalanche at the bottom of the trench gate can be suppressed. As a result, the semiconductor device has improved tolerance when the IGBT structure is turned off.

This specification may also disclose a method for manufacturing the semiconductor device. This manufacturing method may include a trench forming step of forming a plurality of trenches extending from the upper surface of the semiconductor substrate toward a deep portion thereof, in which the trench width of at least a portion of the trenches corresponding to the plurality of second dummy trenches is greater than the trench width of the trenches corresponding to the plurality of trench gates and the plurality of first dummy trenches. According to this manufacturing method, the trenches corresponding to the plurality of trench gates, the plurality of first dummy trenches, and the plurality of second dummy trenches can be formed simultaneously.

FIG. 2 is a diagram illustrating a planar layout of an IGBT region and a diode region of the semiconductor device. 2 is a cross-sectional view of a main portion showing features of one embodiment of a semiconductor device, and is a schematic cross-sectional view of a main portion corresponding to line II-II in FIG. FIG. 1 is a diagram for explaining one method for realizing one embodiment of a semiconductor device, and is a diagram that typically shows a perspective view of a main part of a semiconductor device with an upper electrode removed. FIG. 1 is a diagram for explaining one method for realizing one embodiment of a semiconductor device, and is a diagram that typically shows a perspective view of a main part of a semiconductor device with an upper electrode removed. FIG. 1 is a diagram for explaining one method for realizing one embodiment of a semiconductor device, and is a diagram that typically shows a perspective view of a main part of a semiconductor device with an upper electrode removed. 2 is a cross-sectional view of a main portion showing features of another embodiment of a semiconductor device, the cross-sectional view corresponding to line II-II in FIG. 1. FIG. 2 is a cross-sectional view of a main portion showing features of another embodiment of a semiconductor device, the cross-sectional view corresponding to line II-II in FIG. 1. FIG. 2 is a cross-sectional view of a main portion showing features of another embodiment of a semiconductor device, the cross-sectional view corresponding to line II-II in FIG. 1. FIG.

Each embodiment will be described below with reference to the drawings. Components common to each embodiment will be given the same reference numerals, and their description will be omitted. Also, for the purpose of clarity of illustration, only some of the components that are repeatedly arranged may be given the same reference numerals.

As shown in FIG. 1, the semiconductor device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 is not particularly limited, and may be, for example, a silicon carbide (SiC) substrate. In the following, the thickness direction of the semiconductor substrate 10 is referred to as the z direction, a direction parallel to the upper surface of the semiconductor substrate 10 is referred to as the x direction, and a direction parallel to the upper surface of the semiconductor substrate 10 and perpendicular to the x direction is referred to as the y direction.

As shown in FIG. 1, the semiconductor substrate 10 may have, for example, two element regions 20 and a termination region 30 arranged around the element regions 20, although this is not particularly limited. Each element region 20 is partitioned into an IGBT region 20A and a diode region 20B. A structure for forming an IGBT is provided in the IGBT region 20A, and a structure for forming a diode is provided in the diode region 20B. In each element region 20, the IGBT region 20A and the diode region 20B are alternately arranged along the y direction. Hereinafter, the direction connecting the IGBT region 20A and the diode region 20B, in which the IGBT region 20A and the diode region 20B are alternately arranged, is also referred to as the IGBT-diode direction.

2, the semiconductor device 1 includes an upper electrode 42, a lower electrode 44, a plurality of trench gates 50 provided in the IGBT region 20A, a plurality of first dummy trenches 60 provided in the diode region 20B, and a plurality of second dummy trenches 70 provided in the boundary portion 20C. The upper electrode 42 is provided to cover the upper surface 10a of the semiconductor substrate 10. The lower electrode 44 is provided to cover the lower surface 10b of the semiconductor substrate 10. In this manner, the semiconductor device 1 is configured as a vertical device. The upper electrode 42 functions as an emitter electrode of the IGBT structure and also functions as an anode electrode of the diode structure. The lower electrode 44 functions as a collector electrode of the IGBT structure and also functions as a cathode electrode of the diode structure.

The semiconductor substrate 10 of the semiconductor device 1 has a p ⁺ type collector region 11, an n ⁺ type cathode region 12, an n-type region 13, a p-type region 14, an n ⁺ type emitter region 15, and a p ⁺ type contact region 16.

The collector region 11 is provided in the IGBT region 20A of the semiconductor substrate 10 and is located at a position exposed to the lower surface 10b of the semiconductor substrate 10. The collector region 11 is in ohmic contact with the lower electrode 44. The cathode region 12 is provided in the diode region 20B of the semiconductor substrate 10 and is located at a position exposed to the lower surface 10b of the semiconductor substrate 10. The cathode region 12 is in ohmic contact with the lower electrode 44. In this way, the collector region 11 is provided over the entire IGBT region 20A at a position exposed to the lower surface 10b of the semiconductor substrate 10, and the cathode region 12 is provided over the entire diode region 20B. In other words, the semiconductor substrate 10 is partitioned such that the range where the collector region 11 is provided is the IGBT region 20A, and the range where the cathode region 12 is provided is the diode region 20B.

The n-type region 13 is provided in both the IGBT region 20A and the diode region 20B. In the IGBT region 20A, the n-type region 13 is disposed between the collector region 11 and the p-type region 14, and functions as the drift region of the IGBT structure. In the diode region 20B, the n-type region 13 is disposed between the cathode region 12 and the p-type region 14, and functions as the low concentration region of the diode structure.

The p-type region 14 is provided in both the IGBT region 20A and the diode region 20B. In the IGBT region 20A, the p-type region 14 is disposed on the n-type region 13, and functions as the body region of the IGBT structure. In the diode region 20B, the p-type region 14 is disposed on the n-type region 13, and functions as the anode region of the diode structure.

The emitter regions 15 are provided in the IGBT region 20A and are distributed in positions exposed on the upper surface 10a of the semiconductor substrate 10. The emitter regions 15 are in ohmic contact with the upper electrode 42. The emitter regions 15 are in contact with the side surface of the trench gate 50 and are separated from the n-type region 13 by the p-type region 14. The portion of the p-type region 14 separating the n-type region 13 and the emitter regions 15 that is in contact with the side surface of the trench gate 50 functions as a channel.

The contact regions 16 are provided in both the IGBT region 20A and the diode region 20B, and are distributed at positions exposed on the upper surface 10a of the semiconductor substrate 10. The contact regions 16 are in ohmic contact with the upper electrode 42. The p-type region 14 is electrically connected to the upper electrode 42 via the contact regions 16.

The trench gates 50 are provided in the upper layer of the semiconductor substrate 10 located in the IGBT region 20A. When the semiconductor substrate 10 is viewed in plan, each of the trench gates 50 extends in the x direction and is arranged at intervals in the y direction. Thus, the trench gates 50 are arranged in a stripe pattern. Each of the trench gates 50 is formed so as to extend from the upper surface 10a of the semiconductor substrate 10 through the p-type region 14 to the n-type region 13. Each of the trench gates 50 includes a gate insulating film 52 and a gate electrode 54 insulated from the semiconductor substrate 10 by the gate insulating film 52. The gate electrode 54 of each of the trench gates 50 is insulated from the upper electrode 42 by an interlayer insulating film.

The first dummy trenches 60 are provided in the upper layer of the semiconductor substrate 10 located in the diode region 20B. When the semiconductor substrate 10 is viewed in a plan view, each of the first dummy trenches 60 extends in the x direction and is arranged at intervals in the y direction. In this manner, the first dummy trenches 60 are arranged in a stripe pattern. Each of the first dummy trenches 60 is formed so as to extend from the upper surface 10a of the semiconductor substrate 10 through the p-type region 14 to the n-type region 13. Each of the first dummy trenches 60 includes a dummy insulating film 62 and a dummy electrode 64 insulated from the semiconductor substrate 10 by the dummy insulating film 62. The dummy electrode 64 of each of the first dummy trenches 60 is electrically connected to the upper electrode 42.

The second dummy trenches 70 are provided in the upper layer of the semiconductor substrate 10 located at the boundary 20C between the IGBT region 20A and the diode region 20B. Here, the boundary 20C is defined as a range extending a predetermined distance from the boundary between the IGBT region 20A and the diode region 20B (i.e., the boundary between the collector region 11 and the cathode region 12) toward each of the IGBT region 20A and the diode region 20B along the IGBT-diode direction (the y direction in this example). The predetermined distance is 1/2 the film thickness of the n-type region 13 measured along the thickness direction of the semiconductor substrate 10. Therefore, the width of the boundary 20C measured along the IGBT-diode direction is equal to the film thickness of the n-type region 13. The second dummy trenches 70 may be arranged in at least a part of the boundary 20C. In this example, multiple second dummy trenches 70 are arranged in both the IGBT region 20A and the diode region 20B of the boundary portion 20C.

When the semiconductor substrate 10 is viewed in a plan view, each of the second dummy trenches 70 extends in the x direction and is arranged at intervals in the y direction. In this manner, the second dummy trenches 70 are arranged in a stripe pattern. Each of the second dummy trenches 70 is formed so as to extend from the upper surface 10a of the semiconductor substrate 10 through the p-type region 14 to the n-type region 13. Each of the second dummy trenches 70 includes a dummy insulating film 72 and a dummy electrode 74 insulated from the semiconductor substrate 10 by the dummy insulating film 72. The dummy electrode 74 of each of the second dummy trenches 70 is electrically connected to the upper electrode 42.

At least a portion of each of the second dummy trenches 70 has a deep portion 76 formed deeper than the trench gates 50 and the first dummy trenches 60. As described below, each of the second dummy trenches 70 may be entirely configured deeper than the trench gates 50 and the first dummy trenches 60, or at least a portion of each of the second dummy trenches 70 may be deeper than the trench gates 50 and the first dummy trenches 60. In an example in which the second dummy trench 70 is entirely configured deeper than the trench gates 50 and the first dummy trenches 60, it can be said that the second dummy trench 70 is entirely configured with a deep portion 76.

The second dummy trenches 70 may be formed in a separate process from the trench gates 50 and the first dummy trenches 60. However, by forming the second dummy trenches 70 in the same process as the trench gates 50 and the first dummy trenches 60, the manufacturing costs can be reduced. With reference to Figures 3 to 5, the second dummy trenches 70 having a shape suitable for reducing manufacturing costs will be described.

3, the overall trench width 70W of the second dummy trench 70 is larger than the trench width 50W of the trench gate 50. The trench width of the first dummy trench 60 is the same as the trench width 50W of the trench gate 50. Therefore, the trench width 70W of the second dummy trench 70 is larger than the trench width of the first dummy trench 60. Here, the trench width refers to the width in the short direction of the trench (the y direction in this example).

When forming a trench in the semiconductor substrate 10, the etching gas easily enters the trench in a trench with a large trench width, and the etching rate increases. Therefore, if multiple trenches with different trench widths are formed by one etching using a single photomask, trenches with different depths can be created. Therefore, the manufacturing method of the semiconductor device 1 of the example shown in FIG. 3 includes a trench formation process including a step of forming a photomask on the semiconductor substrate 10 and a step of forming multiple trenches in the upper layer of the semiconductor substrate 10 exposed from the openings of the photomask by dry etching. The photomask is patterned so that the trench width of the trench corresponding to the multiple second dummy trenches 70 is larger than the trench width of the trench corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60. As a result, the depth of the trench corresponding to the multiple second dummy trenches 70 can be made larger than the depth of the trench corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60 by one etching using a single photomask.

In the example of FIG. 3, each of the second dummy trenches 70 is formed so that the trench width at any position in the longitudinal direction is larger than the trench width of each of the trench gates 50 and the first dummy trenches 60. As a result, each of the second dummy trenches 70 is configured to be deeper than the trench gates 50 and the first dummy trenches 60. Instead of this example, in the example shown in FIG. 4, each of the second dummy trenches 70 is formed so that the trench width at a portion of the longitudinal direction is larger than the trench width of each of the trench gates 50 and the first dummy trenches 60. As a result, each of the second dummy trenches 70 is configured so that a portion corresponding to a portion of the longitudinal direction is deeper than the trench gates 50 and the first dummy trenches 60. In the example of FIG. 4, a deep portion 76 is formed in a portion of each of the second dummy trenches 70, and the deep portions 76 are distributed and arranged within the boundary portion 20C. In the example of FIG. 4, the depth of the trench corresponding to the deep portion 76 can be made greater than the depth of the trenches corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60 by a single etching using a single photomask.

In the example of FIG. 5, a plurality of linking dummy trenches 80 are provided between the second dummy trenches 70 adjacent to each other in the IGBT/diode direction. When the semiconductor substrate 10 is viewed in plan, each of the linking dummy trenches 80 extends in the y direction and is arranged at intervals in the x direction. Each of the linking dummy trenches 80 is formed so as to extend from the upper surface of the semiconductor substrate 10 through the p-type region 14 to reach the n-type region 13. Each of the linking dummy trenches 80 includes a dummy insulating film 82 and a dummy electrode 84 insulated from the semiconductor substrate 10 by the dummy insulating film 82. The dummy electrode 84 of each of the linking dummy trenches 80 is electrically connected to the upper electrode 42.

Each of the multiple linking dummy trenches 80 is connected to the adjacent second dummy trenches 70 at both ends. Deep portions 76 are formed at the portions where the linking dummy trenches 80 are connected to the second dummy trenches 70, and the deep portions 76 are distributed and arranged within the boundary portion 20C. In the example of FIG. 5, trenches corresponding to the multiple trench gates 50, the multiple first dummy trenches 60, the multiple second dummy trenches 70, and the multiple linking dummy trenches 80 are simultaneously formed by one etching using a single photomask. In the portion where the linking dummy trench 80 is connected to the second dummy trench 70, the effective trench width of the trench is large. Therefore, in the example of FIG. 5, the depth of the trench corresponding to the deep portion 76 can be made larger than the depth of the trench corresponding to the multiple trench gates 50 and the multiple first dummy trenches 60 by one etching using a single photomask.

Next, the operation of the semiconductor device 1 will be described. In the mode in which the IGBT structure operates, a voltage is applied between the lower electrode 44 and the upper electrode 42 so that the lower electrode 44 has a higher potential than the upper electrode 42. In this mode in which the IGBT structure operates, when the voltage between the gate electrode 54 and the upper electrode 42 becomes higher than the threshold voltage, a channel is formed in the p-type region 14 that contacts the side of the trench gate 50, and electron carriers are injected from the emitter region 15 to the n-type region 13 through the channel. Meanwhile, hole carriers are injected from the collector region 11 to the n-type region 13. This turns the IGBT structure on. When the voltage between the gate electrode 54 and the upper electrode 42 becomes smaller than the threshold voltage, the channel on the side of the trench gate 50 disappears, and the IGBT structure in the IGBT region 20A turns off. Thus, in the mode in which the IGBT structure operates, the on and off of the IGBT structure is controlled according to the potential of the gate electrode 54 of the trench gate 50.

In the mode in which the diode structure operates, a voltage is applied between the lower electrode 44 and the upper electrode 42 so that the upper electrode 42 is at a higher potential than the lower electrode 44. In this mode in which the diode structure operates, the gate electrode 54 is set to the potential of the upper electrode 42, and the channel on the side of the trench gate 50 disappears. In the mode in which the diode structure operates, the upper electrode 42 is at a higher potential than the lower electrode 44, so a return current flows through the pn diode composed of the p-type region 14, n-type region 13, and cathode region 12.

In the above-mentioned mode in which the IGBT structure operates, when the IGBT structure is turned off, the hole carriers remaining in the n-type region 13 become high energy due to the high voltage of the inductive load, and an avalanche may occur in the process of the hole carriers being discharged to the upper electrode 42. In the semiconductor device 1, since at least a part of the second dummy trench 70 is formed deep, avalanche occurs preferentially at the bottom of the second dummy trench 70, and the occurrence of avalanche at the bottom of the trench gate 50 can be suppressed. In particular, in the semiconductor device 1, a plurality of second dummy trenches are arranged at intervals along the IGBT-diode direction at the boundary portion 20C. Therefore, in the semiconductor device 1, the second dummy trench 70 is reliably arranged in the path through which the hole carriers remaining near the boundary between the IGBT region 20A and the diode region 20B are discharged. As a result, in the semiconductor device 1, avalanche can be preferentially generated at the boundary portion 20C, and the occurrence of avalanche at the bottom of the trench gate 50 can be suppressed. As a result, destruction of the trench gate 50 due to avalanche is suppressed, and the semiconductor device 1 has improved tolerance when the IGBT structure is turned off.

Other embodiments of the semiconductor device will be described below. These embodiments of the semiconductor device can also have the same effects as the semiconductor device 1 described above.

In the semiconductor device 2 of FIG. 6, the second dummy trenches 70 are unevenly arranged in the IGBT region 20A of the boundary portion 20C, and the first dummy trenches 60 are provided in the diode region 20B of the boundary portion 20C.

In the semiconductor device 3 of FIG. 7, the second dummy trenches 70 are unevenly arranged in the diode region 20B of the boundary portion 20C, and the trench gate 50 is provided in the IGBT region 20A of the boundary portion 20C.

As shown in the examples of Figures 6 and 7, it is not necessary that only the second dummy trench 70 is provided in the boundary portion 20C, and the trench gate 50 and the first dummy trench 60 may be provided in the boundary portion 20C as necessary. If multiple second dummy trenches 70 are provided in at least a portion of the boundary portion 20C, the same effect as the semiconductor device 1 described above can be obtained.

The second dummy trenches 70 may be disposed between the trench gate 50 and the first dummy trench 60, or may not be disposed between the trench gate 50 and the first dummy trench 60. For example, as shown in FIG. 8, the first dummy trench 60 may be provided in the IGBT region 20A adjacent to the boundary portion 20C.

The following summarizes the characteristics of the technology disclosed in this specification. Note that the technical elements described below are independent technical elements that demonstrate technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.

(Feature 1)
A semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B);
a lower electrode (44) provided on the lower surface (10b) of the semiconductor substrate;
an upper electrode (42) provided on an upper surface (10a) of the semiconductor substrate;
A plurality of trench gates (50) extending from the upper surface of the semiconductor substrate toward a deep portion thereof located in the IGBT region;
A plurality of first dummy trenches (60) extending from the top surface of the semiconductor substrate toward a deep portion thereof located in the diode region;
a plurality of second dummy trenches (70) extending from the top surface of the semiconductor substrate toward a deep portion thereof at a boundary (20C) between the IGBT region and the diode region,
The second dummy trenches are arranged at intervals along a direction connecting the IGBT region and the diode region,
Each of the second dummy trenches has, at least in a portion thereof, a deep portion (76) formed deeper than the trench gates and the first dummy trenches.

(Feature 2)
2. The semiconductor device according to claim 1, wherein the second dummy trenches are provided between the trench gates and the first dummy trenches.

(Feature 3)
Some of the second dummy trenches among the plurality of second dummy trenches are disposed in the IGBT region of the boundary portion,
3. The semiconductor device according to feature 1 or 2, wherein another of the plurality of second dummy trenches is disposed in the diode region of the boundary portion.

(Feature 4)
The semiconductor device according to any one of features 1 to 3, wherein each of the second dummy trenches is configured to be deeper than the trench gates and the first dummy trenches as a whole.

(Feature 5)
4. The semiconductor device according to any one of features 1 to 3, wherein each of the second dummy trenches is configured so that a portion thereof is deeper than the trench gates and the first dummy trenches.

(Feature 6)
6. The semiconductor device according to claim 1, wherein the deep portion of each of the second dummy trenches has a trench width wider than a trench width of the trench gates and the first dummy trenches.

(Feature 7)
Further comprising a connecting dummy trench (80) extending between adjacent second dummy trenches,
6. The semiconductor device according to feature 5, wherein the deep portion of each of the plurality of second dummy trenches is located in a portion that is connected to the connecting dummy trench.

Although the embodiments have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the specific examples given above. The technical elements described in this specification or drawings demonstrate technical utility either alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology exemplified in this specification or drawings achieves multiple objectives simultaneously, and achieving one of these objectives is itself technically useful.

Reference Signs List 1, 2, 3: semiconductor device, 10: semiconductor substrate, 20A: IGBT region, 20B: diode region, 20C: boundary portion, 50: trench gate, 60: first dummy trench, 70: second dummy trench, 80: connecting dummy trench

Claims (8)

A semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B);
a lower electrode (44) provided on the lower surface (10b) of the semiconductor substrate;
an upper electrode (42) provided on an upper surface (10a) of the semiconductor substrate;
A plurality of trench gates (50) extending from the upper surface of the semiconductor substrate toward a deep portion thereof located in the IGBT region;
A plurality of first dummy trenches (60) extending from the top surface of the semiconductor substrate toward a deep portion thereof located in the diode region;
a plurality of second dummy trenches (70) extending from the top surface of the semiconductor substrate toward a depth thereof at a boundary (20C) between the IGBT region and the diode region,
The second dummy trenches are arranged at intervals along a direction connecting the IGBT region and the diode region,
Each of the second dummy trenches has, at least in a portion thereof, a deep portion (76) formed deeper than the trench gates and the first dummy trenches. The semiconductor device according to claim 1, wherein the second dummy trenches are provided between the trench gates and the first dummy trenches. Some of the second dummy trenches among the plurality of second dummy trenches are disposed in the IGBT region of the boundary portion,
The semiconductor device according to claim 1 , wherein other of the plurality of second dummy trenches are disposed in the diode region of the boundary portion. The semiconductor device according to claim 1, wherein each of the second dummy trenches is configured to be deeper than the trench gates and the first dummy trenches. The semiconductor device according to claim 1, wherein each of the second dummy trenches is configured so that a portion of the second dummy trench is deeper than the trench gates and the first dummy trenches. The semiconductor device according to any one of claims 1 to 5, wherein the deep portion of each of the second dummy trenches has a trench width wider than the trench widths of the trench gates and the first dummy trenches. Further comprising a connecting dummy trench (80) extending between adjacent second dummy trenches,
The semiconductor device according to claim 5 , wherein the deep portion of each of the plurality of second dummy trenches is located at a portion connected to the coupling dummy trench. A semiconductor substrate (10) including an IGBT region (20A) and a diode region (20B);
a lower electrode (44) provided on the lower surface (10b) of the semiconductor substrate;
an upper electrode (42) provided on an upper surface (10a) of the semiconductor substrate;
A plurality of trench gates (50) extending from the upper surface of the semiconductor substrate toward a deep portion thereof located in the IGBT region;
A plurality of first dummy trenches (60) extending from the top surface of the semiconductor substrate toward a deep portion thereof located in the diode region;
a plurality of second dummy trenches (70) extending from the top surface of the semiconductor substrate toward a deep portion thereof at a boundary (20C) between the IGBT region and the diode region,
The second dummy trenches are arranged at intervals along a direction connecting the IGBT region and the diode region,
A method for manufacturing a semiconductor device, wherein each of the plurality of second dummy trenches has, at least in a portion thereof, a deep portion (76) formed deeper than the plurality of trench gates and the plurality of first dummy trenches,
a trench formation process for forming a plurality of trenches extending from the top surface of the semiconductor substrate toward a depth thereof, wherein a trench width of at least a portion of the trenches corresponding to the plurality of second dummy trenches is larger than a trench width of the trenches corresponding to the plurality of trench gates and the plurality of first dummy trenches.

Images