JP2023170314A - Data processing method and data processing device - Google Patents

Abstract

To provide a data processing technology for new data compression.SOLUTION: A data processing method includes a step a) of dividing first data of m*n bit length into m divided blocks of n bit length, a step b) of determining a valid block to be stored from among the divided blocks, and a step c) of storing a valid block. In the step b), the uppermost divided block whose numerical value is non-zero and the divided blocks lower than the uppermost divided block whose numerical value is non-zero are defined as valid blocks. As a result, data in which the upper digits are successively zero can be efficiently compressed and stored.SELECTED DRAWING: Figure 2

Description

The present invention relates to a data processing method and data processing apparatus for compressing data.

Conventionally, data sensing has been performed in many industrial devices for various purposes such as device control, monitoring, and failure prediction. In recent years, there has been a demand for diversification of processing within sensing devices, higher performance, lower power consumption, etc., and an increasing number of sensing devices are equipped with reconfigurable FPGA (Filed Programmable Gate Array) devices.

When storing sensing data inside a sensing device, it is difficult to secure a large memory capacity to store the sensing data internally. Furthermore, in order to increase the capacity of sensing data, there is an increasing need to reduce memory capacity through compression processing.

A conventional sensing data compression method using an FPGA is described in, for example, Patent Document 1. Patent Document 1 discloses a data compression method using a run-length compression method.

Special table 2018-534811 publication

The so-called run-length compression method has a problem in that while the compression rate is high for data where the same value is likely to continue, the compression rate decreases when the data matching rate is low.

The present invention was made in view of the above circumstances, and an object of the present invention is to provide a new data processing technique for data compression.

In order to solve the above problems, the first invention of the present application is a data processing method comprising: a) dividing first data of m*n bit length into m divided blocks of n bit length; ) determining a valid block to be stored among the divided blocks; c) storing the valid block; The block and the divided blocks lower than the highest divided block whose numerical values are non-zero are defined as the valid blocks.

A second invention of the present application is the data processing method of the first invention, wherein in step b), one enable signal including an enable bit of m-bit length is generated for one piece of the first data; When the p-th divided block from the lowest order is not the valid block, the p-th digit from the lowest order of the enable bit is set to 0, and when the p-th divided block from the lowest order is the valid block, sets the p-th digit from the lowest order of the enable bit to 1.

A third invention of the present application is the data processing method according to the first invention or the second invention, wherein the step c) includes c1) adding a 1-bit long discrimination bit to each of the valid blocks, and c2) The method includes the step of storing the discrimination bit together with second data having a length of n bits and having the same numerical value as the valid block.

A fourth invention of the present application is the data processing method of the third invention, in which in the step c1), when there is one valid block for one piece of the first data, the data processing method corresponds to the valid block. The discrimination bit is set to 1, and when there is a plurality of valid blocks for one said first data, the discrimination bit for the lowest valid block is set to 1, and the discrimination bit for the other valid blocks is set to 0. In the step c2),
The determination bits and the second data for one piece of the first data are stored in order from the most significant side.

A fifth invention of the present application is the data processing method according to the fourth invention, which includes, after the step c), d) preparing new m*n bit length zero data as new read data; and e. ) reading out the stored discrimination bit and the second data; and f) setting n bits from the least significant side of the read data as a numerical value of the second data read in the step e). and if the discrimination bit read in the step e) is 0, then after the step f), a step of g) shifting all non-zero bits of the read data to the upper n bits is performed. After that, return to step e) again, and if the discrimination bit read in step e) is 1, perform h) outputting the read data as third data after step f). .

A sixth invention of the present application is the data processing method according to any one of the first to fifth inventions, wherein p) time series data is processed before the steps a), b) and c). The method further includes the steps of: acquiring certain original data; and q) calculating the first data that is a difference between the latest original data and the original data at the previous time.

A seventh invention of the present application is the data processing method of the fifth invention, which includes, before the step a), the step b), and the step c), p) acquiring original data that is time series data; q) further comprising the step of calculating the first data that is the difference between the latest original data and the original data at the previous time, and after the step h), r) the outputted Adding the third data to the fourth data at the previous time to calculate new fourth data.

An eighth invention of the present application is a data processing device that stores data in a storage section provided externally or internally, and divides first data of m*n bit length into m divided blocks of n bit length. and a division processing unit that determines valid blocks to be stored among the divided blocks, and a storage processing unit that sequentially stores the valid blocks in the storage unit, and the division processing unit includes: The uppermost divided block whose numerical value is non-zero and the lower divided blocks than the uppermost divided block whose numerical value is non-zero are defined as the valid blocks.

A ninth invention of the present application is the data processing device according to the eighth invention, wherein the division processing unit generates one enable signal including an m-bit length enable bit for one piece of the first data, When the p-th divided block from the lowest order is not the valid block, the p-th digit from the lowest order of the enable bit is set to 0, and when the p-th divided block from the lowest order is the valid block, sets the p-th digit from the lowest order of the enable bit to 1.

A tenth invention of the present application is the data processing device according to the eighth invention, wherein the storage processing unit assigns a 1-bit long discrimination bit to each of the valid blocks, and the discrimination bit for one of the first data. and n-bit length second data having the same numerical value as the valid block are stored in the storage unit in order from the most significant side, and the storage processing unit stores the valid block for one piece of the first data. If there is one block, the determination bit corresponding to the valid block is set to 1; if there is a plurality of valid blocks for one first data, the determination bit for the lowest valid block. is set to 1, and the discrimination bits for the other valid blocks are set to 0.

An eleventh invention of the present application is the data processing device according to the tenth invention, in which decompression processing reads the discrimination bit and the second data from the storage unit and generates third data by restoring the first data. S) preparing new m*n-bit length zero data as new read data; and T) processing the determination bits stored in the storage unit and the A step of reading out the second data, and a step of U) converting the n bits from the least significant side of the read data into the numerical value of the second data read in the step T), and If the determination bit is 0, after the step U), perform the step of V) shifting all non-zero bits of the read data to the upper n bits, and then return to the step T) again. , when the determination bit read in step T) is 0, step W) of outputting the read data is performed after step U).

A twelfth invention of the present application is the data processing device according to any one of the eighth invention to the eleventh invention, which comprises: original data of m*n bit length that is time series data; and the original data at the previous time. It further includes a difference calculation processing unit that calculates the first data that is a difference between the data and the first data.

A thirteenth invention of the present application is the data processing device according to the eleventh invention, wherein the first data processing apparatus is a difference between original data of m*n bit length which is time series data and the original data at the previous time. further comprising: a difference calculation processing unit that calculates data; and an addition processing unit that calculates fourth data obtained by restoring the original data based on the third data output from the decompression processing unit; The addition processing unit calculates new fourth data by adding the fourth data at the previous time and the new third data.

According to the first to thirteenth inventions of the present application, it is possible to efficiently compress and store data whose upper digits are successively zero.

In particular, according to the third, fourth, and tenth inventions of the present application, the division of second data with respect to one piece of first data becomes clear.

In particular, according to the sixth, seventh, twelfth, and thirteenth inventions of the present application, when the data to be compressed is time series data, compression is performed by taking the difference from the previous time. Increased efficiency. That is, the number of second data to be stored can be reduced.

FIG. 1 is a diagram showing the configuration of a data processing device according to a first embodiment. 3 is a flowchart showing the flow of data compression processing according to the first embodiment. FIG. 3 is a diagram showing an example of data at each stage of data compression processing according to the first embodiment. FIG. 7 is a diagram showing a specific example of data at each stage in the data compression process according to the first embodiment. 7 is a flowchart showing the flow of data decompression processing according to the first embodiment. FIG. 3 is a diagram showing an example of stored data and data at each stage of data expansion processing according to the first embodiment. FIG. 2 is a diagram showing the configuration of a data processing device according to a second embodiment. 7 is a flowchart showing the flow of data compression processing according to the second embodiment. FIG. 7 is a diagram showing an example of data at each stage of data compression processing according to the second embodiment. FIG. 7 is a diagram showing a specific example of data at each stage in data compression processing according to the second embodiment. FIG. 7 is a diagram showing a specific example of data at each stage in data compression processing according to the second embodiment. 7 is a flowchart showing the flow of data decompression processing according to the second embodiment. FIG. 7 is a diagram showing an example of stored data and data at each stage of data decompression processing according to the second embodiment.

Embodiments of the present invention will be described below with reference to the drawings.

<1. First embodiment>
<1-1. Configuration of data processing device>
FIG. 1 is a diagram showing the configuration of a data processing device 1 according to an embodiment of the present invention. This data processing device 1 is a device that compresses and stores sensing data input from a sensor 90. The data processing device 1 is realized, for example, by an FPGA (Filed Programmable Gate Array) mounted on a sensing device including the sensor 90.

The data processing device 1 can store the sensing data Di input from the sensor 90 as compressed data in the storage processing unit 15, which will be described later. In this embodiment, the sensing data Di is analog data. Note that the sensing data Di may be digital data. Further, the data processing device 1 can decompress the compressed data stored in the storage processing unit 15 and output it as output data Do. Note that the output data Do may be digital data or analog data.

As shown in FIG. 1, the data processing device 1 includes a receiving section 11, a division processing section 13, a storage processing section 15, an expansion processing section 17, a transmission section 19, and a storage section 20. In this embodiment, the storage unit 20 is a built-in RAM of an FPGA that constitutes the data processing device 1. However, the storage unit 20 may be a memory such as a RAM connected to the outside of the data processing device 1.

The receiving unit 11 receives sensing data Di input from the sensor 90, converts it into digital data of m×n bit length, and sets the digital data as first data D1. Specifically, the receiving unit 11 can interpret protocols such as I2C and SPI. Therefore, the sensing data Di input using these protocols is interpreted and converted into first data D1 which is digital data. The receiving unit 11 then delivers the first data D1 to the division processing unit 13.

The division processing unit 13 divides the first data D1 into a plurality of m division blocks Dv each having a length of n bits. Here, each of the plurality of divided blocks Dv is a first divided block Dv. 1. Second divided block Dv. 2,..., m-th divided block Dv. It is called m. Note that m*n, n, 1, etc. written in parentheses after each data in FIG. 1 represent the number of bits of the data.

The division processing unit 13 divides m divided blocks Dv. 1~Dv. It is determined which data among m is a valid block that should be stored in the storage processing unit 15 or an ineffective block that should not be stored. Then, the division processing unit 13 generates one enable signal De including an m-bit length enable bit for one piece of first data D1. Note that the enable signal De may have a bit length that includes all enable bits, may be m bits long, or may have a bit length longer than m bits. The division processing unit 13 processes each division block Dv. 1~Dv. m and the enable signal De are delivered to the storage processing section 15.

Specifically, the division processing unit 13 divides the division blocks Dv. 1~Dv. Starting from the highest value of m, it is determined whether the numerical value is zero or non-zero. Then, the uppermost divided block Dv. Starting from m, divided blocks Dv whose numerical values become zero consecutively are determined to be ineffective blocks. Further, the uppermost divided block Dv whose numerical value is non-zero and the lower divided blocks Dv than the divided block Dv are defined as valid blocks.

For example, m divided blocks Dv. 1~Dv. If the highest divided block Dv whose numerical value is zero among m is the x-th divided block Dv from the lowest (x-th divided block Dv.x) (1≦x≦m), it is continuous from the lowest. x divided blocks Dv. 1~Dv. Let x be a valid block. In addition, (m−x) divided blocks Dv. (x+1)~Dv. Let m be an invalid block.

Note that when the numerical value of the first data D1 is zero, that is, the division processing unit 13 divides all m division blocks Dv. 1~Dv. If the value of m is zero, the first divided block Dv. Only 1 is considered a valid block. As a result, at least one valid block is designated for one piece of first data D1.

If the numerical value of the first data D1 is zero, all divided blocks Dv. 1~Dv. If m is made an ineffective block, a problem arises in that the discrimination bit Dd and second data D2 corresponding to the first data D1 are not stored, and the first data D1 is not restored in the data decompression process. In this embodiment, even when the numerical value of the first data D1 is zero, the first divided block Dv. 1 as a valid block, data corresponding to the first data D1 (determination bit Dd and second data D2, which will be described later) is stored in the storage unit 20. Therefore, also for such first data D1, Restored during data decompression processing.

Each digit of the enable bit of the enable signal De corresponds to the divided block Dv. 1~Dv. Indicates whether each of m is a valid block. In this embodiment, each enable bit digit of the enable signal De corresponds to the corresponding divided block Dv. 1~Dv. It has a value of 1 if m is a valid block, and 0 if it is a non-valid block. Specifically, the p-th divided block Dv. If p is an ineffective block, the pth digit from the lowest enable bit is set to 0. Also, the p-th divided block Dv. If p is a valid block, the pth digit from the lowest enable bit is set to 1.

The storage processing unit 15 stores divided blocks Dv. 1~Dv. m, a valid block is converted into a combination of a 1-bit discrimination bit Dd and an n-bit long second data D2, and is stored in the storage unit 20. As a result, the storage unit 20 stores a plurality of data groups each having a length of n+1 bits, which is a combination of the 1-bit discrimination bit Dd and the second data D2 having a length of n bits.

Specifically, the storage processing unit 15 refers to the enable signal De of the valid blocks in order from the upper side, adds the discrimination bit Dd to the divided block Dv for which the enable signal De is 1, and adds the discrimination bit Dd to the divided block Dv in which the enable signal De is 1. Stored as data D2. At this time, for one piece of first data D1, the lowest first divided block Dv. The discrimination bit Dd corresponding to 1 is assigned 1, and the discrimination bit Dd corresponding to other valid blocks is assigned 0.

Note that the numerical value of the discrimination bit Dd may be 0 and 1, which are reversed. Furthermore, the storage processing unit 15 may store the valid blocks in order from the lower order side as the second data D2. In this case, the numerical value of the determination bit Dd is such that the determination bit Dd corresponding to the next higher-order effective block among the 1 to m valid blocks is a different value from the determination bit Dd corresponding to the other valid blocks.

The decompression processing unit 17 sequentially reads the discrimination bit Dd and the second data D2 stored in the storage unit 20, thereby generating third data D3 that is the restored first data D1. The decompression processing section 17 then delivers the third data D3 to the transmission section 19. Details of the decompression process in the decompression processing section 17 will be described later.

The transmitter 19 outputs the output data Do to the outside of the data processing device 1. The output data Do may be the third data D3 itself, or may be the third data D3 converted into a desired data format.

<1-2. Flow of data compression process>
Next, data compression processing in the data processing device 1 according to the first embodiment will be explained with reference to FIGS. 2 to 4. FIG. 2 is a flowchart showing the flow of data compression processing in the first embodiment. FIG. 3 is a diagram showing an example of data at each stage of data compression processing according to the first embodiment. Note that in the example of FIG. 3, m=4.

In this data compression process, the data processing device 1 converts the first data D1 of m*n bit length into data groups of multiple sets of discrimination bits Dd (1 bit length) and second data D2 (n bit length). The data is converted and stored in the storage unit 20.

As shown in FIG. 2, in the compression process of the sensing data Di, the receiving unit 11 first receives the sensing data Di (step S11). Then, the receiving unit 11 converts the sensing data Di into first data D1 having a length of m*n bits, and delivers it to the division processing unit 13 (step S12).

In the example of FIG. 3, first data D1 having a length of 4×n bits and four divided blocks Dv. 1, Dv. 2, Dv. 3, Dv. 4 and an enable signal De having a length of 4 bits. Further, in the example of FIG. 3, a plurality of combinations of the discrimination bit Dd and the second data D2 are shown as stored data stored in the storage unit 20.

In addition, in FIG. 3, the numerical values of each of these data are shown in the format of data_k_z. Here, k is a value indicating the order of the plurality of first data D1, and z is the numerical value of the divided block Dv from the lower side in the divided blocks Dv obtained by dividing the first data D1 every n bits. It shows whether there is. That is, data_k_z indicates the numerical value of the z-th divided block Dv from the lower side, which is obtained by dividing the k-th first data D1 into every n bits.

That is, in FIG. 3, data_k_1 is the 1st to nth n-bit data from the least significant side of the first data D1, data_k_2 is the n+1st to 2nth n-bit data from the least significant side of the first data D1, data_k_3 indicates 2n+1 to 3nth n-bit data from the least significant side of the first data D1, and data_k_4 indicates 3n+1 to 4nth n-bit data from the least significant side of the first data D1.

Next, the division processing unit 13 divides the m*n-bit length first data D1 into m n-bit length division blocks Dv. 1~Dv. Divide into m (step S13).

Specifically, the first divided block Dv. 1. Second divided block Dv. 2,..., m-th divided block Dv. Let it be m. That is, the first divided block Dv. 1 is the 1st to nth n-bit data from the least significant side of the first data D1, and the second divided block Dv. 2 is the n+1 to 2n-th n-bit data from the lowest side of the first data D1, and the m-th divided block Dv. m is (m-1)*n+1 to m*n-th n-bit data from the least significant side of the first data D1.

In the example of FIG. 3, the first divided block Dv. 1 is data_k_1, and second divided block Dv. 2 is data_k_2, and third divided block Dv. 3 is data_k_3, and the fourth divided block Dv. 4 becomes data_k_4.

The division processing unit 13 then determines the valid blocks and divides each divided block Dv. 1~Dv. An enable signal De indicating which divided block Dv is a valid block among m is generated (step S14). Then, the division processing unit 13 processes the division block Dv. 1~Dv. m and the enable signal De are delivered to the storage processing section 15.

In the example of FIG. 3, the divided block Dv. 1~Dv. Since the number of 4's is 4, the enable bit included in the enable signal De has a length of 4 bits. That is, the entire bit length of the enable signal De is an enable bit. Further, in the example of FIG. 3, the numerical values of each digit of the 4-bit long enable bit are indicated as enable_k_1, enable_k_2, enable_k_3, and enable_k_4. enable_k_1, enable_k_2, enable_k_3, enable_k_4 are the corresponding divided blocks Dv. 1~Dv. 4 is a valid block, 1, the corresponding divided block Dv. 1~Dv. If 4 is an invalid block, it is 0.

Thereafter, the storage processing unit 15 stores the divided block Dv. 1~Dv. A discrimination bit Dd is generated based on m and the enable signal De, and the discrimination bit Dd and second data D2 are stored in the storage unit 20 (S15).

Specifically, the storage processing unit 15 refers to the enable bit of the enable signal De and stores the divided blocks Dv. 1~Dv. Among m, only valid blocks are stored in the storage unit 20 as second data D2. At this time, since the number of second data D2 corresponding to one first data D1 differs depending on the number of valid blocks, in order to determine the break for each first data D1, a determination bit is set for each second data D2. Give Dd.

In this embodiment, 1 to m divided blocks Dv corresponding to one first data D1 are stored in the storage unit 20 as second data D2 in order from the uppermost side. At this time, each second data D2 is stored together with the discrimination bit Dd. That is, the storage unit 20 stores the 1-bit long discrimination bit Dd and the n-bit long second data D2 as a data group.

Furthermore, among the 1 to m pieces of second data D2 corresponding to one first data D1, the value of the discrimination bit Dd corresponding to the second data D2 stored last is set to 1, and the value of the other discrimination bits Dd is set to 1. is set to 0. That is, when storing the second data D2 in order from the upper divided block Dv as in the present embodiment, the first divided block Dv. Let the value of the discrimination bit Dd corresponding to 1 be 1.

In the example of FIG. 3, the first (k=1) effective block of the first data D1 is the first divided block Dv. 1 (the numerical value is data_1_1) and the second divided block Dv. 2 (the numerical value is data_1_2), and the second (k=2) effective block of the first data D1 is the first divided block Dv. 1 (the numerical value is data_2_1) and the second divided block Dv. 2 (the numerical value is data_2_2) and the third divided block Dv. 3 (the numerical value is data_2_3), an example of stored data is shown. In addition, in FIG. 3, on the right side outside the frame of the stored data, it is written for reference which divided block Dv of which first data D1 corresponds.

In this example, the discrimination bit Dd and the second data D2 are stored as one data group in each stage. The first second data D2 is the second divided block Dv. of the first (k=1) first data D1. 2 (the numerical value is data_1_2). The second second data D2 is the first divided block Dv. of the first (k=1) first data D1. 1 (the numerical value is data_1_1). The third second data D2 is the third divided block Dv. of the second (k=2) first data D1. 3 (the numerical value is data_2_3). The fourth second data D2 is the second divided block Dv. of the second (k=2) first data D1. 2 (the numerical value is data_2_2). The fifth second data D2 is the first divided block Dv. of the second (k=2) first data D1. 1 (the numerical value is data_2_1).

The determination bit Dd is 0 and 1 in order for the two second data D2 corresponding to the first (k=1) first data D1, and the second (k=2) first The three second data D2 corresponding to the data D1 are 0, 0, and 1 in this order. That is, for each first data D1, the determination bit Dd of the second data D2 stored last is 1, and the determination bit Dd of the other second data D2 is 0.

When steps S11 to S15 are completed for one piece of sensing data Di, the data processing device 1 determines whether sensing by the sensor 90 has ended (step S16). If it is determined that the sensing has not been completed (step S16: No), the data processing device 1 returns to step S11 and performs steps S11 to S15 on the next sensing data Di. On the other hand, if it is determined that the sensing has ended (step S16: Yes), the data processing device 1 ends the data compression process.

FIG. 4 shows a specific example of data (first data D1, divided data Dv.1 to Dv.4, enable signal De, discrimination bit Dd, and second data D2) at each stage of the data compression process of the first embodiment. FIG. In the example of FIG. 4, the first data D1 is 16 bits, m=4, and n=4.

In the example of FIG. 4, the first data D1 is sequentially from the first (k=1) to the fourth (k=4).
k=1:008a (hexadecimal)/0000000001001010 (binary)
k=2:0f03 (hexadecimal)/0000111100000011 (binary)
k=3:0000 (hexadecimal)/0000000000000000 (binary)
k=4:10c5 (hexadecimal)/0001000011000101 (binary)
It becomes.

Therefore, the first (k=1) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 are 0000, 0000, 0100, and 1010 in order from the upper side. Fourth divided block Dv. 4 and third divided block Dv. 3 is an invalid block because the numerical value is 0. Further, the second divided block Dv. Since the numerical value of 2 is non-zero, the second divided block Dv. 2 and the first divided block Dv. 1 is a valid block. Therefore, in the first (k=1) enable signal De, the fourth and third digits from the least significant side are 0, and the second and first digits from the least significant side are 1.

The second (k=2) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 are 0000, 1111, 0000, 0011 in order from the upper side. Fourth divided block Dv. 4 is an invalid block because the numerical value is 0. Further, the third divided block Dv. Since the numerical value of 3 is non-zero, the third divided block Dv. 3 and the second divided block Dv.3 on the lower side. 2 and the first divided block Dv. 1 is a valid block. Therefore, in the second (k=2) enable signal De, the fourth digit from the least significant side is 0, and the third, second, and first digits from the least significant side are 1.

The third (k=3) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 are 0000, 0000, 0000, 0000 in order from the upper side. All divided blocks Dv. 4, Dv. 3, Dv. Since the value of Dv.2,Dv,1 is 0, the first divided block Dv.2, Dv. Only Dv.1 is a valid block, and the other divided blocks Dv. 4~Dv. 2 is an invalid block. Therefore, in the third (k=3) enable signal De, the fourth, third, and second digits from the lower order side are 0, and the first digit from the lower order side is 1.

Fourth (k=4) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 are 0001, 0000, 1100, 0101 in order from the upper side. The fourth divided block Dv. Since the value of Dv.4 is non-zero, all divided blocks Dv. 4, Dv. 3, Dv. 2,Dv,1 becomes a valid block. Therefore, all four digits of the fourth (4=3) enable signal De are 1.

Such a divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 and the enable signal De are input, the storage processing unit 15 stores the data group of the 1-bit discrimination bit Dd and the 4-bit second data D2 in the storage unit 20 as the first (k= 1) 2 sets for the first data D1, 3 sets for the 2nd (k=2) first data D1, 1 set for the 3rd (k=3) first data D1, and 4th (k=4) Four sets of first data D1 are stored. That is, in this case, ten sets of discrimination bits Dd and second data D2 are stored in the storage unit 20 for four pieces of first data D1.

When storing the four pieces of first data D1 as they are without performing data compression processing, data for 64 bits (16 bits x 4) is stored in the storage unit 20. On the other hand, when the data compression process of this embodiment is performed, in the example of FIG. 4, 50 bits of data are stored in the storage unit 20 in 5 bits x 10 sets. That is, the amount of data to be stored in the storage unit 20 can be compressed.

In this way, by using the data compression process according to the first embodiment, the amount of data to be stored can be reduced. In particular, when the upper digits of the first data D1 are consecutive 0s, the amount of data to be stored can be particularly reduced.

<1-3. Flow of data decompression process>
Next, data decompression processing in the data processing device 1 according to the first embodiment will be explained with reference to FIGS. 5 and 6. FIG. 5 is a flowchart showing the flow of data decompression processing in the first embodiment. FIG. 6 is a diagram showing an example of stored data stored in the storage unit 20 and data at each stage of data decompression processing according to the first embodiment. Note that the example in FIG. 6 corresponds to the stored data example in FIG. 3, and m=4.

In this data decompression process, the data processing device 1 reads out data groups of multiple sets of discrimination bits Dd (1 bit length) and second data D2 (n bit length) stored in the storage unit 20, and Third data D3 (m*n bit length) is generated by restoring D1 (m*n bit length).

As shown in FIG. 5, in the data decompression process, the decompression processing unit 17 first transfers zero data having the same bit length (m*n bit length) as the first data D1 to the third data when starting to read new data. It is prepared as temporary data for D3 (step S21).

Next, the decompression processing unit 17 reads out one data group of the discrimination bit Dd and the second data D2 from the storage unit 20 (step S22). Then, the decompression processing unit 17 inputs the read second data D2 into the first to nth digits from the lowest order of the temporary data of the third data D3.

Subsequently, the decompression processing unit 17 determines whether the second data D2 read out in step S22 is the final block based on the determination bit Dd read out in step S22 (step S23). If the determination bit Dd is 0, the decompression processing unit 17 determines that it is not the final block (step S23: No), proceeds to step S24, and converts each digit of the temporary data of the third data D3 by n bits to the upper side. (step S24). Thereafter, the decompression processing unit 17 proceeds to step S22 and reads out the next determination bit Dd and second data D2.

On the other hand, if the determination bit Dd is 1, the decompression processing unit 17 determines that the block is the final block (step S23: Yes), and uses the third data D3, which was temporary data, as the final third data D3. , is output to the transmitter 19 (step S25). Thereafter, the transmitter 19 outputs output data Do to the outside of the data processing device 1 based on the third data D3. Note that the output data Do may be the third data D3 itself, or may be the third data D3 converted into a desired data format.

Below, using the example of FIG. 6, a specific method of generating the third data D3 in the data decompression process of this embodiment will be described. As shown in the upper part of FIG. 6, in the example of FIG. Three second data D2 (data_2_3, data_2_2, data_2_1) corresponding to the first data D1 (k=1) are stored.

In the example of FIG. 6, provisional data of the third data D3, which is zero data, is prepared in the first step S21. Thereafter, in the first step S22, data_1_2 is read out as the second data D2. Therefore, the first to nth digits from the least significant side of the temporary data of the third data D3 become data_1_2.

Subsequently, in step S23, since the determination bit Dd read in the first step S22 is 0, the decompression processing unit 17 determines that it is not the final block, and shifts the temporary data of the third data D3. (Step S24). As a result, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_1_2, and the 1st to nth digits from the least significant side become 0.

Then, in the second step S22, data_1_1 is read out as the second data D2. Therefore, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_1_2, and the 1st to nth digits from the least significant side become data_1_1.

Subsequently, in step S23, since the determination bit Dd read in the second step S22 is 1, the decompression processing unit 17 determines that it is the final block, and sets the current third data D3 as the final data. Output (step S25). As a result, third data D3 obtained by restoring the first (k=1) first data D1 is output.

After outputting the third data D3, temporary data of the third data D3, which is zero data, is prepared in a second step S21. Thereafter, in the third step S22, data_2_3 is read out as the second data D2. Therefore, the first to nth digits from the least significant side of the temporary data of the third data D3 become data_2_3.

Subsequently, in step S23, since the determination bit Dd read in the third step S22 is 0, the decompression processing unit 17 determines that it is not the final block, and shifts the temporary data of the third data D3. (Step S24). As a result, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_2_3, and the 1st to nth digits from the least significant side become 0.

Thereafter, in the fourth step S22, data_2_2 is read out as the second data D2. Therefore, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_2_3, and the 1st to nth digits from the least significant side become data_2_2.

Subsequently, in step S23, since the determination bit Dd read out in step S22 for the fourth time is 0, the decompression processing unit 17 determines that it is not the final block, and shifts the temporary data of the third data D3. (Step S24). As a result, the 2n+1 to 3n digits from the least significant side of the temporary data of the third data D3 become data_2_3, the n+1 to 2n digits from the least significant side become data_2_2, and the 1st to nth digits from the least significant side become 0. .

Thereafter, in the fifth step S22, data_2_1 is read out as the second data D2. Therefore, the 2n+1 to 3n digits from the least significant side of the temporary data of the third data D3 become data_2_3, the n+1 to 2n digits from the least significant side become data_2_2, and the 1st to nth digits from the least significant side become data_2_1.

Subsequently, in step S23, since the determination bit Dd read out in step S22 for the fifth time is 1, the decompression processing unit 17 determines that it is the final block and sets the current third data D3 as the final data. Output (step S25). As a result, third data D3 obtained by restoring the second (k=2) first data D1 is output.

<2. Second embodiment>
<2-1. Configuration of data processing device>
FIG. 7 is a diagram showing the configuration of a data processing device 1A according to the second embodiment of the present invention. The data processing device 1A stores the time-series sensing data Di input from the sensor 90 as compressed data in the storage processing unit 15A.

As shown in FIG. 7, the data processing device 1A of this embodiment includes a receiving section 11A, a difference calculation processing section 12A, a division processing section 13A, a storage processing section 15A, an expansion processing section 17A, and an addition processing section. 18A, a transmitting section 19A, and a storage section 20A. Note that, below, descriptions of the same matters as in the first embodiment will be omitted.

The receiving unit 11A periodically receives sensing data Di input from the sensor 90, converts it into digital data of m×n bit length, and sets the digital data, which is time series data, as original data D0. The receiving unit 11A then delivers the original data D0 to the difference calculation processing unit 12A.

The difference calculation processing unit 12A calculates the difference between the latest original data D0 and the original data D0 at the previous time, and generates first data D1 indicating the absolute value of the difference and a sign indicating the sign of the difference. A bit Ds is generated. Specifically, the first data D1 is obtained by subtracting the original data D0 at the previous time from the latest original data D0. The difference calculation processing section 12A then delivers the first data D1 and the sign bit Ds to the division processing section 13A.

The bit length of the first data D1 is m*n bits, which is the same as the bit length of the original data D0. The sign bit Ds is data indicating whether the calculated difference is positive or negative. In this embodiment, when the calculated difference is a positive number, the sign bit Ds is 0, and when the calculated difference is a negative number, the sign bit Ds is 1.

Note that when the original data D0 is input to the difference calculation processing unit 12A for the first time (first time), the first data D1 is set to the same numerical value as the original data D0, and the sign bit Ds is set to indicate "positive". value (0 in this embodiment).

The division processing unit 13A divides the first data D1 into a plurality of m division blocks Dv each having a length of n bits. Here, each of the plurality of divided blocks Dv is a first divided block Dv. 1. Second divided block Dv. 2,..., m-th divided block Dv. It is called m.

The division processing unit 13A divides m division blocks Dv. 1~Dv. It is determined which data among m is a valid block that should be stored in the storage unit 20A or an ineffective block that should not be stored. Then, the division processing unit 13A generates one enable signal De including an m-bit length enable bit for one piece of first data D1. The division processing unit 13A processes each division block Dv. 1~Dv. m, the enable signal De, and the sign bit Ds generated by the difference calculation processing section 12A are delivered to the storage processing section 15A.

Specifically, like the division processing unit 13 of the first embodiment, the division processing unit 13A divides the uppermost division block Dv. Starting from m, divided blocks Dv whose numerical values become zero consecutively are determined to be ineffective blocks. Further, the uppermost divided block Dv whose numerical value is non-zero and the lower divided blocks Dv than the divided block Dv are defined as valid blocks. In addition, when the numerical value of the first data D1 is zero, the division processing unit 13A performs a process in which all m division blocks Dv. 1~Dv. If the value of m is zero, the first divided block Dv. Only 1 is considered a valid block.

Each digit of the enable bit of the enable signal De corresponds to the divided block Dv. 1~Dv. Indicates whether each of m is a valid block. In this embodiment, each enable bit digit of the enable signal De corresponds to the corresponding divided block Dv. 1~Dv. It has a value of 1 if m is a valid block, and 0 if it is a non-valid block.

The storage processing unit 15A stores divided blocks Dv. 1~Dv. m, a valid block is converted into a combination of a 1-bit discrimination bit Dd, a sign bit Ds, and an n-bit length of second data D2, and is stored in the storage unit 20A. As a result, the storage unit 20A stores a plurality of n+2 bit long data groups that are a combination of the 1-bit discrimination bit Dd, the 1-bit sign bit Ds, and the n-bit long second data D2.

Specifically, the storage processing unit 15A sequentially refers to the enable signal De from the upper side, adds the discrimination bit Dd to the divided block Dv for which the enable signal De is 1, and adds the discrimination bit Dd and the sign bit Ds to the divided block Dv. 2 data D2.

The decompression processing unit 17A generates third data D3, which is the restored first data D1, as read data by sequentially reading out the discrimination bit Dd, code bit Ds, and second data D2 stored in the storage unit 20A. The decompression processing in the decompression processing section 17A is performed in the same manner as in the decompression processing section 17A of the first embodiment. The expansion processing section 17A then delivers the third data D3 and the code bit Ds read from the storage section 20A to the addition processing section 18A.

The addition processing section 18A refers to the sign bit Ds, adds or subtracts the third data D3 delivered from the decompression processing section 17A to the fourth data D4 at the previous time, and generates new fourth data D4. calculate. The fourth data D4 is the final output data. Specifically, when the sign bit Ds delivered together with the third data D3 is a numerical value indicating "positive", the third data D3 and the fourth data D4 of the previous time are added. , new fourth data D4. On the other hand, if the sign bit Ds delivered together with the third data D3 is a numerical value indicating "negative", the third data D3 is subtracted from the fourth data D4 of the previous time, and a new 4 data D4.

The transmitter 19A outputs the output data Do to the outside of the data processing device 1A. The output data Do may be the fourth data D4 itself, or may be the fourth data D4 converted into a desired data format.

<2-2. Flow of data compression process>
Next, data compression processing in the data processing device 1A according to the second embodiment will be explained with reference to FIGS. 8 and 9. FIG. 8 is a flowchart showing the flow of data compression processing according to the second embodiment. FIG. 9 is a diagram showing an example of data at each stage of the data compression process according to the first embodiment. Note that in the example of FIG. 9, m=4.

In this data compression process, the data processing device 1A converts m*n bit length first data D1 into multiple sets of discrimination bit Dd (1 bit length), sign bit Ds (1 bit length), and second data D2 ( n bits long) and stored in the storage unit 20A.

As shown in FIG. 8, in the compression process of the sensing data Di, first, the receiving unit 11A receives the sensing data Di (step S31). Then, the receiving unit 11A converts the sensing data Di into original data D0 of m*n bit length and delivers it to the difference calculation processing unit 12A (step S32).

In the example of FIG. 9, original data D0 and first data D1 each having a length of 4×n bits, and four divided blocks Dv. 1, Dv. 2, Dv. 3, Dv. 4, a 1-bit long code bit Ds, and a 4-bit long enable signal De. Furthermore, in the example of FIG. 3, a plurality of combinations of the discrimination bit Dd, the sign bit Ds, and the second data D2 are shown as the stored data stored in the storage unit 20.

Note that in FIG. 9, the numerical values of each of these data are shown in the format of data0_k_z and data_k_z. Here, k is a value indicating the order of the plurality of original data D0 or first data D1, and z is a value indicating the order of the plurality of original data D0 or first data D1, and z is a value indicating the order of the plurality of original data D0 or first data D1 from the lower order in the divided block Dv obtained by dividing the original data D0 or first data D1 into every n bits. This indicates whether it is the numerical value of the th divided block Dv.

Following step S32, the difference calculation processing unit 12A performs a difference calculation process of step S33. In the first step S33, the difference calculation processing unit 12A sets the numerical value of the first data D1 to be the same as the numerical value of the original data D0, and sets the sign bit Ds to "positive" because the original data D0 of the previous time does not exist. ” is set to 0.

In addition, in the second and subsequent k-th steps S33, the difference calculation processing unit 12A calculates the difference between the original data D0 at the current time (k-th time) and the original data D0 at the previous time (k-1st time). Calculate. Specifically, the difference is calculated by subtracting the original data D0 at the previous time (k-1st time) from the original data D0 at the current time (kth time). Then, the absolute value of the calculated difference is set as the numerical value of the first data D1, and a sign bit Ds is generated based on the sign of the difference (step S33). At this time, in this embodiment, the sign bit Ds is set to 0 when the difference is a positive value, and the sign bit Ds is set to 1 when the difference is a negative value. Thereafter, the difference calculation processing section 12A delivers the first data D1 and the sign bit Ds to the division processing section 13A.

In addition, in FIG. 9, the numerical value of the 1st to nth n bits from the least significant side of the original data D0 at the current time (kth time) is data0_k_1, the numerical value of the n+1 to 2nth n bits from the least significant side is designated as data0_k_2, and the most significant value is The numerical value of the 2n+1 to 3nth n bits from the least significant side is data0_k_3, and the numerical value of the 3n+1 to nth n bits from the least significant side is data0_k_4.

Similarly, in FIG. 9, the 1st to nth n bits from the least significant side of the original data D0 at the previous time (k-1st time) are data0_k-1_1, and the n+1 to 2nth values from the least significant side are The n-bit value is data0_k-1_2, the 2n+1 to 3n-th n-bit value from the least significant side is data0_k-1_3, and the 3n+1 to n-th n-bit value from the least significant side is data0_k-1_4.

In FIG. 9, the numerical value of the 1st to nth n bits from the least significant side of the first data D1 calculated in the k-th step S33 is referred to as data_k_1, the numerical value of the n+1 to 2nth n bits from the least significant side is referred to as data_k_2, and the numerical value of the n bits from the least significant side is referred to as data_k_2. The numerical value of the 2n+1 to 3nth n bits from the least significant side is defined as data_k_3, and the numerical value of the 3n+1 to nth n bits from the least significant side is defined as data_k_4. Further, in FIG. 9, the numerical value of the sign bit Ds generated in the k-th step S33 is set as pnsign_k.

Next, the division processing unit 13A divides the m*n-bit length first data D1 into m n-bit length division blocks Dv. 1~Dv. Divide into m (step S34).

Specifically, the first divided block Dv. 1. Second divided block Dv. 2,..., m-th divided block Dv. Let it be m. In the example of FIG. 9, the first divided block Dv. 1 is data_k_1, and second divided block Dv. 2 is data_k_2, and third divided block Dv. 3 is data_k_3, and the fourth divided block Dv. 4 becomes data_k_4.

The division processing unit 13A then determines valid blocks and divides each divided block Dv. 1~Dv. An enable signal De indicating which divided block Dv is a valid block among m is generated (step S35). Then, the division processing unit 13A processes the division block Dv. 1~Dv. m and the enable signal De are delivered to the storage processing section 15A together with the sign bit Ds.

In the example of FIG. 9, the number of divided blocks Dv is four, so the enable bit included in the enable signal De has a length of four bits. That is, the entire bit length of the enable signal De is an enable bit. Further, in the example of FIG. 3, the numerical values of each digit of the 4-bit long enable bit are indicated as enable_k_1, enable_k_2, enable_k_3, and enable_k_4. enable_k_1, enable_k_2, enable_k_3, enable_k_4 are the corresponding divided blocks Dv. 1~Dv. 4 is a valid block, 1, the corresponding divided block Dv. 1~Dv. If 4 is an invalid block, it is 0.

After that, the storage processing unit 15A stores the divided block Dv. 1~Dv. A discrimination bit Dd is generated based on m and the enable signal De, and the discrimination bit Dd, sign bit Ds, and second data D2 are stored in the storage unit 20 (step S36).

Specifically, the storage processing unit 15 refers to the enable bit of the enable signal De and stores the divided blocks Dv. 1~Dv. Among m, only valid blocks are stored in the storage unit 20 as second data D2. At this time, since the number of second data D2 corresponding to one first data D1 differs depending on the number of valid blocks, in order to determine the break for each first data D1, a determination bit is set for each second data D2. Give Dd. Then, the second data D2 is stored in the storage unit 20 together with the discrimination bit Dd and the sign bit Ds. That is, the storage unit 20 stores a 1-bit long discrimination bit Dd, a 1-bit long code bit Ds, and an n-bit long second data D2 as a data group.

In the example of FIG. 9, the first (k=1) effective block of the first data D1 is the first divided block Dv. 1 (the numerical value is data_1_1) and the second divided block Dv. 2 (the numerical value is data_1_2) and the third divided block Dv. 3 (the numerical value is data_1_3), and the second (k=2) effective block of the first data D1 is the first divided block Dv. 1 (the numerical value is data_2_1) and the second divided block Dv. 2 (the numerical value is data_2_2), and the second (k=2) sign bit Ds is 1 indicating "negative".

In this example, a discrimination bit Dd, a sign bit Ds, and second data D2 are stored as a data group in each stage. The first second data D2 is the third divided block Dv. of the first (k=1) first data D1. 3 (the numerical value is data_1_3). The second second data D2 is the second divided block Dv. of the first (k=1) first data D1. 2 (the numerical value is data_1_2). The third second data D2 is the first divided block Dv. of the first (k=1) first data D1. 1 (the numerical value is data_1_1).

The fourth second data D2 is the second divided block Dv. of the second (k=2) first data D1. 2 (the numerical value is data_2_2). The fifth second data D2 is the first divided block Dv. of the second (k=2) first data D1. 1 (the numerical value is data_2_1).

The determination bit Dd is 0, 0, 1 in order for the three second data D2 corresponding to the first (k=1) first data D1, and is 0, 0, 1 for the second (k=2) first data D1. The two second data D2 corresponding to the first data D1 are 0 and 1 in that order. That is, for each first data D1, the determination bit Dd of the second data D2 stored last is 1, and the determination bit Dd of the other second data D2 is 0.

Moreover, the sign bit Ds is 0 indicating "positive" for the three second data D2 corresponding to the first (k=1) first data D1, since this is the first first data D1. It has become. Further, the sign bits Ds corresponding to the two second data D2 corresponding to the second (k=2) first data D1 are both 1 indicating "negative". In this way, the code bits Ds corresponding to the same first data D1 have the same numerical value.

When steps S31 to S36 are completed for one piece of sensing data Di, the data processing device 1A determines whether sensing by the sensor 90 has ended (step S37). If it is determined that sensing has not been completed (step S37: No), the data processing device 1A returns to step S31 and performs steps S31 to S36 on the next sensing data Di. On the other hand, if it is determined that the sensing has ended (step S37: Yes), the data processing device 1A ends the data compression process.

10 and 11 show data at each stage of the data compression process of the second embodiment (original data D0, first data D1, divided data Dv.1 to Dv.4, sign bit Ds, enable signal De, discrimination bit FIG. 4 is a diagram showing a specific example of Dd and second data D2). In the examples of FIGS. 10 and 11, the original data D0 is 16 bits, m=4, and n=4.

In the example of FIG. 10, the original data D0 is sequentially from the first (k=1) to the fourth (k=4).
k=1:534a (hexadecimal)/0101001101001010 (binary)
k=2:5323 (hexadecimal)/0101001100100011 (binary)
k=3:532c (hexadecimal)/0101001100101100 (binary)
k=4:5315 (hexadecimal)/0101001100010101 (binary)
It becomes.

The first data D1 is sequentially from the first (k=1) to the fourth (k=4).
k=1:534a (hexadecimal)/0101001101001010 (binary)
k=2:0027 (hexadecimal)/0000000000100111 (binary)
k=3:0009 (hexadecimal)/0000000000001001 (binary)
k=4:0017 (hexadecimal)/0000000000010111 (binary)
The code bits Ds are sequentially from the first (k=1) to the fourth (k=4):
k=1:0
k=2:1
k=3:0
k=4:1
It becomes.

When k=1, the first data D1 has the same numerical value as the original data D0, and the sign bit Ds is 0 indicating "positive". The first data D1 with k=2 is the absolute value of the result of subtracting the original data D0 with k=1 from the original data D0 with k=2. Further, since the numerical value of the original data D0 with k=2 is smaller than the numerical value of the original data D0 with k=1, the sign bit Ds is 1 indicating "negative". The first data D1 with k=3 is the absolute value of the result of subtracting the original data D0 with k=2 from the original data D0 with k=3. Further, since the numerical value of the original data D0 with k=3 is larger than the numerical value of the original data D0 with k=2, the sign bit Ds is 0 indicating "positive". The first data D1 with k=4 is the absolute value of the result of subtracting the original data D0 with k=3 from the original data D0 with k=4. Further, since the numerical value of the original data D0 with k=4 is smaller than the numerical value of the original data D0 with k=3, the sign bit Ds is 1 indicating "negative".

In the example of FIG. 10, the first (k=1) divided block Dv. 4, Dv. 3, Dv. 2, Dv, and 1 are all non-zero. Therefore, all divided blocks Dv. 1 to 4 are valid blocks. Therefore, all four digits of the first (k=1) enable signal De are 1.

The second (k=2) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 is the fourth divided block Dv. 4 and third divided block Dv. Since the value of 3 is 0, it is an invalid block. Further, the second divided block Dv. Since the numerical value of 2 is non-zero, the second divided block Dv. 2 and the first divided block Dv. 1 is a valid block. Therefore, in the second (k=2) enable signal De, the fourth and third digits from the least significant side are 0, and the second and first digits from the least significant side are 1.

The third (k=3) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 are the fourth divided blocks Dv. 4. Third divided block Dv. 3 and the second divided block Dv. 2 is 0, the lowest first divided block Dv. Only Dv.1 is a valid block, and the other divided blocks Dv. 4~Dv. 2 is an invalid block. Therefore, in the third (k=3) enable signal De, the fourth, third, and second digits from the lower order side are 0, and the first digit from the lower order side is 1.

Fourth (k=4) divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1 is the fourth divided block Dv. 4 and third divided block Dv. Since the value of 3 is 0, it is an invalid block. Further, the second divided block Dv. Since the numerical value of 2 is non-zero, the second divided block Dv. 2 and the first divided block Dv. 1 is a valid block. Therefore, in the fourth (k=4) enable signal De, the fourth and third digits from the least significant side are 0, and the second and first digits from the least significant side are 1.

Such a divided block Dv. 4, Dv. 3, Dv. 2, Dv, 1, when the enable signal De and the sign bit Ds are input, the storage processing unit 15 stores the 1-bit discrimination bit Dd, the 1-bit sign bit Ds, and the 4-bit second data in the storage unit 20. The data group of D2 is divided into four sets for the first (k=1) first data D1, two sets for the second (k=2) first data D1, and three sets for the third (k=3) first data D1. One set is stored for the first data D1, and two sets are stored for the fourth (k=4) first data D1. That is, in this case, nine sets of discrimination bits Dd and second data D2 are stored in the storage unit 20 for four pieces of first data D1.

When storing the four pieces of first data D1 as they are without performing data compression processing, data for 64 bits (16 bits x 4) is stored in the storage unit 20. On the other hand, when the data compression process of this embodiment is performed, in the example of FIG. 4, 54 bits of data are stored in the storage unit 20 in 6 bits x 9 sets. That is, the amount of data to be stored in the storage unit 20 can be compressed.

In this way, by using the data compression process according to the second embodiment, the amount of data to be stored can be reduced. In particular, when the input data is time-series sensing data Di, the sensing data Di often have similar numerical values at consecutive times. In such a case, when the first data D1 is calculated as a difference from the previous time, the number of consecutive zero digits of the first data D1 increases from the highest order. In other words, the number of invalid blocks increases. Therefore, the number of second data D2 to be stored in the storage unit 20 can be significantly reduced.

<2-3. Flow of data decompression process>
Next, data decompression processing in the data processing device 1A according to the second embodiment will be described with reference to FIGS. 12 and 13. FIG. 12 is a flowchart showing the flow of data decompression processing in the second embodiment. FIG. 13 shows an example of stored data stored in the storage unit 20A, and examples of third data D3 and fourth data D4 at each stage of the data decompression process of the second embodiment, which correspond to the stored data. It is a diagram. Note that the example in FIG. 13 corresponds to the stored data example in FIG. 3, and m=4.

In this data decompression process, the data processing device 1A stores multiple sets of discrimination bits Dd (1 bit length), code bits Ds (1 bit length), and second data D2 (n bit length) stored in the storage unit 20A. The data group is read and fourth data D4 (m*n bit length) is generated by restoring the original data D0 (m*n bit length).

As shown in FIG. 12, in the data decompression process, the decompression processing unit 17A first transfers zero data having the same bit length (m*n bit length) as the first data D1 to the third data when starting to read new data. It is prepared as temporary data for D3 (step S41).

Next, the decompression processing unit 17A reads out one data group of the discrimination bit Dd, the sign bit Ds, and the second data D2 from the storage unit 20A (step S42). Then, the decompression processing unit 17A inputs the read second data D2 to the first to nth digits from the least significant side of the temporary data of the third data D3.

Subsequently, the decompression processing unit 17A determines whether the second data D2 read out in step S42 is the final block based on the determination bit Dd read out in step S42 (step S43). If the determination bit Dd is 0, the decompression processing unit 17A determines that it is not the final block (step S43: No), proceeds to step S44, and converts each digit of the temporary data of the third data D3 by n bits to the upper side. (step S44). Thereafter, the decompression processing unit 17A proceeds to step S42 and reads out the next determination bit Dd, sign bit Ds, and second data D2.

On the other hand, if the determination bit Dd is 1, the decompression processing unit 17A determines that the block is the final block (step S43: Yes), and uses the third data D3, which was temporary data, as the final third data D3. , and the sign bit Ds are delivered to the addition processing section 18A, and the process proceeds to step S45.

When the third data D3 and the sign bit Ds are delivered, the addition processing unit 18A adds the newly input third data D3 at the current time and the fourth data D4 at the previous time (step S45 ).

In the first step S45, the addition processing unit 18A sets the numerical value of the delivered third data D3 as the numerical value of the fourth data D4 since the fourth data D4 of the previous time does not exist.

Further, in the second and subsequent k-th steps S45, the addition processing unit 18A adds the current time (k-th time) to the fourth data D4 at the previous time (k-1st time) based on the sign bit Ds. The third data D3 in is added or subtracted.

Specifically, when the sign bit Ds of the current time (kth time) is 0 indicating "positive", the numerical value of the fourth data D4 of the previous time (k-1st time) and the current time The value obtained by adding the numerical values of the third data D3 (kth time) is set as the new fourth data D4 of the current time (kth time).

On the other hand, if the sign bit Ds of the current time (kth time) is 1 indicating "negative", the current time (kth time) is calculated from the value of the fourth data D4 of the previous time (k-1st time). ) is subtracted from the third data D3, and the result is set as the new fourth data D4 at the current time (kth time).

After that, the addition processing section 18A outputs the calculated fourth data D4 to the transmission section 19A (step S46). Thereafter, the transmitter 19A outputs output data Do to the outside of the data processing device 1A based on the fourth data D4. Note that the output data Do may be the fourth data D4 itself, or may be the fourth data D4 converted into a desired data format.

Below, using the example of FIG. 13, a specific method of generating the third data D3 in the data decompression process of this embodiment will be described. As shown in the upper part of FIG. 13, in the example of FIG. 13, three second data D2 (data_1_3, data_1_2, data_1_1) corresponding to the first (k=1) first data D1 are stored in the storage unit 20. Two second data D2 (data_2_2, data_2_1) corresponding to the second (k=1) first data D1 are stored.

In the example of FIG. 13, provisional data of the third data D3, which is zero data, is prepared in the first step S41. Thereafter, in the first step S42, data_1_3 is read out as the second data D2. Therefore, the first to nth digits from the least significant side of the temporary data of the third data D3 become data_1_3.

Subsequently, in step S43, since the determination bit Dd read in the first step S42 is 0, the decompression processing unit 17A determines that it is not the final block, and shifts the temporary data of the third data D3. (Step S44). As a result, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_1_3, and the 1st to nth digits from the least significant side become 0.

Then, in the second step S42, data_1_2 is read out as the second data D2. Therefore, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_1_3, and the 1st to nth digits from the least significant side become data_1_2.

Subsequently, in step S43, since the determination bit Dd read in the second step S42 is 0, the decompression processing unit 17A determines that it is not the final block, and shifts the temporary data of the third data D3. (Step S44). As a result, the 2n+1 to 3n digits from the least significant side of the temporary data of the third data D3 become data_1_3, the n+1 to 2n digits from the least significant side become data_1_2, and the 1st to nth digits from the least significant side become 0.

Then, in the third step S42, data_1_1 is read out as the second data D2. Therefore, the 2n+1 to 3n digits from the least significant side of the temporary data of the third data D3 are data_1_3, the n+1 to 2n digits from the least significant side are data_1_2, and the 1st to n digits from the least significant side are data_1_1.
becomes.

Subsequently, in step S43, since the discrimination bit Dd read in the second step S42 is 1, the decompression processing unit 17A determines that it is the final block, and saves the current third data along with the sign bit Ds. D3 is passed to the addition processing section 18A as final data, and the process proceeds to step S45. As a result, the third data D3 obtained by restoring the first (k=1) first data D1 and the sign bit Ds are delivered to the addition processing section 18A.

In step S45, the delivered third data D3 is the first (k=1) third data D3 and the fourth data D4 of the previous time does not exist, so the addition processing unit 18A The numerical value of the third data D3 is used as the fourth data D4. Then, the fourth data D4 is output (step S46).

After outputting the fourth data D4, temporary data of the third data D3, which is zero data, is prepared again in a second step S41. Thereafter, in the fourth step S22, data_2_2 is read out as the second data D2. Therefore, the first to nth digits from the least significant side of the temporary data of the third data D3 become data_2_2.

Subsequently, in step S43, since the determination bit Dd read out in step S42 for the fourth time is 0, the decompression processing unit 17A determines that the block is not the final block, and shifts the temporary data of the third data D3. (Step S44). As a result, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_2_2, and the 1st to nth digits from the least significant side become 0.

Thereafter, in the fifth step S42, data_2_1 is read out as the second data D2. Therefore, the n+1 to 2n digits from the least significant side of the temporary data of the third data D3 become data_2_2, and the 1st to nth digits from the least significant side become data_2_1.

Subsequently, in step S43, since the discrimination bit Dd read out in step S22 for the fifth time is 1, the decompression processing unit 17A determines that it is the final block, and converts the current third data D3 into Together with the sign bit Ds read out in the fifth step S22, it is delivered to the addition processing section 18A as final data.

Since the sign bit Ds is 1 indicating "negative", the addition processing unit 18A subtracts the current third data D3 from the previous fourth data D4 (step S45). Specifically, from the numerical values 0, data_1_3, data_1_2, data_1_1 for every n bits from the high-order side, the numerical values 0, 0, data_2_2, data_2_1 for every n bits from the high-order side are subtracted. As a result, new fourth data D4 is calculated. This new fourth data D4 has the same numerical value as the second (k=2) original data D0 (data0_1_4, data0_1_3, data0_1_2, data0_1_1 for every n bits from the high-order side). Then, the fourth data D4 is output (step S46).

<3. Modified example>
Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment.

In the above embodiment, the method and apparatus for compressing the original data D0 or the first data D1 having a length of m*n bits and decompressing it again have been described. As a specific example, the case where the number of divided blocks Dv is m=4 and the bit length of the divided blocks Dv is n=4 has been given, but the present invention is not limited to this. For example, m=16, n=8, and the original data D0 or first data D1 may have a length of 128 bits.

Furthermore, the elements appearing in the above-described embodiments and modifications may be combined as appropriate to the extent that no contradiction occurs.

1, 1A Data processing device 12A Difference calculation processing section 13, 13A Division processing section 15, 15A Storage processing section 17, 17A Decompression processing section 18A Addition processing section 20, 20A Storage section D0 Original data D1 First data D2 Second data D3 3rd data D3 4th data D4 4th data Dd Discrimination bit De enable signal Ds Sign bit Dv Divided block

Claims (13)

A data processing method, comprising:
a) dividing the first data having a length of m*n bits into m divided blocks having a length of n bits;
b) determining a valid block to be stored among the divided blocks;
c) storing the valid block;
has
In the step b), data processing in which the uppermost divided block whose numerical value is non-zero and the lower divided blocks than the uppermost divided block whose numerical value is non-zero are used as the valid blocks. Method. The data processing method according to claim 1,
In step b), one enable signal including an m-bit length enable bit is generated for one piece of the first data;
If the p-th divided block from the lowest order is not the valid block, the p-th digit from the lowest order of the enable bit is set to 0;
The data processing method includes setting the pth digit of the enable bit to 1 when the pth divided block from the lowest order is the valid block. The data processing method according to claim 1,
The step c) is
c1) adding a 1-bit long discrimination bit to each of the valid blocks;
c2) storing the discrimination bit and n-bit second data having the same numerical value as the valid block;
data processing methods, including; 4. The data processing method according to claim 3,
In the step c1),
When the number of the valid blocks is one for one piece of the first data, the determination bit corresponding to the valid block is set to 1,
When there is a plurality of valid blocks for one piece of the first data, the determination bit for the lowest valid block is set to 1, and the determination bit for the other valid blocks is set to 0;
In the step c2),
A data processing method, wherein the discrimination bits and the second data for one piece of the first data are stored in order from the most significant side. 5. The data processing method according to claim 4,
After said step c),
d) preparing new m*n bit length zero data as new read data;
e) reading the stored discrimination bit and the second data;
f) setting n bits from the least significant side of the read data as a numerical value of the second data read in the step e);
and
If the determination bit read in step e) is 0, after step f),
g) After performing the step of shifting all the non-zero bits of the read data upward by n bits, return to the step e) again,
If the determination bit read in step e) is 1, after step f),
h) A data processing method, comprising the step of outputting the read data as third data. The data processing method according to any one of claims 1 to 5,
Before the step a), the step b), and the step c), p) obtaining original data that is time series data;
q) calculating the first data that is the difference between the latest original data and the original data at the previous time;
A data processing method further comprising: 6. The data processing method according to claim 5,
Before the step a), the step b), and the step c), p) obtaining original data that is time series data;
q) calculating the first data that is the difference between the latest original data and the original data at the previous time;
It further has
After the step h),
r) adding the outputted third data to fourth data at the previous time to calculate new fourth data;
data processing methods. A data processing device that stores data in a storage section provided externally or internally,
a division processing unit that divides the first data having a length of m*n bits into m divided blocks each having a length of n bits, and determines an effective block to be stored among the divided blocks;
a storage processing unit that sequentially stores the valid blocks in the storage unit;
has
The division processing unit performs data processing in which the uppermost divided block whose numerical value is non-zero and the lower divided blocks than the uppermost divided block whose numerical value is non-zero are used as the valid blocks. Device. 9. The data processing device according to claim 8,
The division processing unit is
generating one enable signal including an m-bit length enable bit for one piece of the first data;
If the p-th divided block from the lowest order is not the valid block, the p-th digit from the lowest order of the enable bit is set to 0;
In the data processing device, when the p-th divided block from the lowest order is the valid block, the p-th digit from the lowest order of the enable bit is set to 1. 9. The data processing device according to claim 8,
The storage processing unit includes:
assigning a 1-bit long discrimination bit to each of the valid blocks;
storing the discrimination bits for one of the first data and n-bit second data having the same numerical value as the valid block in the storage unit in order from the most significant side;
The storage processing unit includes:
When the number of the valid blocks is one for one piece of the first data, the determination bit corresponding to the valid block is set to 1,
When there is a plurality of valid blocks for one piece of the first data, the determination bit for the lowest valid block is set to 1, and the determination bit for the other valid blocks is set to 0. The data processing device according to claim 10,
further comprising an expansion processing unit that reads the discrimination bit and the second data from the storage unit and generates third data that is a restored version of the first data;
The decompression processing section includes:
S) preparing new m*n bit length zero data as new read data;
T) reading the discrimination bit and the second data stored in the storage unit;
U) a step of setting n bits from the least significant side of the read data as a numerical value of the second data read in the step T);
and
If the discrimination bit read in the step T) is 0, after the step U),
V) After performing the step of shifting all the non-zero bits of the read data to the upper n bits, return to the step T) again,
If the discrimination bit read in the step T) is 0, after the step U),
W) A data processing device that performs the step of outputting the read data. The data processing device according to any one of claims 8 to 11,
A data processing device further comprising a difference calculation processing unit that calculates the first data that is a difference between m*n bit length original data that is time series data and the original data at a previous time. The data processing device according to claim 11,
a difference calculation processing unit that calculates the first data that is the difference between m*n bit length original data that is time series data and the original data at the previous time;
an addition processing unit that calculates fourth data obtained by restoring the original data based on the third data output by the expansion processing unit;
It further has
The addition processing unit is a data processing device that calculates new fourth data by adding the fourth data of the previous time and the new third data.

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