JP2023164990A - Event-based vision sensor manufactured with 3d-ic technology - Google Patents

Abstract

To provide an event-based vision sensor by using an advanced stacking technology, known as Three-Dimensional Integrated Circuit technology.SOLUTION: In three-dimensional integration, many wafers (or dies) are stacked and are interconnected vertically. An electronic integrated circuit of a sensor is distributed between two or more electrically connected dice. On a wafer 1, a photosensitive device such as a PD is formed, and on a wafer 2, a pixel circuit such as a PR or an event generator is formed. Both wafers are bonded via a Cu-Cu bonded portion CC.SELECTED DRAWING: Figure 3A

Description

This application incorporates the benefit of U.S. Provisional Application No. 62/642,838, filed March 14, 2018, under 35 U.S.C. S. C. §119(e), the provisional application being incorporated herein by reference.

One of the important parameters in the design of an event-based pixel array (also referred to as a dynamic vision sensor (DVS)) is quantum efficiency (QE). Quantum efficiency (QE) is the ratio of the number of electrons generated for an optical signal to the number of photons of this optical signal. This parameter depends directly on the fill-factor (FF). The fill factor (FF) is the ratio of the area of the photosensitive device that is exposed to the total area of the integrated circuit that is exposed.

Today, event-based vision sensors are realized using silicon planar processes, so that the exposed area is shared between the photosensitive device and other semiconductor devices that make up the pixel circuit. This approach has two main drawbacks. One is that the area of the photosensitive device is limited, and the other is that circuitry that does not need to be exposed is exposed to light, which degrades the performance of the circuit.

The main objective of the present invention is to alleviate these two problems using advanced lamination techniques in the manufacture of event-based vision sensors. Such advanced stacking technology is known as three-dimensional integrated circuit (3D-IC) technology. 3D-IC technology allows many wafers (or dies) to be stacked and interconnected vertically.

The existing motives include:

Increase FF.

Shielding circuits that do not need to or should not receive light.

Establish different requirements for different components of a pixel. To meet this requirement, it is optimal to realize each of these components in a different IC process (the photosensitive device could theoretically be fabricated in non-silicon-based technologies, e.g. GaAs). .

In general, in one aspect, the invention features that an event-based vision sensor (EBVS) includes vertically connected stacked dies. As a result, the photosensitive device of each pixel of the pixel array can be placed on the die to be exposed, and other devices not used for receiving light can be placed on other wafers or dies.

Preferably, there is at least one connection for every pixel in the inter-die pixel array.

Typically, a photodiode for each pixel in the pixel array is located on a first die, and an event detector for each pixel in the pixel array on a second die and an interconnect between the first and second die. A diode is connected to each event detector.

This technique can be used for both front-illuminated structures and back-illuminated structures.

Also, there are many different ways to implement the photoreceptor circuitry for each pixel in the pixel array. For example, the photoreceptor circuit can be located on the second die, it can be located on the first die, or it can be distributed between the first die and the second die.

Additional amplifier stages may be added to the first die.

Often, n-FET transistors are used in a first wafer or die, and both n-FET and p-FET transistors are used in a second die.

Also, the transistor characteristics of the transistor on the first die and the transistor on the second die may be different, the gate oxide thickness may be different, or the implant may be different.

In general, in one aspect, the invention features a method of manufacturing an event-based vision sensor. Typically, this method involves manufacturing a different device for each pixel of the pixel array on a different wafer or die, and then stacking the wafers or dies.

As used herein, the term "die" refers to a portion of a semiconductor wafer, typically having a rectangular shape, such as a chip. Here, the portion of the semiconductor wafer includes a portion of an example integrated circuit device, such as an event-based vision sensor. Reference to wafer or die is based on the possibility of different manufacturing techniques. The stacking may be performed at the wafer level before dicing into dies, or the stacking may be performed on individual dies after the dies are cut out from the wafer (dicing is performed). As a result, the final device obtained by such a manufacturing process is a stacked die.

The method then includes connecting each pixel using, for example, a Cu-Cu junction.

In one embodiment, the method further includes fabricating a photodiode for each pixel of the pixel array on the first wafer or die and fabricating an event detector for each pixel of the pixel array on the second wafer or die. including.

These and other features and other advantages of the invention, including various novel details as to construction and combinations of parts, will be described in detail in the specification with reference to the accompanying drawings, and pointed out in the claims. . It is understood that the particular methods and devices implementing the invention are not limiting, and are shown by way of example only. The principles and features of the invention may be embodied in various embodiments without departing from the scope of the invention.

In the accompanying drawings, the same reference numerals indicate the same parts in different drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 shows, for example, PCT/IB2017/058526 and U. S. Pub. No. 2018/0191972 is a circuit diagram illustrating an example of a pixel according to the prior art for an event-based image sensor; FIG.

2A-2C show a conventional event-based image sensor implemented by a single wafer (FIGS. 2A and 2B show a partial longitudinal cross-sectional view, and FIG. 2C shows a partial top view). FIG. 2A shows an example of application to front-side illumination (FSI). FIG. 2B shows an example of application to back-side illumination (BSI). FIG. 2C shows a partial top view.

FIG. 3A shows a partial vertical cross-sectional view of two stacked wafers according to a preferred embodiment prior to wafer dicing. FIG. 3B is a partial vertical cross-sectional view focused on one pixel, showing a back-side illumination (BSI) top wafer containing only a photo-diode (PD) and one of the connections connecting each pixel to the bottom wafer. shows. FIG. 3C is a block diagram showing details of the pixel front end circuitry and how it is placed between the wafers/dies. FIG. 3D is a circuit diagram showing details of the pixel front end circuitry and how it is placed between the wafers/dies. .

FIG. 4A shows a partial longitudinal cross-sectional view of two stacked wafers according to another embodiment in which the top wafer further includes two transistors of a front-end circuit. FIG. 4B is a circuit diagram showing details of the pixel front end circuit and how it is placed between the wafers/dies.

FIG. 5A is a partial longitudinal cross-sectional view of two stacked wafers showing the entire front end at the top wafer, ultimately including the source follower stage. FIG. 5B is a partial vertical cross-sectional view focused on one pixel, showing how the output from the first wafer is transmitted to the event detector on the bottom wafer (located between the first and second metals from the top). A direct connection can be made to one of the plates of a MIM (metal-insulator-metal structure) capacitor. This is a simplified longitudinal cross-sectional view including details regarding the silicon processing layers for two stacked wafers. 5C and 5D are circuit diagrams showing details of the pixel front end circuit. 5C and 5D are circuit diagrams showing details of the pixel front end circuit.

FIG. 6A is a circuit diagram illustrating another pixel front end circuit that includes additional p-FETs to improve performance. FIG. 6B is a circuit diagram illustrating wafer/die separation.

7A-7C are circuit diagrams illustrating various pixel front end circuits that require multiple Cu--Cu junctions in every pixel. FIG. 7A shows a preferred example. Figures 7B and 7C show how circuit components can be placed between the wafers/die such that the top wafer does not contain p-FET devices, and in this case how can three per pixel be used? Indicates whether more connections between wafers (or dies) are required. Figures 7B and 7C show how circuit components can be placed between the wafers/die such that the top wafer does not contain p-FET devices, and in this case how can three per pixel be used? Indicates whether more connections between wafers (or dies) are required.

The invention will now be described in detail with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. However, this invention may be embodied in a variety of different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments may be embodied in a variety of different forms and should not be construed as limited to the embodiments set forth herein; It is provided that this disclosure will be complete and complete, and will fully convey the scope of the invention to those skilled in the art.

As used herein, the term "and/or" includes any or all combinations of one or more of the associated listed items. Additionally, the singular forms and articles "a," "an," and "the" are intended to include plural forms unless clearly stated otherwise. Also, when the terms "includes" and "comprises" are used in this specification, they refer to the features, integers, steps, acts, elements, and/or components mentioned. It is understood that defining the existence does not exclude the presence or addition of one or more other features, integers, steps, acts, elements, components, and/or collections thereof. Also, when elements, including components or subsystems, are referred to or illustrated as being connected or coupled to other elements, they may be directly connected or joined or there may be intervening elements. It is understood that it is also good.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Furthermore, terms as defined in commonly used dictionaries should be construed as having meanings similar to their meaning in the context of the relevant art and are not expressly defined herein. It is understood that the invention is not to be construed in any idealized or overly formal sense.

definition

An Event-Based Pixel Array (EBPA) is an array of pixels with photosensitive devices. These pixels are each spatially and/or temporally independent and generate discretized data in response to the light radiation they receive.

An event-based vision sensor (EBVS) is a sensor that outputs data extracted and/or constructed from an EBPA.

Fill-factor (FF) is defined as the ratio of the area of a pixel to the area of the photosensitive device within the pixel. This is a measure of how much of the total light radiation reaching the surface of the sensor is efficiently received by the sensor.

Quantum efficiency (QE) is defined as the ratio between the number of photons that reach the surface of a photosensitive sensor and the number of electrons that are correspondingly generated and converted into an electrical signal.

3D IC is an acronym for Three-Dimensional Integrated Circuit, a technology that manufactures integrated circuits by stacking silicon wafers or dies and vertically interconnecting them.

Front-Side Illumination (FSI) is a type of image sensor that is implemented as an integrated circuit (IC) such that light enters from the top of the die, which is the side on which the planar process layers are implemented. All devices and metal interconnects, along with photosensitive devices, receive direct optical radiation.

Back-Side Illumination (BSI) is a type of image sensor that is implemented as an IC so that light enters from the bottom of the die, which is the substrate side. The devices and metal interconnects do not receive optical radiation directly, but only through the substrate.

Conventional technology

Examples of event-based vision sensors include, for example, PCT/IB2017/058526, US7728269B2, U. S. Pub. No. It is described in 2018/0191972.

FIG. 1 shows an example of an EBPA pixel structure of EBVS used as a reference in this specification. This is based on PCT/IB2017/058526 and U. S. Pub. No. 2018/0191972, which are incorporated herein by reference. However, the main concepts of the invention can be applied to virtually any event-based vision sensor implemented as an IC, independent of the particular pixel structure used.

The main components of the pixel circuit are listed below.

1. Photoreceptor module. As shown in the figure, the pixel circuit 100 includes a photodiode PD or other photosensor for measuring the impinging light and converting the light intensity into a current Iphoto, and a photoreceptor signal Vpr that is dependent on the light intensity. photoreceptor circuit PRC, and a memory capacitor C1 for storing past photoreceptor signals. The photosensor PD and the photoreceptor circuit PRC constitute a photoreceptor module PR.

2. Memory capacitor C1: receives photoreceptor signal Vpr, and thus receives photoreceptor signal Vpr such that the first plate of the capacitor is charged in accordance with the light received by photosensor PD. Memory capacitor C1 is part of event detector ED. The second plate of memory capacitor C1 is connected to the comparator node (inverting input) of A1. Therefore, the voltage Vdiff at the comparator node varies with changes in the photoreceptor signal Vpr.

3. Comparator A1: This is a means for comparing the difference between the current photoreceptor signal Vpr and the past photoreceptor signal with a threshold value. Comparator A1 is part of event detector ED. This comparator A1 may be in each pixel or may be shared between a subset of pixels (eg, a pixel column). In a preferred embodiment, the comparators are integral to the pixels, with each pixel having its own dedicated comparator A1.

4. Memory: Memory 50 stores comparator outputs based on sample signals from controller 60. Memory 50 is part of event detector ED. The memory can be sampling circuits (eg, switches and parasitic or explicit capacitors) or digital memory circuits (latches or flip-flops). In some embodiments, the memories are sampling circuits, and each pixel has two memories.

5. Conditional Reset Circuit R1: The condition for reset is the combination of the stored state of the comparator output and the reset signal applied by controller 60. Conditional reset circuit R1 is part of event detector ED.

6. Peripheral circuit components: Comparator A1 and memory 50 can be located in the pixel or in the peripheral circuit (external to the pixel circuit).

The peripheral circuitry includes a controller 60 that applies a threshold signal to comparator A1, sends a control signal to memory 50, and selects the times at which conditional reset circuit R1 is active.

The peripheral circuitry may also include readout circuitry. The readout circuit reads the contents of memory 50 and determines whether the light intensity for a given pixel has increased, decreased, or remained unchanged (calculated from the current memory value). Send output to processor.

More specifically, the comparator tells whether the light has increased and/or decreased. For an Off event: if Vdiff is less than the threshold Voff (above Vb), the comparator output is high and this level is stored in memory. This means that a decrease is detected. If Vdiff is not below the threshold, the comparator output will be low. That is, no decrease is detected.

The only difficulty is that for an On event, a low comparator output means an increase, while a high comparator output means no change, but for an Off event, a high comparator output means a decrease, while a low This is the point where the comparator output means no change.

Therefore, when reading, it is necessary to be aware of the memory content and which threshold was applied.

Pixel circuit 100 and controller 60 operate as follows.

A change in the light intensity received by the photosensor PD is converted into a change in the photoreceptor signal Vpr. When the reset circuit R1 is not conducting, the change in Vpr is also reflected in the voltage Vdiff at the comparator node at the inverting input (-) to the comparator A1. This occurs because the voltage across memory capacitor C1 remains constant.

At a time selected by the controller 60, the comparator A1 changes the voltage at the comparator node (Vdiff) at the second terminal of the memory capacitor C1 to the non-inverting input (+) of the comparator A1 (from the controller). ) threshold voltage Vb.

Controller 60 activates memory 50 to store the comparator output Vcomp. Memory 50 is typically implemented as part of pixel circuit 100, as shown. However, in other embodiments, memory 50 is implemented as part of column logic (peripheral circuits, one for each column of the pixel array).

If the state of the storage comparator output held in the memory 50 indicates a change in light intensity and the GlobalReset signal, which is the global reset signal from the controller 60, is active, then the conditional reset circuit R1 is conducting. . Here, "AND" indicates a logical AND operator. When conditional reset circuit R1 is conductive, the voltage at the comparator node (Vdiff) at the inverting input of comparator A1 is reset to a known level. Comparator A1 therefore stores the current photoreceptor signal Vpr on memory capacitor C1.

At present, the EBVS having the EBPA of the pixel shown in FIG. 1 is manufactured as an integrated circuit on a single wafer using a silicon planar process. Using this technique, semiconductor devices (eg MOS transistors, diodes, photodiodes, polysilicon resistors, etc.) are placed only on a single layer, and vertical stacking of semiconductor devices is not possible.

For this reason, the area of pixel 100 needs to be shared between the photosensitive device (eg PD) and other elements of the circuit. In this regard, FIG. 2A shows a front-illuminated structure, FIG. 2B shows a back-illuminated structure, and in particular FIG. 2C shows a top view. This means that the photodetector PD cannot use all the light that reaches the surface. Although this problem can be alleviated by using a layer of microlenses, the surface of the sensor will always have a portion that absorbs the optical radiation without converting it into a useful electrical signal.

Also, light reaching non-photosensitive devices can have undesired effects. This is because some of the characteristics of the non-photosensitive device may change due to the light impinging on the non-photosensitive device. For example, a MOS transistor includes several semiconductor pn junctions. Typically, semiconductor pn junctions trap photogenerated carriers and generate unwanted signals in response.

A more advanced process technique called back-side illumination (BSI) allows for improved utilization of the available area by exposing the back side of the wafer or die, which is the side of the silicon substrate. In this way, the flexibility of wiring metal connections that can be located above the photosensitive device within the pixel can be increased, while in front-side illumination (FSI) technology, the photosensitive device The light must be exposed toward the top of the wafer, so no metal can be placed on top of the photosensitive device to maximize the captured light. The present invention is superior to both BSI and FSI approaches that are implemented on a single wafer or die.

As is well known, event-based vision sensors are based on pixel arrays. The pixels generate data depending on the light that reaches them. Each pixel is spatially and/or temporally independent.

Each pixel includes circuitry. This circuit is divided into a photosensitive part (for example, photodiode PD) and a non-photosensitive part (for example, photoreceptor circuit PRC, capacitor C1, comparator A1, memory 50, and reset circuit R1). The non-photosensitive portion biases the photosensitive circuitry, receives the signal generated in response to the light, and often performs a first signal conditioning or refinement. Examples of such types of pixels have been described above (as prior art).

Typically, such sensors are manufactured as silicon integrated circuits (ICs) based on planar processes. This means that the photosensitive part of the pixel and the rest of the circuitry need to be realized using a single layer semiconductor device. As a result, a portion of the area of the pixel is occupied by non-photosensitive circuitry, which substantially reduces the fill factor of the pixel (see FIGS. 2A, 2B, and 2C). Therefore, the quantum efficiency also decreases. The same is true for back side illuminated (BSI) ICs that are fabricated on a single wafer or die.

In the present invention, the fill factor of the pixels of an event-based vision sensor can be maximized by stacking multiple wafers or dies using a technique known as three-dimensional integration (3DIC).

Since the photosensitive device can be stacked on non-photosensitive parts of the circuit, the above technique allows pixel circuitry to be separated between different wafers or dies, maximizing the area of the photosensitive device. . Additionally, circuits located on wafers below the top wafer do not receive any (or most) optical radiation captured by the top wafer, allowing for a significant reduction in undesirable behavior in non-photosensitive circuits due to impinging light. Make it.

Another advantage of this approach is that two wafers or dies can be manufactured using two different technology processes. This allows selecting the best available process for both the photosensitive device and the rest of the circuitry. The technical requirements for these two types of circuits often do not overlap completely.

Examples of embodiments

3A to 3C illustrate a first embodiment (preferred embodiment) of the invention. 3A and 3B show longitudinal cross-sectional views of an EBVS IC. FIG. 3A illustrates two stacked wafers (or dies). Connections to the bottom wafer (wafer 2) are provided as wire bond pads 210 located on the top surface of the top wafer (wafer 1). Electrical connections are made through the body of the top wafer (wafer 1) by using through-silicon vias (TSV). The end of the TSV is a Cu--Cu junction CC such as a copper ball bump. In this way, the electric circuits on the bottom surface of the top wafer and the top surface of the bottom wafer (wafer 2) are electrically connected.

Note that in this specification, die and wafer are used interchangeably. Generally, a "die" means a part of a semiconductor wafer, and usually has a rectangular shape such as a chip. Here, the portion of the semiconductor wafer includes a portion of an example integrated circuit device, such as an event-based vision sensor. Reference to wafer or die is based on the possibility of different manufacturing techniques. Lamination can be done at the wafer level before dicing into die. Alternatively, the individual dies may be laminated after the dies are cut out from the wafer (dicing is performed). In any case, the final unified device, or EBVS, resulting from this manufacturing process will be a stack of multiple dies.

FIG. 3B shows details of a vertical cross-sectional view of an EBVS pixel. This shows how the light impinges only on the surface of the top wafer (wafer 1) on the substrate side (BSI) and how this wafer only contains photosensitive devices, photodiodes PD. . For this reason, one Cu-Cu junction CC is used for each pixel to connect to the bottom wafer (or die). A non-photosensitive part of a pixel circuit, for example, a comparator A1, is mounted on the bottom wafer (wafer 2).

FIG. 3C shows a pixel circuit diagram. Examples of this are PCT/IB2017/058526 and U. S. Pub. No. Although reference is made to the pixel circuit described in 2018/0191972 and FIG. 1, event detection pixels with a different structure may be used. This illustrates how circuits are distributed between two wafers (or dies). Only the photodiode PD is mounted on the top wafer/die (wafer 1), and the remaining pixel circuits are mounted on the bottom wafer/die. There is a Cu--Cu junction CC for every pixel. The Cu--Cu junction CC connects the photodiode and the light receiving circuit. Also shown is an event detector on wafer 2. The readout circuit RO may be installed on the wafer 2, or on another wafer or die.

FIG. 3D shows details of the photoreceptor circuit PRC mounted on the wafer 2 using a circuit diagram.

4A and 4B show other embodiments. The circuit selected for the pixel is the same as shown in FIGS. 3C and 3D, but the circuit components are arranged differently from wafer/die to wafer.

Furthermore, the partitioned wafer/die as shown in FIG. 4B allows the circuitry in the bottom wafer to be implemented entirely with p-type MOSFET devices, since the event detector can be implemented with only p-type devices. According to this method, the entire pixel region can be placed in the same n-well, so the area of the pixel can be further reduced. Typically, a minimum clearance is required between the n-type MOSFET device and the n-well (where the p-type MOSFET device is located). If there are no n-type devices and the pixels are contained in a single n-well, the area required for the pixels should be less than if both n-type and p-type devices are used for every pixel. Can be done.

As shown in FIG. 4B, the top wafer (wafer 1) includes two n-FET transistors (M1 and MA1) of the photodetector circuit PRC along with a photodiode PD. In this case, the wafer/die Cu-Cu junction CC is connected to a node that connects to the gate of feedback transistor M1 and the drain of MA1, and a node that connects to the drain of bias p-FET transistor MA2 and the input of the event detector. located between. The input of the event detector corresponds to one of the plates of capacitor C1 shown in FIG. Such an arrangement improves photodetection performance without unduly reducing fill factor or reducing top wafer complexity (effectively limiting the number of process masks required for fabrication). can be improved. This performance improves especially with respect to noise. Cu-Cu bonds typically have some resistance due to the vias and metal layers required to reach the surface of one wafer and the devices on the other wafer. This resistance creates thermal noise. Furthermore, the stacked metal layers and vias are typically fabricated using different metals, and the metal bonding introduces noise. For this reason, solutions such as those shown in FIGS. 4A and 4B are beneficial. This solution sacrifices less of the area occupancy benefits initially provided by wafer/die stacking techniques. Such a solution also requires less area on the lower wafer (wafer 2) since fewer transistors are required. Therefore, the pixel size can be reduced. A further advantage of this solution (and other solutions with transistors on both wafers) is that the characteristics of the two transistors on the upper wafer can be compared to the characteristics of the transistors on the lower wafer (wafer 2). can be optimized independently.

A third embodiment is shown in FIGS. 5A to 5D. The third embodiment refers again to the circuits presented in the above embodiments, but the top wafer (wafer 1) of the third embodiment includes bias transistors of the front-end circuit. Finally, it is also possible to add a buffer stage, preferably realized as a source follower amplifier stage.

An advantage of this embodiment is that it improves the drive capability of the circuit before bonding between wafers (dies). In particular, when adding a buffer stage, the load on the output node is reduced so that the resistance of the Cu-Cu junction CC has less impact on front-end performance. In this case, the Cu-Cu junction is located between the output node of the front end and the input of the event detection circuit. As an example, the output node of the front end consists of the gate of M1, the drain of MA1, and the drain of MA2. The input of the event detection circuit corresponds to one of the plates of capacitor C1.

However, the greatest advantage of this approach relates to the fact that capacitor C1 is usually manufactured as a MIM (metal-insulator-metal construction) capacitor. This type of device is manufactured using two metal layers on top of a silicon planar process, or one metal layer ultimately below the top layer. Then, the output of the circuit mounted on the top wafer can be directly connected to the top plate of the MIM capacitor, and the size of the capacitor can be maximized. This is because the circuit on the top wafer does not need to be connected to other nodes except the top plate of the MIM capacitor C1, and can be realized by occupying the entire area of the pixel.

Therefore, this approach can greatly facilitate pixel layout and ultimately achieve smaller pixels by better distributing the devices between two wafers/dies.

This situation is shown in FIG. 5B. FIG. 5B is a schematic diagram of two stacked wafers (Wafer 1 and Wafer 2) realized in silicon planar processing technology, illustrating the various layers forming the wafers. From this it can be seen how the last metal layer of the top wafer can be directly connected to one of the plates of the MIM capacitor C1. In this specific example, the top wafer/die is arranged as a BSI (back side illuminated) configuration, so the top wafer/die receives light on the substrate side and connects to other wafers using Cu-Cu junctions CC. The two respective top metal layers of the two wafers/dies are bonded together. To simplify the drawing, the photodiode junction shown in FIG. 5 is realized as an n-well in a p-substrate, but in practice more sophisticated structures are preferred.

Figures 5C and 5D show two different circuit layouts. Specifically, FIG. 5D shows a front end that includes a buffer amplifier B (preferably a source follower amplifier).

By connecting the top wafer to the bottom wafer using TSVs (through silicon vias), an FSI (front surface illumination) approach to the top wafer can be realized.

Using this technique and using the same transistor placement between the two wafers (or dies), MIM capacitor C1 is placed on the top wafer (or die) (wafer 1) instead of the bottom wafer (or die) (wafer 2). ) can also be placed. Such an approach can be justified by making specific considerations regarding metal layers, e.g., distributing metal layers between wafers (or dies) according to the most cost-effective solution. can. The two wafers can be realized with two different technologies. One of these technology processes allows the addition of metal layers or MIM-specific metal layers at a lower cost than other processes.

In all wafer examples presented herein, additional layers implementing microlenses and/or optical waveguides can be stacked on the exposure side, which can improve the QE of the photoreceptor. , the microlens and/or the optical waveguide are not shown to simplify the drawing.

In FIG. 6A, another embodiment of a pixel front end is shown. Again, only one inter-wafer (or die) connection is required per pixel. The top wafer (wafer 1) includes transistors that, together with photodiodes PD, constitute a pixel front end that includes a photoreceptor circuit PRC.

FIG. 6B shows how amplifier stage B (preferably realized as a source follower amplifier) can be added in the end and how to include amplifier stage B in the top wafer (wafer 1). It shows what you can do. This has the advantage of increasing the drive capability of the front end and effectively limiting the load on the front end output nodes (gate of M1, drain of MA1, and drain of MA2). In fact, the Cu-Cu junction CC may have a non-negligible resistance that would directly load the output of the front end if there were no amplifier stage.

FIG. 7A shows a pixel front end circuit similar to that shown in FIG. 5B. The amplifier stage of FIG. 7A is specified as a source-follower amplifier implemented with n-FET MOS devices. The solution proposed here does not include p-FET devices in the top wafer, so the number of inter-wafer (or die) connections required is greater than one. Here, in particular, there are two connections for one pixel.

The choice of not having p-FET MOS devices in the top wafer has the advantage of improving QE. This means that if an n-well is present in the irradiated wafer, this n-well will attract the carriers generated by the impinging light and act as a parasitic photodiode connected between the supply voltage and ground. Because it does.

FIG. 7C shows another embodiment of a pixel front end, which is similar to that shown in FIG. 6B. In this embodiment, as in FIG. 7A, the top wafer being illuminated does not contain p-FET MOS devices, thus requiring multiple inter-wafer (or die) connections per pixel. This embodiment requires four connections per pixel. The buffer stage is implemented as a source follower amplifier consisting of n-FET devices.

In FIG. 7C, the same pixel structure as used in FIG. 7B is shown, but the source follower amplifier acting as a buffer is realized by a p-FET MOS device. In this way, one connection per pixel can be omitted, and the number of connections required is only three.

In general, many different methods of partitioning pixel circuits are available, all with their own advantages and disadvantages. For example, if your focus is on finding the best technology for each part of your circuit, you might want to separate the digital and analog parts of your circuit. Also, the use of Cu-Cu junctions and TSVs, for example, eliminates the theoretical limits imposed on the number of wafers/dies that can be stacked and vertically connected by stacking techniques. Such connections can be placed within every pixel or at the edges of the pixel array. For example, one connection is arranged per column and/or row.

While the present invention has been particularly illustrated and described with reference to preferred embodiments thereof, it is apparent to those skilled in the art that the present invention does not depart from the scope of the invention as encompassed by the appended claims. It will be understood that various changes may be made in the form and details of the invention.

Claims (7)

An event-based vision sensor comprising a stacked first die and a second die, the sensor comprising:
A photodiode for each pixel of a pixel array is arranged on the first die,
An event detector for each pixel of the pixel array and a photoreceptor circuit that generates a photoreceptor signal dependent on light intensity and inputs it to the event detector are disposed on the second die,
The photoreceptor circuit is composed of a plurality of transistors,
The event detector includes a memory capacitor, a comparator, and a memory;
The memory capacitor is constituted by an MIM (metal-insulator-metal structure) capacitor, a first plate of the MIM capacitor is connected to a photoreceptor signal generated by the photoreceptor circuit, and a second plate of the MIM capacitor is connected to a photoreceptor signal generated by the photoreceptor circuit. a plate of is connected to one input of the comparator, the other input of the comparator being connected to a threshold signal applied by a controller;
the output of the comparator is configured to be stored in the memory;
Event-based vision sensor. The event-based vision sensor according to claim 1,
The conditional reset circuit is connected between the second plate of the MIM capacitor and one input of the comparator, and the conditional reset circuit is connected to the output of the comparator stored in the memory. configured to switch the conduction state based on combination with a reset signal applied by the controller;
Event-based vision sensor. The event-based vision sensor according to claim 1,
The first die has a back-illuminated structure in which the wiring layer is arranged on the opposite side of the light incident surface. The event-based vision sensor. The event-based vision sensor according to claim 1,
The first die and the second die are connected to each other using a Cu-Cu junction. The event-based vision sensor according to claim 1,
The first die and/or the second die include stacked dies, and the stacked dies have through-silicon via connections. The event-based vision sensor according to claim 1,
The photoreceptor circuit includes an n-FET transistor and a p-FET transistor. Event-based vision sensor. The event-based vision sensor according to claim 1,
The photoreceptor circuit includes two n-FET transistors and a p-FET transistor. Event-based vision sensor.

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