JP2021129188A - Semiconductor device, and system and analog-digital converter including semiconductor device - Google Patents

Abstract

To provide a semiconductor device with low consumption power and smaller area, and a system and an analog-digital converter including the semiconductor device.SOLUTION: According to one embodiment, a semiconductor device includes an initial-stage modulator SDM1 including a quantizer QT1 and receiving the input of an external input signal that is an analog signal, a next-stage modulator SDM2 including a quantizer QT2 and connected to a subsequent stage of the initial-stage modulator SDM1, a probe signal generation circuit XG that injects a probe signal to the initial-stage modulator SDM1, an adjustment filter CF1 that adjusts the frequency characteristic of an output signal of the quantizer QT1, an adjustment filter CF2 that adjusts the frequency characteristic of an output signal of the quantizer QT2, an adaptive filter AF1 that searches for a transmission function of the initial-stage modulator SDM1, an adaptive filter AF2 that searches for a transmission function of the next-stage modulator SDM2, and a noise canceling circuit CCN1 that cancels the quantization error using the search results of the adaptive filter AF1 and the adaptive filter AF2.SELECTED DRAWING: Figure 6

Description

The present invention relates to semiconductor devices, systems using semiconductor devices, and analog-to-digital converters.

For example, a millimeter-wave radar system for in-vehicle use requires a high-resolution, wide-signal band, and robust analog-to-digital converter. As an analog-to-digital converter that satisfies such a requirement, a MASH type (cascade type) sigma-delta (ΣΔ) analog-digital converter (also called a delta-sigma (ΔΣ) ADC) is known.

Patent Document 1 describes a MASH type ΣΔ analog-to-digital converter. The ΣΔ analog-to-digital converter of Patent Document 1 includes first and second modulators, a probe signal generation circuit, first and second adaptive filters, and a noise canceling circuit.

In the ΣΔ analog-digital converter of Patent Document 1, the first modulator is a first analog integrator composed of an analog circuit and a first quantum that quantizes the output signal of the first analog integrator. An external input signal that becomes an analog signal including an integrator is input. The second modulator is coupled after the first modulator and includes a second quantizer. Then, the first adaptive filter searches for the transfer function of the first modulator by observing the output signal of the first quantizer corresponding to the probe signal, and the second adaptive filter uses the probe signal. The transfer function of the second modulator is searched by observing the output signal of the second modulator corresponding to the signal. The noise canceling circuit cancels the quantization error caused by the first quantizer by using the search results of the first and second adaptive filters.

Japanese Unexamined Patent Publication No. 2018-182610

In Patent Document 1, the frequency characteristic of the digital filter can be matched with the frequency characteristic of the analog transfer function by the transfer function search technique. Thereby, the characteristics required for the analog integrators constituting the first and second modulators can be relaxed. Therefore, the power consumption required for the first and second modulators can be suppressed.

However, when imperfections such as variations in the RC elements of the analog integrators constituting the first and second modulators, insufficient amplifier gain, and insufficient bandwidth become large, the transfer function H _1D (f) of the first modulator becomes large. And the scale of the digital filter coefficient for accurately expressing the transfer function H _{2D (f) of the second modulator is greatly increased.} Therefore, the power consumption of the digital unit increases more than the power consumption of the analog integrator is reduced, and the area of the circuit constituting the ΣΔ analog-digital converter also increases significantly.

Other challenges and novel features will become apparent from the description and accompanying drawings herein.

According to one embodiment, the semiconductor device includes a first loop filter having a first analog integrator composed of an analog circuit and a first quantizer for quantizing the output signal of the first loop filter. A probe to the first modulator, which includes an external input signal to be an analog signal, a second modulator which is connected to the subsequent stage of the first modulator and includes a second quantizer, and the first modulator. A probe signal generation circuit that injects a signal, a first adjustment filter that adjusts the frequency characteristics of the output signal of the first quantizer, and a second adjustment filter that adjusts the frequency characteristics of the output signal of the second quantizer. The first adaptive filter for searching the transfer function of the first modulator by observing the output signal of the first quantizer corresponding to the probe signal through the first adjustment filter, and the probe. The second adaptive filter for searching the transfer function of the second modulator by observing the output signal of the second quantizer corresponding to the signal through the second adjustment filter, and the first adaptive filter. It is provided with a noise canceling circuit that cancels the quantization error generated in the first quantizer by using the search result and the search result of the second adaptive filter.

According to the above-described embodiment, it is possible to provide a semiconductor device that realizes low power consumption and a small area, a system using the semiconductor device, and an analog / digital converter.

It is a block diagram which illustrated the ADC which concerns on Comparative Example 1. FIG. It is a block diagram exemplifying the first stage modulator in the ADC which concerns on Comparative Example 1. FIG. It is a block diagram which illustrated the next-stage modulator in the ADC which concerns on Comparative Example 1. FIG. It is a block diagram which illustrated the ADC which concerns on Comparative Example 2. FIG. It is a block diagram exemplifying the first stage modulator in the ADC which concerns on Comparative Example 2. FIG. It is a block diagram which illustrated the ADC which concerns on Embodiment 1. FIG. In the ADC according to the first embodiment, it is a graph exemplifying the transfer characteristics of the quantization error in the output of the first stage modulator with and without the adjustment filter, the horizontal axis shows the frequency, and the vertical axis shows the transmission characteristics. Is shown. In the ADC according to the first embodiment, it is a graph exemplifying the transfer characteristics of the quantization error in the output of the next-stage modulator with and without the adjustment filter, the horizontal axis represents the frequency, and the vertical axis represents the transmission. Shows the characteristics. In the ADC according to the first embodiment, _{it is a graph exemplifying the coefficient sequence of the transmission characteristic H 1D} with and without the adjustment filter, the horizontal axis shows the coefficient number, and the vertical axis shows the coefficient value. In the ADC according to the first embodiment, _{it is a graph exemplifying the coefficient sequence of the transmission characteristic H 2D} with and without the adjustment filter, the horizontal axis shows the coefficient number, and the vertical axis shows the coefficient value. It is a block diagram which illustrated the ADC which concerns on Embodiment 2. It is a block diagram which illustrated the ADC which concerns on Embodiment 3. It is a block diagram which illustrated the main part of the system using ADC which concerns on Embodiment 4. FIG.

In order to clarify the explanation, the following description and drawings have been omitted or simplified as appropriate. Further, in each drawing, the same elements are designated by the same reference numerals, and duplicate explanations are omitted as necessary.

The analog-to-digital converter (hereinafter, referred to as ADC) according to the first to fourth embodiments will be described. First, before explaining the ADCs of the first to fourth embodiments, the ADCs according to Comparative Examples 1 and 2 and their problems will be described. This makes the ADCs of embodiments 1 to 4 clearer.

(Comparative Example 1)
The ADC according to Comparative Example 1 will be described. The ADC of Comparative Example 1 is, for example, an ADC used in a millimeter-wave laser receiving unit. FIG. 1 is a block diagram illustrating an ADC according to Comparative Example 1. FIG. 2 is a block diagram illustrating a first-stage modulator in the ADC according to Comparative Example 1. FIG. 3 is a block diagram illustrating a next-stage modulator in the ADC according to Comparative Example 1.

As shown in FIGS. 1 to 3, the ADC 101 according to the comparative example includes a first-stage modulator SDM101, a second-stage modulator SDM102, and a noise canceling circuit CCN101. ADC101 is a MASH type ΣΔADC. ADC101 is an analog signal external input signal _{V IN,} and outputs an external output signal _{D OUT} as a digital signal.

The first-stage modulator SDM101 includes a loop filter LF1, a quantizer QT1, and a digital-to-analog conversion circuit DAC12. The loop filter LF1 includes, for example, an analog adder / subtractor AS11, an analog integrator unit INTU1, and a digital-to-analog conversion circuit DAC11. As described above, the loop filter LF1 includes an analog integrator unit INTU1 composed of an analog circuit.

In the loop filter LF1, the digital-to-analog conversion circuit DAC11 converts the digital signal output by the quantizer QT1 into an analog signal and outputs it to the analog adder / subtractor AS11. The analog adder / subtractor AS11 _{outputs a difference signal between the external input signal VIN} and the output of the digital-to-analog conversion circuit DAC11 to the analog integrator unit INTU1. Both the digital-to-analog conversion circuits DAC11 and DAC12 convert the output signal of the quantizer QT1 into an analog signal.

The quantizer QT1 quantizes the output signal of the loop filter LF1. Here, the quantizer QT1, quantization error Q ₁ is generated in such a way are added in the quantizer QT1. The quantization error Q ₁ can be extracted from the difference signal between the output signal of the digital-to-analog conversion circuit DAC12 and the output signal of the loop filter LF1.

The second-stage next-stage modulator SDM102 has a loop filter LF2 and a quantizer QT2. The loop filter LF2 includes, for example, an analog adder / subtractor AS21, an analog integrator unit INTU2, and a digital-to-analog conversion circuit DAC21. As described above, the loop filter LF2 includes an analog integrator unit INTU2 composed of an analog circuit.

In the loop filter LF2, the digital-to-analog conversion circuit DAC21 converts the digital signal output by the quantizer QT2 into an analog signal and outputs it to the analog adder / subtractor AS21. Analog adder-subtracter AS21 outputs the extracted signal of the quantization error _{Q 1} in the first stage modulator SDM101, a difference signal between the output signal of the digital-to-analog converter DAC21 to analog integrator unit INTU2.

The quantizer QT2 quantizes the output signal of the loop filter LF2. Even quantizer QT2, as in the case quantization error _{Q 2} quantizer QT1 occurs.

The noise canceling circuit CCN101 has a noise canceling filter NCF1, a noise canceling filter NCF2, and a digital adder / subtractor DAS31. The noise canceling filter _{NCF1 is a digital filter to which the output signal DSO 1} of the quantizer QT1 is input, and the noise canceling filter NCF2 is a digital filter to which the output signal DSO ₂ of the quantizer QT2 is input.

The digital filter is, for example, an FIR (Fiinite Impulse Response) filter that realizes a desired filter characteristic by a plurality of tap coefficients, an IIR (Infinite Impulse Response) filter, and the like. The digital adder / subtractor DAS31 calculates the difference between the output signal S11 of the noise canceling filter NCF1 and the output signal S12 of the noise canceling filter NCF2 (here, “S11-S12”), and uses the calculated difference as the external output signal D _OUT. Is output.

Here, as shown in FIG. 1, the transfer function H _1A (f) is referred to as " _{the transfer function from the application point of the quantization error Q 1 to the output signal DSO 1} of the first-stage modulator SDM 101 (quantizer QT 1)". Define. In the example of FIG. 1, the transfer function H _1A (f) coincides with the noise transfer function NTF ₁ of the first-stage modulator SDM101. Further, the transfer function _H 2A (f), defined as "transfer function from the application point of the quantization error _{Q 1} to the output signal DSO ₂ of the next stage modulator SDM102 (quantizer QT2)". In the example of FIG. 1, the transfer function H _2A (f) coincides with the signal transfer function (Signal Transfer Function STF ₂ ) of the next-stage modulator SDM102.

The output signal DSO ₁ of the modulator SDM101 is "V _IN L _1A + Q ₁ H _1A ". Here, L _1A is, for example, the signal transfer function STF ₁ of the first-stage modulator SDM 101. Output signal DSO ₂ of the next stage modulator SDM102 is _{"Q 1 · H 2A + Q 2} · L 2A ". Here, L _2A is the noise transfer function NTF ₂ of the next-stage modulator SDM102. The transfer function H _2D (f) of the noise canceling filter NCF1 is set in advance in the transfer function H _2A (f), and the transfer function H _1D (f) of the noise canceling filter NCF2 is previously set in the transfer function H _1A (f). Set.

Therefore, the output signal S11 of _{the noise canceling filter NCF1 becomes "VIN} · L _1A · H _2A + Q ₁ · H _1A · H _2A ", and the output signal S12 of the noise canceling filter NCF2 becomes "Q ₁ · H _2A · H". the _{1A + Q 2 · L 2A ·} H 1A ".

As a result, in the external output signal D _OUT , the external input signal V _IN is delayed by the order of "STF ₁ · H _2A (f)" (that is, the total integral order of the analog integrator units INTU1 and INTU2). It is output. Further, the quantization error Q ₁ is canceled. Further, the quantization error Q ₂ is reduced by noise shaping for the order of "NTF ₂ · H _1A (f)" (total integration order).

For example, in a millimeter wave radar system or the like, input noise of a high frequency component may occur. The MASH (Multi-stAge noise-Shaping) type ΣΔADC can operate more stably even if a high frequency component is included in the _{external input signal VIN as} compared with the non-MASH type (single loop type) sigma delta ADC. That is, in general, in order to increase the resolution of ΣΔADC, it is necessary to increase the order of the integrator. For example, in the case of realizing the fourth order with the MASH type ΣΔADC of FIG. 1, each of the analog integrator units INTU1 and INTU2 may be configured with a second order integrator. On the other hand, in the non-MASH type, a fourth-order integrator is required in a single loop, and as a result, the loop operation tends to become unstable when _{the external input signal VIN contains a high frequency component.}

For example, in the case of using the fourth-order MASH type ΣΔADC the quantization error Q ₂ is is reduced to a level that can adequately ignored by fourth-order component of the noise shaping. Therefore, the MASH-type?? ADC, as far as possible cancel the quantization error _{Q 1,} attained the high resolution and the like. However, if the cancellation of the quantization error Q ₁ is insufficient, the resolution is lowered due to the remaining quantization error Q _1. In the actual analog integrator units INTU1 and INTU2, various characteristic variations can occur with reference to a certain ideal state. Factors of characteristic variation include manufacturing variation of RC (resistor / capacitor) elements, insufficient gain of operational amplifier, insufficient band, etc. in the case of continuous time type integrator.

As a result, "H _1A (f) · Q _{1 " in the output signal DSO 1} of the first-stage modulator SDM 101 in FIG. 1 actually becomes “H _{1A_R} (f) · Q ₁ ”. The transfer function H _{1A_R} (f) is the actual transfer function for the _{ideal transfer function H 1A (f).} Similarly, the “H _2A (f) · Q _{1 ” in the output signal DSO 2} of the next-stage modulator SDM 102 in FIG. 1 is actually “H _{2A_R} (f) · Q ₁ ”. The transfer function H _{2A_R} (f) is the actual transfer function for the _{ideal transfer function H 2A (f).} On the other hand, the transfer functions H _2D (f) and H _1D (f) of the noise canceling filters NCF1 and NCF2 are the ideal transfer functions H _2A (f) and H _1A (f) set in advance. As a result, the cancellation of the quantization error Q ₁ in the external output signal D _OUT becomes insufficient.

(Comparative Example 2)
Next, the ADC according to Comparative Example 2 will be described. FIG. 4 is a block diagram illustrating the ADC according to Comparative Example 2. FIG. 5 is a block diagram illustrating a first-stage modulator in the ADC according to Comparative Example 2. As shown in FIGS. 4 and 5, the ADC 102 according to Comparative Example 2 includes a first-stage regulator SDM1, a second-stage regulator SDM2, a noise canceling circuit CCN102, and a calibration circuit. That is, in addition to the configuration of the ADC 101 according to Comparative Example 1 described above, a calibration circuit is provided. The calibration circuit includes a probe signal generation circuit XG and a plurality of (here, two) adaptive filters AF1 and AF2. The adaptive filter AF1 includes a shift register SR1 and a search unit TS1. The adaptive filter AF2 includes a shift register SR2 and a search unit TS2.

The first-stage modulator SDM1 includes a loop filter LF1, a quantizer QT1, and a digital-to-analog conversion circuit DAC12. The loop filter LF1 includes, for example, an analog adder / subtractor AS11, an analog integrator unit INTU1, and a DAC11. Unlike the first-stage modulator SDM101 of FIG. 1, the first-stage modulator SDM1 of this comparative example has an analog adder / subtractor AS12 inserted into the input of the quantizer QT1 and a digital-to-analog conversion circuit DAC13 coupled to the input. Be prepared.

On the other hand, the configuration of the next-stage modulator SDM2 is the same as that of the next-stage modulator SDM102 of FIG. 1, and includes a loop filter LF2 and a quantizer QT2. The loop filter LF2 includes, for example, an analog adder / subtractor AS21, an analog integrator unit INTU2, and a digital-to-analog conversion circuit DAC21.

The probe signal generation circuit XG generates the probe signal X _PRN . The probe signal X _PRN is, for example, a pseudo-random signal, preferably a 1-bit (binary) pseudo-random signal. The probe signal X _PRN is input to the first-stage modulator SDM1. For example, the probe signal X _PRN is converted into an analog signal via the DAC 13, and then injected into the input signal of the quantizer QT1 via the analog adder / subtractor AS12. The probe signal X _PRN is also input to the adaptive filters AF1 and AF2 as digital signals.

The adaptive filter AF1 searches for the actual transfer function of the first-stage modulator SDM1 by observing _{the output signal DSO 1} of the first-stage modulator SDM1 (quantifier QT1) in response to _{the probe signal X PRN.} Specifically, the shift register SR1 generates a large number of probe signals z− ^k · X _{PRN for coefficient search according to the injected probe signal X PRN.} Here, the shift register SR1 changes k from 0 to K (K> 100). As a result, the search unit TS1 searches for the tap coefficient to be searched by using the plurality of coefficient search probe signals generated by the shift register SR1. Specifically, the search unit TS1 uses each coefficient to indicate the noise transfer function NTF ₁ of the _{first-stage modulator SDM1 in which the transfer function H 1D (f) of the noise canceling filter NCF 2 includes imperfections in analog characteristics.} Search for a transfer function coefficient that is equal to H _{1A_R (f).}

For example, the adaptive filter AF1 _{calculates an error between the output signal DSO 1 of} the first-stage modulator SDM1 (quantizer QT1) corresponding to _{the probe signal X PRN} and the output signal of the adaptive filter AF1, and the error resulting from the calculation. Generate a signal. The adaptive filter AF1 searches for the filter coefficient (tap coefficient) of the adaptive filter AF1 itself by using the LMS (Least Mean Square) algorithm based on the _{probe signal X PRN and the error signal.}

At this time, since the injection point of the probe signal X _{PRN and the application point of the quantization error Q 1 are substantially the same in the output signal DSO 1} , the actual transfer function H _{1A_R} (f) with respect to the above-mentioned quantization error Q _{1 ) Is} used to include the component of "H 1A_R (f) · X _PRN". The output signal of the adaptive filter AF1 is "H _1D (f) · X _PRN ". Strictly speaking, the output signal DSO ₁ also includes a component of the quantization error Q _{1 and} a component of the external input signal _VIN. However, components of the quantization error Q ₁ and the external input signal V _IN can be ignored in terms of the input signal to the adaptive filter AF1. The adaptive filter AF1 searches for a tap coefficient that minimizes the error between the _{output signal DSO 1 and the output signal of the adaptive filter AF1.} As a result, the transfer function H _1D (f) of _{the adaptive filter AF1 converges to the transfer function H 1A_R} (f).

Similarly, adaptive filters AF2, by observing the output signals DSO ₂ of the next stage modulator SDM2 corresponding to the probe signal _{X PRN} (quantizer QT2), searches the actual transfer function of the next modulator SDM2 .. Specifically, the shift register SR2 generates a large number of probe signals z− ^k · X _{PRN for coefficient search according to the injected probe signal X PRN.} Here, the shift register SR2 changes k from 0 to K (K> 100). As a result, the search unit TS2 searches for the tap coefficient to be searched by using the plurality of coefficient search probe signals generated by the shift register SR2. Specifically, the search unit TS2 uses each coefficient to _{indicate the noise transfer function NTF 2} of the first-stage modulator SDM2 in which _{the transfer function H 2D (f) of the noise canceling filter NCF 1 includes imperfections in analog characteristics.} Search for a transfer function coefficient that is equal to H _{2A_R (f).}

For example, the applied filter AF2 _{calculates an error between the output signal DSO 2 of} the first-stage modulator SDM2 (quantizer QT2) corresponding to _{the probe signal X PRN} and the output signal of the adaptive filter AF2, and the error resulting from the calculation. Generate a signal. The adaptive filter AF2 searches for the filter coefficient (tap coefficient) of the adaptive filter AF2 itself by using the LMS (Least Mean Square) algorithm based on the _{probe signal X PRN and the error signal.}

At this time, since the injection point of the probe signal X _{PRN and the application point of the quantization error Q 1 are substantially the same in the output signal DSO 2} , the actual transfer function H _{2A_R} (f) with respect to the above-mentioned quantization error Q _{1 ) Is} used to include the component of "H 2A_R (f) · X _PRN". The applied filter AF2 output signal S is “H _2D (f) · X _PRN ”. Strictly speaking, the output signal DSO ₂ also includes a component of the quantization error Q _{1 and} a component of the quantization error Q _2. However, components of the quantization error Q ₁ and the quantization error Q ₂ is can be ignored in terms of the input signal to the adaptive filter AF2. The adaptive filter AF2 searches for a tap coefficient that minimizes the error between the _{output signal DSO 2 and the output signal of the applied filter AF2.} As a result, the transfer function H _2D (f) of _{the adaptive filter AF2 converges to the transfer function H 2A_R} (f).

The digital adder / subtractor DAS31 is the same as in the case of FIG. The configurations of the noise canceling filters NCF1 and NCF2 are also the same as those of the noise canceling filters NCF1 and NCF2 of FIG. However, unlike the case of FIG. 1, the noise canceling filter NCF1 has a tap coefficient (that is, the transfer function H _{2A_R} (f)) based on the search result of the adaptive filter AF2, and the noise canceling filter NCF2 has the search result of the adaptive filter AF1. It has a tap coefficient based on (that is, a transfer function H _{1A_R} (f)).

Thus, the external output signal D _OUT, it is possible to cancel the quantization error Q _1. Further, since the probe signal X _{PRN is} also transmitted along the same route as the quantization error Q ₁ , it is canceled at the _{external output signal D OUT.} As a result, the external output signal D _OUT, as described in FIG. 1, the component of the external input signal V _IN, will include a noise-shaped component of the quantization error Q _2. The probe signal X _PRN is defined as a 1-bit (binary value) digital signal such as ± 0.1, and the digital-to-analog conversion circuit DAC13 sets the probe signal X _{PRN as a reference voltage as V ref} . Convert to a voltage signal such as "± 0.1 x V _{ref (V)".} Further, the injection of the probe signal X _PRN can be performed in parallel with the A / D conversion process of the external input signal SI (that is, in the background).

As described above, in Comparative Example 2, the injected 1-bit random probe signal X _PRN is used as a probe, and in the adaptive filter AF1, the transfer function H _1D (f) of the noise canceling filter NCF 2 determines the imperfections of the analog characteristics. The transfer function coefficient is searched so as to be equal to H _{1A_R (f) indicating the noise transfer function NTF 1} of the first-stage modulator SDM1 including the noise transfer function NTF 1. Further, in the adaptive filter AF2, the transfer function H _{2D (f) of the noise canceling filter NCF1} is equal to _{H 2A_R (f) indicating the signal transfer function STF 2} of the next-stage modulator SDM2, which also includes imperfections in analog characteristics. Search for the transfer function coefficient so that Specifically, the search units ST1 and TS2 search for the transfer function coefficients _{of the filters H 1D} (f) and H _{2D (f).}

_{H 1A_R} (f) / H _{2A_R} (f) fluctuates strongly depending on the characteristic fluctuations of the analog integrator units INTU1 and INTU2 in the first-stage modulator SDM1 and the second-stage modulator SDM2. , It is possible to match the frequency characteristics of the digital filter well with the frequency characteristics of the analog transfer function. As a result, it is practically possible to relax the characteristic requirements for the analog integrator (tolerance of imperfections), which leads to a reduction in power consumption.

However, in Comparative Example 2, when the imperfections of the analog integrator units INTU1 and INTU2 (for example, RC element variation, amplifier gain and band shortage) become large, the logical scale required for calibration increases. Specifically, the scale of the digital filter coefficient for accurately expressing _{H 1D} (f) / H _{2D (f) is greatly increased.}

That is, as shown in FIG. 4, 100 or more filter coefficients k (k> 100) to be searched are required, and a large number of probe signals Z− ^k · X _PRN for each coefficient are generated by the shift registers SR1 and SR2. However, there is a need to search for all of them. Therefore, the power consumption of the digital unit increases more than the power consumption of the analog unit is reduced. At the same time, the area will increase significantly. Further, when trying to realize a wide band (high speed) as MASH CT (Continuous-Time) ΔΣ ADC, the increase in power consumption of the digital unit becomes dominant, and it becomes difficult to achieve both high speed and low power.

(Embodiment 1)
Next, the ADC according to the first embodiment will be described. FIG. 6 is a block diagram illustrating the ADC according to the first embodiment. As shown in FIG. 6, the ADC1 according to the present embodiment includes a first-stage modulator SDM1, a second-stage modulator SDM2, a noise canceling circuit CCN1, a probe signal generation circuit XG, and a plurality of (two in this case) adaptive filters AF1 and AF2. , The adjustment filters CF1 and CF2 are provided.

Compared to the ADC 102 of Comparative Example 2, the ADC 1 of the present embodiment further includes adjustment filters CF1 and CF2 for adjusting frequency characteristics. ADC1 is a MASH type ΣΔADC. The ADC1 is input with an external input signal _VIN which is an analog signal, and outputs an external output signal D _OUT which is a digital signal. For example, ADC1 may be formed on a semiconductor substrate as a semiconductor device.

The first-stage modulator SDM1 has the same configuration as the first-stage modulator SDM1 of Comparative Example 2. The first-stage modulator SDM1 includes a loop filter LF1 having an analog integrator unit INTU1 composed of an analog circuit, and a quantizer QT1 for quantizing the output signal of the loop filter LF1. An external input signal to be an analog signal is input to the first-stage modulator SDM1. Quantization error _{Q 1} occurring in the quantizer QT1 of the first-stage modulator SDM1 is taken from the output and input of the quantizer QT1 loop filter LF1.

The next-stage modulator SDM2 has the same configuration as the next-stage modulator SDM202 of Comparative Example 2. The next-stage modulator SDM2 is connected to the subsequent stage of the first-stage modulator SDM1. The next stage modulator SDM2 includes a loop filter LF2 including a plurality of analog integrator units and a quantizer QT2. The next stage modulator SDM2, quantization error _{Q 1} is inputted.

The adjustment filter CF1 is connected to the output of the quantizer QT1 in the first-stage modulator SDM1. _{The output signal DSO 1} output from the quantizer QT1 is input to the adjustment filter CF1. The adjustment filter CF1 adjusts the frequency characteristics _{of the output signal DSO 1 of the quantizer QT1.} For example, the adjustment filter CF1 is a low-pass filter that allows low-frequency components to pass through. The adjustment filter CF1 is not limited to the low-pass filter, and other frequency components may be adjusted. The adjustment filter CF1 is connected to the noise canceling filter NCF1 and the search unit TS1 of the adaptive filter AF1. The adjustment filter CF1 outputs the adjusted output signal DSOF ₁ to the search unit TS1 of the noise canceling filter NCF1 and the adaptive filter AF1.

The adjustment filter CF2 is connected to the output of the quantizer QT2 in the next-stage modulator SDM2. _{The output signal DSO 2} output from the quantizer QT2 is input to the adjustment filter CF2. The adjustment filter CF2 adjusts the frequency characteristics _{of the output signal DSO 2 of the quantizer QT2.} For example, the adjustment filter CF2 is a low-pass filter that allows low-frequency components to pass through. The adjustment filter CF2 is not limited to the low-pass filter, and other frequency components may be adjusted. The adjustment filter CF2 is connected to the search unit TS2 of the noise canceling filter NCF2 and the adaptive filter AF2. The adjustment filter CF2 outputs the adjusted output signal DSOF ₂ to the search unit TS2 of the noise canceling filter NCF2 and the adaptive filter AF2.

The probe signal generation circuit XG generates the probe signal X _PRN . The probe signal generation circuit XG is connected to the first stage regulator SDM1. The probe signal generation circuit XG _{injects the generated probe signal X PRN} into the first-stage modulator SDM1. For example, as shown in FIG. 5, the probe signal X _PRN is converted into an analog signal via the DAC 13 of the first-stage modulator SDM1 and then injected into the input signal of the quantizer QT1 via the analog adder / subtractor AS12. .. Further, the probe signal generation circuit XG is connected to the adaptive filters AF1 and AF2. The probe signal generation circuit XG _{injects the generated probe signal X PRN} into the adaptive filters AF1 and AF2. The probe signal X _PRN is, for example, a pseudo-random signal as in Comparative Example 2, preferably a 1-bit (binary) pseudo-random signal.

The adaptive filter AF1 is connected to the output of the adjustment filter CF1. The adaptive filter AF1 searches for the transfer function of the first-stage modulator SDM1 by observing _{the output signal DSO 1} of the quantizer QT1 corresponding to _{the probe signal X PRN and the output signal DSOF 1} via the adjustment filter CF1. The adaptive filter AF1 has a shift register SR1 and a search unit TS1. The shift register SR1 generates a large number of probe signals z− ^j · X _{PRN for coefficient search according to the injected probe signal X PRN.} As a result, the search unit TS1 searches for the tap coefficient to be searched by using the plurality of coefficient search probe signals generated by the shift register SR1. Specifically, the search unit TS1 uses each coefficient to indicate the noise transfer function NTF ₁ of the _{first-stage modulator SDM1 in which the transfer function H 1D (f) of the noise canceling filter NCF 2 includes imperfections in analog characteristics.} Search for a transfer function coefficient that is equal to H _{1A_R (f).}

The adaptive filter AF2 is connected to the output of the adjustment filter CF2. The adaptive filter AF2 searches for the transfer function of the next-stage modulator SDM2 by observing _{the output signal DSO 2} of the quantizer QT2 according to _{the probe signal X PRN and the output signal DSOF 2} via the adjustment filter CF2. .. The adaptive filter AF2 has a shift register SR2 and a search unit TS2. The shift register SR2 generates a large number of probe signals z− ^j · X _{PRN for coefficient search according to the injected probe signal X PRN.} As a result, the search unit TS2 searches for the tap coefficient to be searched by using the plurality of coefficient search probe signals generated by the shift register SR2. Specifically, the search unit TS2 uses each coefficient to _{indicate the noise transfer function NTF 1} of the first-stage modulator SDM2 in which _{the transfer function H 2D (f) of the noise canceling filter NCF 1 includes imperfections in analog characteristics.} Search for a transfer function coefficient that is equal to H _{2A_R (f).}

The noise canceling circuit CCN1 cancels the quantization error of the ADC1. The noise canceling circuit CCN1 includes noise canceling filters NCF1 and NCF2, and a digital adder / subtractor DAS31. For example, the noise cancellation circuit CCN1 cancels the quantization error Q ₁ occurring in quantizer QT1 by using the search result of the adaptive filter AF2 and the search result of the adaptive filter AF1.

The noise canceling filter NCF1 is _{a digital filter in which the output signal DSO 1} of the quantizer QT1 is input via the adjustment filter CF1. The noise canceling filter NCF1 has a tap coefficient based on the search result of the adaptive filter AF2. The noise canceling filter NCF2 is _{a digital filter in which the output signal DSO 2} of the quantizer QT2 is input via the adjustment filter CF2. The noise canceling filter NCF2 has a tap coefficient based on the search result of the adaptive filter AF1.

The digital adder / subtractor DAS31 calculates the difference between the output signal S11 of the noise canceling filter NCF1 and the output signal S12 of the noise canceling filter NCF2. The digital adder / subtractor DAS31 outputs the calculated difference as an external output signal D _OUT .

As described above, in the ADC of the present embodiment, the adjustment filters CF1 and QT2 are added to the outputs of the first-stage regulator SDM1 and the second-stage regulator SDM2 with respect to the configuration of the ADC 102 of Comparative Example 2.

For example, in the first-stage regulator SDM1 and the second-stage regulator SDM2, if the imperfections such as the variation of RC elements in the analog integrator units INTU1 and INTU2, the amplifier gain shortage, and the band shortage become large, the characteristics in the high frequency region become excessive. It may be amplified (peaking).

Figure 7 is the ADC according to the first embodiment, a graph illustrating the transfer characteristics of the quantization error Q ₁ at the output of the first-stage modulator SDM1 cases when well no adjustment filter CF1 and CF2 is present, the horizontal axis, The frequency is shown, and the vertical axis shows the transmission characteristics. Figure 8 is the ADC according to the first embodiment, a graph illustrating the transfer characteristics of the quantization error Q ₁ at the output of the next stage modulator SDM2 cases when adjusting filter CF1 and CF2 is present as well as free, horizontal axis , The vertical axis shows the transmission characteristics. When there are no adjustment filters CF1 and CF2, it corresponds to ADC102 of Comparative Example 2.

Figure 9 is the ADC according to the first embodiment, a graph illustrating the coefficient sequence of the transfer characteristic H _1D when the case and no adjustment filter CF1 and CF2 is present, the horizontal axis represents the number of coefficients, the vertical axis Indicates a coefficient value. _{FIG. 10 is a graph illustrating a coefficient sequence of the transmission characteristics H 2D} with and without the adjustment filters CF1 and CF2 in the ADC according to the first embodiment, and the horizontal axis shows the coefficient numbers and the vertical axis shows the coefficient numbers. Indicates a coefficient value. When there are no adjustment filters CF1 and CF2, it corresponds to ADC102 of Comparative Example 2.

As shown in FIGS. 7 and 8, in the absence of the adjustment filters CF1 and CF2, the characteristics in the high frequency region are over-amplified (peaking). For example, when the frequency is 200 MHz or more, the H _1D characteristic and the H _2D characteristic are rapidly amplified. In a state where such over-amplification occurs, as shown in FIGS. 9 and 10, the digital filter coefficient for accurately expressing _{H 1D} (f) / H _{2D (f) behaves like oscillation.} .. As a result, the coefficient value has a magnitude that cannot be ignored up to a deep order. Therefore, the scale of the coefficient required for the digital filter is greatly increased. For example, the coefficient k> 100.

As a result, the logical scales of the search units TS1 and TS2 and the noise canceling filters NCF1 and 2 increase, and the area and power consumption of the digital unit become larger than those of the analog unit.

On the other hand, as shown in FIGS. 7 and 8, when the adjustment filters CF1 and CF2 are present, for example, the characteristics of the adjustment filters CF1 and CF2 can be changed to a low-pass filter to change the frequency characteristics of the transfer function. Fluctuations, especially an increase in high frequency components, can be suppressed.

Then, as shown in FIGS. 9 and 10, by suppressing the high frequency component, the _{digital filter coefficient required to express H 1D} (f) / H _2D (f) approaches 0 in a large order. Therefore, the digital filter coefficient of a large order can be omitted. Therefore, the coefficient scale can be significantly reduced. For example, the coefficient k <30 can be set. Therefore, it is possible to suppress an increase in the area of the digital unit and reduce power consumption.

(Embodiment 2)
Next, the ADC according to the second embodiment will be described. The ADC of the present embodiment is provided with a thinning block on the output side of the adjustment filters CF1 and CF2. FIG. 11 is a block diagram illustrating the ADC according to the second embodiment.

As shown in FIG. 11, the ADC2 of the present embodiment includes the first-stage modulator SDM1, the second-stage modulator SDM2, the noise canceling circuit CCN1, the probe signal generation circuit XG, a plurality of adaptive filters AF1 and AF2, and the adjustment filters CF1 and CF2. In addition, it includes a plurality of thinning blocks MB1. The plurality of thinning blocks MB1 are connected to the subsequent stages of the adjustment filter CF1 and the adjustment filter CF2. _{The thinning block MB1 reduces the data rates of the output signals DSOF 1} and DSOF ₂ whose frequency characteristics are adjusted by the adjustment filters CF1 and CF2 to a predetermined ratio. The predetermined ratio is, for example, 1 / M.

At this time, the adaptive filters AF1 and AF2 search for the transfer function in correspondence with a predetermined ratio. Specifically, for the coefficient search generated in the shift registers SR1 and SR2 so that ^{the search units TS1 and TS2 receive the probe signals z−j} · X _{PRN for the coefficient search at the data rate thinned out by 1 / M.} The probe signal z ^−j · X _PRN is thinned out at 1 / M.

With such a configuration, for example, when the first-stage modulator SDM1 and the second-stage modulator SDM2, the adjustment filters CF1 and CF2, and the shift registers SR1 and SR2 operate at 40 MHz, noise is assumed when M = 4. The cancel filters NCF1 and NCF2 and the search units TS1 and TS2 operate at 10 MHz.

According to the present embodiment, the noise canceling filters NCF1 and NCF2, and the noise canceling filters NCF1 and NCF2, and the noise canceling filters NCF1 and NCF2 by performing 1 / M data thinning processing on the outputs of the adjustment filters CF1 and CF2 and the outputs of the shift registers SR1 and SR2. , The operating rates of the search units TS1 and TS2 can be reduced to 1 / M. As a result, the area occupied by the noise canceling filters NCF1 and NCF2, and the search units TS1 and TS2 and the power consumption can be reduced. The effect of folding back high-frequency components caused by thinning out data can be reduced by using adjustment filters CF1 and CF2, for example, a low-pass filter or the like. Other configurations, operations and effects are included in the description of the first embodiment.

(Embodiment 3)
Next, the ADC according to the third embodiment will be described. In the ADC of the present embodiment, the adjustment filter is divided into a noise canceling filter and a search unit. FIG. 12 is a block diagram illustrating the ADC according to the third embodiment.

As shown in FIG. 12, the ADC3 of the present embodiment includes a first-stage modulator SDM1, a second-stage modulator SDM2, a noise canceling circuit CCN1, a probe signal generation circuit XG, a plurality of adaptive filters AF1 and AF2, and a plurality of adjustment filters CF1. It includes CF2, CF3 and CF4, and a plurality of thinning blocks MB1, MB2, MB3 and MB4. The output side of the quantizer QT1 in the first-stage modulator SDM1 is connected to the adjustment filters CF1 and CF3. The output side of the quantizer QT2 in the next-stage modulator SDM2 is connected to the adjustment filters CF2 and CF4.

The adjustment filter CF1 is connected to the output of the quantizer QT1 in the first-stage modulator SDM1. _{The output signal DSO 1} output from the quantizer QT1 is input to the adjustment filter CF1. The adjustment filter CF1 adjusts the frequency characteristics _{of the output signal DSO 1 of the quantizer QT1.} The adjustment filter CF1 is connected to the thinning block MB1. The adjustment filter CF1 outputs the adjusted output signal to the thinning block MB1.

The thinning block MB1 is connected to the subsequent stage of the adjustment filter CF1. The thinning block MB1 reduces the data rate of the output signal whose frequency characteristics have been adjusted by the adjustment filter CF1 to a predetermined ratio. The predetermined percentage, for example, a 1 / _{N 1.} The thinned-out block MB1 outputs the thinned-out output signal to the search unit TS1 of the adaptive filter AF1.

At this time, the adaptive filter AF1 searches for the transfer function in correspondence with _{a predetermined ratio (1 / N 1).} More specifically, in order to receive at a data rate search unit TS1 is thinned out probe signal ^z -j _{· X PRN} for searching coefficient 1 / _{N 1,} a probe signal generated in the shift register SR1 ^{z -j} · X the _PRN, thinned out in the ₁ / _N 1.

The adjustment filter CF2 is connected to the output of the quantizer QT2 in the next-stage modulator SDM2. _{The output signal DSO 2} output from the quantizer QT2 is input to the adjustment filter CF2. The adjustment filter CF2 adjusts the frequency characteristics _{of the output signal DSO 2 of the quantizer QT2.} The adjustment filter CF2 is connected to the thinning block MB2. The adjustment filter CF2 outputs the adjusted output signal to the thinning block MB2.

The thinning block MB2 is connected to the subsequent stage of the adjustment filter CF2. The thinning block MB2 reduces the data rate of the output signal whose frequency characteristics have been adjusted by the adjustment filter CF2 to a predetermined ratio. The predetermined ratio is, for example, 1 / N ₂ . The thinned-out block MB2 outputs the thinned-out output signal to the search unit TS2 of the adaptive filter AF2.

At this time, the adaptive filter AF2 searches for the transfer function in correspondence with _{a predetermined ratio (1 / N 2).} Specifically, the probe signal z for coefficient search generated in the shift register SR2 is generated so that the search unit TS2 receives the probe signal z ^−j · X _PRN for coefficient search at the data rate thinned out by 1 / N _2. ^-J · X _PRN is thinned out by 1 / N _2.

The adjustment filter CF3 is connected to the output of the quantizer QT1 in the first-stage modulator SDM1. _{The output signal DSO 1} output from the quantizer QT1 is input to the adjustment filter CF3. The adjustment filter CF3 adjusts the frequency characteristics _{of the output signal DSO 1 of the quantizer QT1.} The adjustment filter CF3 is connected to the thinning block MB3. The adjustment filter CF3 outputs the adjusted output signal to the thinning block MB3.

The thinning block MB3 is connected to the subsequent stage of the adjustment filter CF3. The thinning block MB3 reduces the data rate of the output signal whose frequency characteristics have been adjusted by the adjustment filter CF3 to a predetermined ratio. The predetermined percentage, for example, a 1 / _{N 3.} The thinning block MB3 outputs the thinned output signal to the noise canceling filter NCF1.

The adjustment filter CF4 is connected to the output of the quantizer QT2 in the next-stage modulator SDM2. _{The output signal DSO 2} output from the quantizer QT2 is input to the adjustment filter CF4. The adjustment filter CF4 adjusts the frequency characteristics _{of the output signal DSO 2 of the quantizer QT2.} The adjustment filter CF4 is connected to the thinning block MB4. The adjustment filter CF4 outputs the adjusted output signal to the thinning block MB4.

The thinning block MB4 is connected to the subsequent stage of the adjustment filter CF4. The thinning block MB4 reduces the data rate of the output signal whose frequency characteristics have been adjusted by the adjustment filter CF4 to a predetermined ratio. The predetermined percentage, for example, a 1 / _{N 4.} The thinning block MB4 outputs the thinned output signal to the noise canceling filter NCF2.

The adaptive filter 1 has a conversion unit HK1. The conversion unit HK1 converts the tap coefficient based on the frequency characteristics adjusted by the adjustment filter CF1 and the adjustment filter CF3. The conversion unit HK1 outputs the converted tap coefficient to the noise canceling filter NCF2.

The adaptive filter 2 has a conversion unit HK2. The conversion unit HK2 converts the tap coefficient based on the frequency characteristics adjusted by the adjustment filter CF2 and the adjustment filter CF4. The conversion unit HK2 outputs the converted tap coefficient to the noise canceling filter NCF1.

The noise canceling filter NCF1 is a digital filter in which the output signal of the quantizer QT1 is input via the adjustment filter CF3 and the thinning block MB3. The noise canceling filter NCF1 has a tap coefficient based on the search result of the adaptive filter AF2. The noise canceling filter NCF1 performs filter processing in correspondence with a predetermined ratio (1 / N _3).

The noise canceling filter NCF2 is a digital filter in which the output signal of the quantizer QT2 is input via the adjustment filter CF4 and the thinning block MB4. The noise canceling filter NCF2 has a tap coefficient based on the search result of the adaptive filter AF1. The noise canceling filter NCF2 performs filter processing in correspondence with a predetermined ratio (1 / N _4).

The digital adder / subtractor DAS31 calculates the difference between the output signal S11 of the noise canceling filter NCF1 and the output signal S12 of the noise canceling filter NCF2. The digital adder / subtractor DAS31 outputs the calculated difference as an external output signal D _OUT .

In the ADC 2 of the second embodiment described above, in many cases, the adjustment filters CF1 and CF2 can be operated at low speeds of the noise canceling filters NCF1 and NCF2 and obtain desired conversion accuracy (noise characteristics) in the _{external output signal D OUT.} In addition, it is desirable to use a high-order filter that is as steep as possible.

However, when a steep high-order filter is used, the search units TS1 and TS2 of the adaptive filters AF1 and AF2 remove too much high-frequency components necessary for the search, which rather deteriorates the search accuracy. there is a possibility. That is, the noise canceling filters NCF1 and NCF2 and the search units TS1 and TS2 may have different characteristics required for the adjustment filters CF1 and CF2 which are the pre-filters.

In ADC3 of the present embodiment, the adjustment filter is divided into a noise canceling filter NCF1 and NCF2 and a search unit TS1 and TS2. With such a configuration, the noise canceling filters NCF1 and NCF2, and the search units TS1 and TS2 can be thinned out at _{individual rates (N 1} , N ₂ , N ₃ , N _3). can. Therefore, each thinning block MB1 to MB4 can be operated at an arbitrary speed.

In addition, in order to compensate for the difference between the noise canceling filters NCF1 and CF2 generated by separating the adjustment filters CF1 and CF4 and the transfer functions of the search units TS1 and TS2, the conversion units HK1 and HK2 that convert the coefficients are added. As described above, by configuring the ADC3 of the third embodiment, it is possible to reduce the mounting cost (area, current consumption) of the noise canceling filters NCF1 and NCF2 while ensuring the search accuracy of the transfer function.

(Embodiment 4)
Next, a system using the ADC according to the fourth embodiment will be described. The ADCs of Embodiments 1 to 3 described above can be applied to, for example, a millimeter wave radar system. The application examples of the ADCs of the first to third embodiments are not limited to the millimeter wave radar system. FIG. 13 is a block diagram illustrating a main part of the system using the ADC according to the embodiment.

As shown in FIG. 13, the millimeter-wave radar system of the present embodiment receives the baseband unit BBU, the high-frequency unit RFU, the low-pass filter LPF, the transmitting antenna ANTt, and n (n is an integer of 1 or more). The antennas ANTr [1] to ANTr [n] are provided. The high-frequency unit RFU performs various signal processing in the high-frequency band, includes a modulator MOD, an oscillator OSC, and a power amplifier PA as transmission circuits, and n mixers MIX [1] to MIX [n] and as reception circuits. It includes n amplifiers IA [1] to IA [n].

The baseband unit BBU is composed of, for example, one semiconductor chip such as a microcontroller, and performs various signal processing in the baseband. The baseband unit BBU includes n analog-to-digital converters ADC [1] to ADC [n], a CPU (Central Processing Unit), a RAM (Random Access Memory), a digital-analog converter DACU, and a flash. It is provided with a non-volatile memory NVM such as a memory.

The modulator MOD and oscillator OSC are a frequency-modulated transmission wave (FM-CW system transmission wave) or two transmission waves with different frequencies (two-frequency CW system) based on control from the baseband unit BBU. (Transmission wave) etc. are generated. The transmitted wave has a frequency such as a 60 GHz band or a 76 GHz band, and is transmitted from the transmitting antenna ANTt via the power amplifier PA.

On the other hand, the transmitted wave transmitted from the transmitting antenna ANTt is reflected by the object and then received by the n receiving antennas ANTr [1] to ANTr [n]. The n mixers MIX [1] to MIX [n] bring down the received waves (reflected waves) received by the receiving antennas ANTr [1] to ANTr [n], respectively, by using the transmitted wave from the oscillator OSC. By converting, n beat signals are output. The n beat signals are input to the n analog-to-digital converters ADC [1] to ADC [n] of the baseband unit BBU via a low-pass filter (anti-aliasing filter) LPF, respectively.

As the n analog-to-digital converters ADC [1] to ADC [n], the ADCs of the first to third embodiments can be used. The ADCs of the first to third embodiments have a MASH type and a ΣΔ type configuration, and convert a plurality of beat signals from the low-pass filter LPF into digital signals, respectively. The baseband unit BBU detects the distance to the object, the relative velocity, and the like by processing the digital signals from the analog-digital converters ADC [1] to ADC [n] using a CPU or the like.

Such millimeter-wave radar systems are used in various fields, such as automobiles and medical devices. Further, in order to improve the performance as a radar, the n analog-to-digital converters ADC [1] to ADC [n] are required to have high resolution (that is, a wide dynamic range) and a wide signal band. The ADCs of embodiments 1 to 3 can meet such requirements.

Although the invention made by the present inventor has been specifically described above based on the embodiment, the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. Needless to say. Further, a combination of the configurations of the first to fourth embodiments is also within the scope of the technical idea.

1, 2, 3 ADC
101, 102 ADC
AF1, AF2 Adaptive filter AS11, AS12, AS21 Analog adder / subtractor CF1, CF2, CF3, CF4 Adjustment filter CCN101, CCN102, CCN1 Noise canceling circuit DAC11, DAC12, DAC13, DAC21 Digital-to-analog conversion circuit DAS31 Digital adder / subtractor HK1, HK2 conversion Part INTU1, INTU2 Analog integrator unit LF1, LF2 Loop filter MB1, MB2, MB3, MB4 Thinning block NCF1, NCF2 Noise canceling filter QT1, QT2 Quantizer SDM101, SDM1 First stage modulator SDM102, SDM Second stage modulator SR1, SR2 Shift register TS1, TS2 Search unit XG probe signal generation circuit

Claims (20)

An external input signal to be an analog signal is input, including a first loop filter having a first analog integrator composed of an analog circuit and a first quantizer for quantizing the output signal of the first loop filter. 1st modulator and
A second modulator connected to the subsequent stage of the first modulator and including a second quantizer, and
A probe signal generation circuit that injects a probe signal into the first modulator,
The first adjustment filter that adjusts the frequency characteristics of the output signal of the first quantizer, and
A second adjustment filter that adjusts the frequency characteristics of the output signal of the second quantizer, and
A first adaptive filter that searches for the transfer function of the first modulator by observing the output signal of the first quantizer corresponding to the probe signal through the first adjustment filter.
A second adaptive filter that searches for the transfer function of the second modulator by observing the output signal of the second quantizer in response to the probe signal through the second adjustment filter.
A noise canceling circuit that cancels the quantization error that occurs in the first quantizer by using the search result of the first adaptive filter and the search result of the second adaptive filter.
Semiconductor device equipped with. The first adjustment filter and the second adjustment filter are low-pass filters that allow low-frequency components to pass through.
The semiconductor device according to claim 1. The noise canceling circuit
A digital filter in which the output signal of the first quantizer is input via the first adjustment filter, and a first noise canceling filter having a tap coefficient based on the search result of the second adaptive filter.
A digital filter in which the output signal of the second quantizer is input via the second adjustment filter, and a second noise canceling filter having a tap coefficient based on the search result of the first adaptive filter.
A first digital adder / subtractor that calculates the difference between the output signal of the first noise canceling filter and the output signal of the second noise canceling filter.
Have,
The semiconductor device according to claim 1. The first adaptive filter is
A first shift register that generates a plurality of coefficient search probe signals according to the probe signal, and
Using the plurality of coefficient search probe signals generated by the first shift register, a first search unit that searches for a tap coefficient to be searched, and a first search unit.
Have,
The second adaptive filter is
A second shift register that generates a plurality of coefficient search probe signals according to the probe signal, and
A second search unit that searches for a tap coefficient to be searched by using the plurality of coefficient search probe signals generated by the second shift register, and a second search unit.
Have,
The semiconductor device according to claim 1. The probe signal is a 1-bit pseudo-random signal.
The semiconductor device according to claim 1. The data rate of the output signal connected to each subsequent stage of the first adjustment filter and the second adjustment filter and whose frequency characteristics are adjusted by the first adjustment filter and the second adjustment filter is reduced to a predetermined ratio. Further equipped with multiple thinning blocks to make
The first adaptive filter and the second adaptive filter search for the transfer function in correspondence with the predetermined ratio.
The semiconductor device according to claim 1. A first thinning block, which is connected to the subsequent stage of the first adjustment filter and whose frequency characteristics are adjusted by the first adjustment filter, reduces the data rate of the output signal to a predetermined first ratio.
A second thinning block, which is connected to the subsequent stage of the second adjustment filter and whose frequency characteristics are adjusted by the second adjustment filter, reduces the data rate of the output signal to a predetermined second ratio.
With more
The first adaptive filter searches for the transfer function in correspondence with the first ratio.
The second adaptive filter searches for the transfer function in correspondence with the second ratio.
The semiconductor device according to claim 1. A third adjustment filter that adjusts the frequency characteristics of the output signal of the first quantizer, and
A fourth adjustment filter that adjusts the frequency characteristics of the output signal of the second quantizer, and
A third thinning block, which is connected to the subsequent stage of the third adjustment filter and whose frequency characteristics are adjusted by the third adjustment filter, reduces the data rate of the output signal to a predetermined third ratio.
A fourth thinning block, which is connected to the subsequent stage of the fourth adjustment filter and whose frequency characteristics are adjusted by the fourth adjustment filter, reduces the data rate of the output signal to a predetermined fourth ratio.
With more
The noise canceling circuit
A digital filter in which the output signal of the first quantizer is input via the third adjustment filter and the third thinning block, and the first noise canceling having a tap coefficient based on the search result of the second adaptive filter. With a filter
A digital filter in which the output signal of the second quantizer is input via the fourth adjustment filter and the fourth thinning block, and a second noise canceling having a tap coefficient based on the search result of the first adaptive filter. With a filter
A first digital adder / subtractor that calculates the difference between the output signal of the first noise canceling filter and the output signal of the second noise canceling filter.
Have,
The semiconductor device according to claim 7. The first noise canceling filter is filtered in correspondence with the third ratio.
The second noise canceling filter performs filter processing in correspondence with the fourth ratio.
The semiconductor device according to claim 8. The first adaptive filter has a first conversion unit that converts the tap coefficient based on the frequency characteristics adjusted by the first adjustment filter and the third adjustment filter.
The second adaptive filter has a second conversion unit that converts the tap coefficient based on the frequency characteristics adjusted by the second adjustment filter and the fourth adjustment filter.
The semiconductor device according to claim 9. A high-frequency unit that generates a plurality of beat signals by transmitting a transmitted wave to an object and down-converting a reflected wave from the object received by a plurality of antennas using the transmitted wave.
A low-pass filter to which the plurality of beat signals are input, and
A baseband unit that processes the plurality of beat signals from the low-pass filter, and
It is a system using a semiconductor device equipped with a millimeter-wave radar having
The baseband unit includes a plurality of semiconductor devices that convert the plurality of beat signals from the low-pass filter into digital signals, respectively.
Each of the plurality of semiconductor devices
An external input signal to be an analog signal is input, including a first loop filter having a first analog integrator composed of an analog circuit and a first quantizer for quantizing the output signal of the first loop filter. 1st modulator and
A second modulator connected to the subsequent stage of the first modulator and including a second quantizer, and
A probe signal generation circuit that injects a probe signal into the first modulator,
The first adjustment filter that adjusts the frequency characteristics of the output signal of the first quantizer, and
A second adjustment filter that adjusts the frequency characteristics of the output signal of the second quantizer, and
A first adaptive filter that searches for the transfer function of the first modulator by observing the output signal of the first quantizer in response to the probe signal through the first adjustment filter.
A second adaptive filter that searches for the transfer function of the second modulator by observing the output signal of the second quantizer in response to the probe signal through the second adjustment filter.
A noise canceling circuit that cancels the quantization error that occurs in the first quantizer by using the search result of the first adaptive filter and the search result of the second adaptive filter.
A system using a semiconductor device equipped with. The first adjustment filter and the second adjustment filter are low-pass filters that allow low-frequency components to pass through.
A system using the semiconductor device according to claim 11. The noise canceling circuit
A digital filter in which the output signal of the first quantizer is input via the first adjustment filter, and a first noise canceling filter having a tap coefficient based on the search result of the second adaptive filter.
A digital filter in which the output signal of the second quantizer is input via the second adjustment filter, and a second noise canceling filter having a tap coefficient based on the search result of the first adaptive filter.
A first digital adder / subtractor that calculates the difference between the output signal of the first noise canceling filter and the output signal of the second noise canceling filter.
Have,
A system using the semiconductor device according to claim 11. The first adaptive filter is
A first shift register that generates a plurality of coefficient search probe signals according to the probe signal, and
Using the plurality of coefficient search probe signals generated by the first shift register, a first search unit that searches for a tap coefficient to be searched, and a first search unit.
Have,
The second adaptive filter is
A second shift register that generates a plurality of coefficient search probe signals according to the probe signal, and
A second search unit that searches for a tap coefficient to be searched by using the plurality of coefficient search probe signals generated by the second shift register, and a second search unit.
Have,
A system using the semiconductor device according to claim 11. The probe signal is a 1-bit pseudo-random signal.
A system using the semiconductor device according to claim 11. The data rate of the output signal connected to each subsequent stage of the first adjustment filter and the second adjustment filter and whose frequency characteristics are adjusted by the first adjustment filter and the second adjustment filter is reduced to a predetermined ratio. Further equipped with multiple thinning blocks to make
The first adaptive filter and the second adaptive filter search for the transfer function in correspondence with the predetermined ratio.
A system using the semiconductor device according to claim 11. A first thinning block, which is connected to the subsequent stage of the first adjustment filter and whose frequency characteristics are adjusted by the first adjustment filter, reduces the data rate of the output signal to a predetermined first ratio.
A second thinning block, which is connected to the subsequent stage of the second adjustment filter and whose frequency characteristics are adjusted by the second adjustment filter, reduces the data rate of the output signal to a predetermined second ratio.
With more
The first adaptive filter searches for the transfer function in correspondence with the first ratio.
The second adaptive filter searches for the transfer function in correspondence with the second ratio.
A system using the semiconductor device according to claim 11. A third adjustment filter that adjusts the frequency characteristics of the output signal of the first quantizer, and
A fourth adjustment filter that adjusts the frequency characteristics of the output signal of the second quantizer, and
A third thinning block, which is connected to the subsequent stage of the third adjustment filter and whose frequency characteristics are adjusted by the third adjustment filter, reduces the data rate of the output signal to a predetermined third ratio.
A fourth thinning block, which is connected to the subsequent stage of the fourth adjustment filter and whose frequency characteristics are adjusted by the fourth adjustment filter, reduces the data rate of the output signal to a predetermined fourth ratio.
With more
The noise canceling circuit
A digital filter in which the output signal of the first quantizer is input via the third adjustment filter and the third thinning block, and the first noise canceling having a tap coefficient based on the search result of the second adaptive filter. With a filter
A digital filter in which the output signal of the second quantizer is input via the fourth adjustment filter and the fourth thinning block, and a second noise canceling having a tap coefficient based on the search result of the first adaptive filter. With a filter
A first digital adder / subtractor that calculates the difference between the output signal of the first noise canceling filter and the output signal of the second noise canceling filter.
Have,
A system using the semiconductor device according to claim 17. The first noise canceling filter is filtered in correspondence with the third ratio.
The second noise canceling filter performs filter processing in correspondence with the fourth ratio.
A system using the semiconductor device according to claim 18. An external input signal to be an analog signal is input, including a first loop filter having a first analog integrator composed of an analog circuit and a first quantizer for quantizing the output signal of the first loop filter. 1st modulator and
A second modulator connected to the subsequent stage of the first modulator and including a second quantizer, and
A probe signal generation circuit that injects a probe signal into the first modulator,
The first adjustment filter that adjusts the frequency characteristics of the output signal of the first quantizer, and
A second adjustment filter that adjusts the frequency characteristics of the output signal of the second quantizer, and
A first adaptive filter that searches for the transfer function of the first modulator by observing the output signal of the first quantizer in response to the probe signal through the first adjustment filter.
A second adaptive filter that searches for the transfer function of the second modulator by observing the output signal of the second quantizer in response to the probe signal through the second adjustment filter.
A noise canceling circuit that cancels the quantization error that occurs in the first quantizer by using the search result of the first adaptive filter and the search result of the second adaptive filter.
Analog-to-digital converter equipped with.

Images