JP2020020769A - Capacitance detection circuit - Google Patents

Abstract

To reduce noise.SOLUTION: A preamplifier 110 includes an operational amplifier OA1 and a feedback capacitor Cf. A driver 120 controls the voltages of a first line L1, a second line L2, and a sense node Ns. The driver 120 applies a driving voltage Vd with a first polarity between the first line L1 and the second line L2 in a first state φ1 and in a second state φ2, and applies a driving voltage with a second polarity opposite to the first polarity in a third state φ3. The preamplifier 110 is formed so that the charge of the feedback capacitor Cf is initialized in the first state φ1 and the feedback capacitor Cf is connected between the sensor node Ns and the output terminal of the operational amplifier OA1 in the second state φ2 and in the third state φ3.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a capacitance detection circuit.

  As the acceleration sensor, a capacitance type is widely used. The capacitance-type acceleration sensor has a movable electrode and a fixed electrode that are displaced in accordance with acceleration, and detects a change in capacitance formed by the electrodes. Such an acceleration sensor has a built-in capacitance detection circuit.

N. Yazdi, K. Najafi, "An interface IC for a capacitive silicon ug accelerometer", IEEE International Solid-State Circuits Conference, 1999 IEEE International Solid-State Circuits Conference.Digest of Technical Papers.ISSCC.First Edition (Cat. .99CH36278), pp132-133, 17, Feb, 1999, DOI: 10.1109 / ISSCC.1999.759161

  The detection circuit includes a preamplifier including an operational amplifier, a capacitor, and some analog switches. In such a preamplifier, kT / C noise is generated due to charging a capacitor via an analog switch. In order to reduce the kT / C noise, it is necessary to increase the size of the capacitor C, but this causes problems such as a decrease in operation speed and an increase in circuit area.

  The present invention has been made in such a situation, and an exemplary object of one embodiment of the present invention is to provide a capacitance detection circuit with reduced kT / C noise.

  One embodiment of the present invention relates to a detection circuit for detecting capacitances of a first sense capacitor and a second sense capacitor connected in series between a first line and a second line. The detection circuit includes a preamplifier including an operational amplifier and a feedback capacitor, and a driver for controlling a voltage of a first sense line, a second line, and a sense node connecting the first and second sense capacitors. The driver applies a drive voltage of a first polarity between the first line and the second line in the first state and the second state, and applies a drive voltage between the first line and the second line in the third state. The driving voltage of the second polarity opposite to the one polarity can be applied. The preamplifier is configured such that the charge of the feedback capacitor is initialized in the first state, and the feedback capacitor is connected between the sense node and the output terminal of the operational amplifier in the second state and the third state.

  According to this aspect, the difference between the first sense capacitor and the second sense capacitor can be detected by calculating the difference between the output voltages of the preamplifier obtained in the second state and the third state. In the second state and the third state, a common noise component is included in the output voltage of the preamplifier. Therefore, by taking the difference between them, the noise component is canceled and the effect of kT / C noise can be reduced.

  A reference voltage may be applied to the non-inverting input terminal of the operational amplifier. The driver applies a first voltage to the first line, applies a second voltage to the second line, applies a reference voltage to the sense node in the first state and the second state, and outputs the first voltage in the third state. It may be configured to apply a second voltage to the line and apply a first voltage to the second line. In the preamplifier, in the first state, the reference voltage is applied to both ends of the feedback capacitor, the inverting input terminal and the output terminal of the operational amplifier are short-circuited, and in the second state and the third state, between the sense node and the output terminal of the operational amplifier. A feedback capacitor may be configured to be connected.

  One end of the feedback capacitor may be connected to the sense node. The preamplifier is provided between the inverting input terminal and the output terminal of the operational amplifier and is turned on in the first state, and is provided between the other end of the feedback capacitor and the output terminal of the operational amplifier. It may further include a second switch that is turned on in the third state, and a third switch that is provided between the reference line to which the reference voltage is applied and the other end of the feedback capacitor and is turned on in the first state.

  One end of the feedback capacitor may be connected to an output terminal of the operational amplifier. The preamplifier is connected in parallel with the feedback capacitor and is turned on in the first state. The fourth switch is provided between the other end of the feedback capacitor and the inverting input terminal of the operational amplifier and turned on in the first state. And a sixth switch provided between the other end of the feedback capacitor and the sense node and turned on in the second state and the third state.

  The preamplifier may further include an input capacitor provided between the sense node and an inverting input terminal of the operational amplifier. Thereby, the influence of the offset voltage can be canceled. By calculating the difference between the second state and the third state, not only kT / C noise caused by the capacitance of the sense node but also kT / C noise caused by the capacitance of the connection node between the input capacitor and the operational amplifier can be canceled.

  The detection circuit may further include a difference amplifier that calculates a difference between the output voltage of the preamplifier in the second state and the output voltage of the preamplifier in the third state. The detection circuit may further include a ΔΣ modulator that converts an output of the difference amplifier into a digital signal.

  It should be noted that any combination of the above-described components, and any replacement of the components and expressions of the present invention between methods, apparatuses, systems, and the like are also effective as embodiments of the present invention.

  Furthermore, the description of this item (means for solving the problem) does not explain all the indispensable features of the present invention, and therefore, the sub-combinations of these features described can also be the present invention. .

  According to an embodiment of the present invention, the influence of noise can be reduced.

FIG. 3 is a circuit diagram of the acceleration sensor according to the embodiment. FIG. 3 is a block diagram of a capacitance detection circuit according to the first embodiment. FIGS. 3A to 3C are equivalent circuit diagrams of the capacitance detection circuit of FIG. 2 in the first state φ1 to the third state φ3. FIGS. 4A and 4B are diagrams illustrating the detection of the capacitance. FIG. 6 is a diagram illustrating dispersion of an output voltage Vout of the capacitance detection circuit. FIGS. 6A and 6B are diagrams illustrating the operation of the capacitance detection circuit according to the comparative technique. FIG. 9 is a diagram illustrating dispersion of an output voltage Vout of the capacitance detection circuit according to the comparative technique. FIG. 9 is a circuit diagram of a capacitance detection circuit according to a second example. FIGS. 9A to 9C are equivalent circuit diagrams of the capacitance detection circuit in FIG. 8 in the first state φ1 to the third state φ3. It is a block diagram of an acceleration sensor. FIG. 11 is a circuit diagram of a preamplifier and a difference amplifier of FIG.

  Hereinafter, the present invention will be described based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and the repeated description will be omitted as appropriate. In addition, the embodiments do not limit the invention, but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  FIG. 1 is a circuit diagram of the acceleration sensor 2 according to the embodiment. The acceleration sensor 2 includes a MEMS circuit 4 and a readout circuit 6. The MEMS circuit 4 and the read circuit 6 are integrated on one semiconductor substrate. The MEMS circuit 4 includes a movable electrode and a fixed electrode, between which sense capacitors Cm1 and Cm2 are formed. The sense capacitors Cm1 and Cm2 are provided in series between the first line L1 and the second line L2, and a connection node between them is referred to as a sense node Ns.

  The read circuit 6 includes a capacitance detection circuit 100. The capacitance detection circuit 100 includes a preamplifier 110 and a driver 120. The preamplifier 110 includes an operational amplifier OA1, a feedback capacitor Cf, and some switches SW. The driver 120 controls the voltages of the first line L1, the second line L2, and the sense node Ns.

  The capacitance detection circuit 100 can switch between the first state φ1 to the third state φ3.

  The driver 120 applies a drive voltage Vd of the first polarity between the first line L1 and the second line L2 in the first state φ1 and the second state φ2, and connects the first line L1 with the first line L1 in the third state φ3. A drive voltage -Vd having a second polarity opposite to the first polarity can be applied between the second lines L2.

  In the preamplifier 110, the charge of the feedback capacitor Cf is initialized in the first state φ1, and the feedback capacitor Cf is connected between the sense node Ns and the output terminal of the operational amplifier OA1 in the second state φ2 and the third state φ3. It is configured as follows.

  The above is the basic configuration of the capacitance detection circuit 100. The present invention extends to various devices and methods that can be grasped as the block diagram or circuit diagram of FIG. 1 or derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and embodiments will be described, not to narrow the scope of the present invention but to help understand the essence and operation of the present invention and to clarify them.

(First embodiment)
FIG. 2 is a block diagram of the capacitance detection circuit 100A according to the first embodiment. Driver 120 applies a first voltage (eg, power supply voltage Vdd) to first line L1 and applies a second voltage (eg, ground voltage Vss) to second line L2 in first state φ1 and second state φ2. , A reference voltage Vcom is applied to the sense node Ns. The reference voltage Vcom can be set at a midpoint between the first voltage and the second voltage.

  Driver 120 includes switches SW21 to SW25. The switches SW21 and SW24 are turned on in the first state φ1 and the second state φ2, and apply the first voltage Vdd to the first line L1 and apply the second voltage Vss to the second line L2. The switches SW22 and SW23 are turned on in the third state φ3, and apply the second voltage Vss to the first line L1 and apply the first voltage Vdd to the second line L2. Each of the pair of switches SW21 and SW22 and the pair of switches SW23 and SW24 may be configured by a CMOS inverter.

  The switch SW25 is turned on in the first state φ1, and applies the reference voltage Vcom to the sense node Ns.

  Preamplifier 110A includes an operational amplifier OA1, a feedback capacitor Cf, and an input capacitor Cs. The reference voltage Vcom is applied to the non-inverting input terminal (+) of the operational amplifier OA1.

  In the first state φ1, in the preamplifier 110A, the reference voltage Vcom is applied to both ends of the feedback capacitor Cf, and the inverting input terminal (−) and the output terminal of the operational amplifier OA1 are short-circuited. In the preamplifier 110, a feedback capacitor Cf is connected between the sense node Ns and the output terminal of the operational amplifier OA1 in the second state φ2 and the third state φ3.

  In the first embodiment, one end of the feedback capacitor Cf is connected to the sense node Ns. In order to realize the first state φ1 to the third state φ3, a plurality of switches SW1 to SW3 are provided. The first switch SW1 is provided between the inverting input terminal (−) and the output terminal of the operational amplifier OA1, and is turned on in the first state φ1. The second switch SW2 is provided between the other end of the feedback capacitor Cf and the output terminal of the operational amplifier OA1, and is turned on in the second state φ2 and the third state φ3. The third switch SW3 is provided between the reference line L3 to which the reference voltage Vcom is applied and the other end of the feedback capacitor Cf, and is turned on in the first state φ1.

  The above is the configuration of the capacitance detection circuit 100A. Subsequently, the operation will be described. FIGS. 3A to 3C are equivalent circuit diagrams of the capacitance detection circuit 100A in FIG. 2 in the first to third states φ1 to φ3.

  In the first state φ1 and the second state φ2 of FIGS. 3A and 3B, the first sense capacitor Cm1 is charged at Vdd-Vcom, and the second sense capacitor Cm2 is charged at Vcom-Vss. Hereinafter, Vss = 0V.

  In the first state φ1 of FIG. 3A, the output of the operational amplifier OA1 and the inverting input terminal are short-circuited, and a voltage follower is formed. The reference voltage Vcom is applied to both ends of the feedback capacitor Cf, and the charge is reset to zero. Since the virtual ground causes the voltage Vb at the inverting input terminal of the operational amplifier OA1 to be equal to the reference voltage Vcom, the reference voltage Vcom is also applied to both ends of the input capacitor Cs, and the charge is reset to zero.

  In the second state φ2 and the third state φ3 of FIGS. 3B and 3C, a voltage Vout corresponding to the first sense capacitance Cm1 and the second sense capacitance Cm2 is generated at the output terminal.

FIGS. 4A and 4B are diagrams illustrating the detection of the capacitance. The capacitor Cs is provided for canceling the offset voltage, and is omitted because capacitance detection can be ignored. FIG. 4A shows the second state φ2, and FIG. 4B shows the third state φ3. In the second state φ2, the voltage Va of the sense node Ns becomes equal to the reference voltage Vcom. The output voltage Vout1 at this time is given by equation (1).
Vout1 = − {VddCm1-Va (Cm1 + Cm2)} / Cf + Va (1)

In the third state φ3, the polarities of the voltages applied to the first and second sense capacitors Cm1 and Cm2 are inverted, and the output voltage Vout2 at this time is given by Expression (2).
Vout2 = − {VddCm2-Va (Cm1 + Cm2)} / Cf + Va (2)

The difference ΔV between the output voltage Vout1 obtained in the second state φ2 and the output voltage Vout2 obtained in the third state φ3 is expressed by Expression (3).
ΔV = Vout1-Vout2 = (Cm2-Cm1) / Cf × Vdd (3)
As is clear from equation (3), the difference ΔV does not include the voltage Va of the sense node Ns, and is therefore not affected by the charge of the kT / C noise injected into the sense node Ns.

  FIG. 5 is a diagram illustrating the dispersion of the output voltage Vout of the capacitance detection circuit 100A. The variance of the output voltage Vout is the magnitude of the amplitude fluctuation. The output voltage Vout in the second state φ2 includes noise variance, and in the third state φ3, the output voltage Vout includes signal component variance in addition to noise variance. By taking the difference between them, a low noise signal component can be extracted. When calculated by transient analysis, the variance of the signal component was 3.77 μV, and the variance of the signal component and the noise component obtained in the third state φ3 was 20.01 μV. Since the variance of the signal portion is sufficiently smaller than the variance of the signal and noise portions, the effectiveness of this embodiment can be confirmed.

  Further advantages of the capacitance detection circuit 100A become clear by comparison with a comparative technique. The capacitance detection circuit according to the comparative technique is similar in configuration to the first embodiment, but operates differently. Specifically, in the first embodiment, transition is made in three states φ1 to φ3, whereas in the comparative technique, transition is made in two states φ1 and φ3. FIGS. 6A and 6B are diagrams illustrating the operation of the capacitance detection circuit 100R according to the comparative technique. FIG. 6A shows the first state φ1, and FIG. 6B shows the third state φ3. In the comparison technique, a difference between the output voltage Vout in the first state φ1 and the output voltage Vout in the third state φ3 is acquired in a subsequent stage.

  FIG. 7 is a diagram illustrating the dispersion of the output voltage Vout of the capacitance detection circuit according to the comparative technique. It can be seen that the noise component cannot be reduced by taking the difference between the third state φ3 and the first state φ1. That is, in the comparative technique, the effect of kT / C noise on the sense node Ns can be reduced, but the effect of kT / C noise on the inverting input terminal of the operational amplifier OA1 remains. In the comparative technique, noise can be reduced by increasing the capacitance value, but it causes problems such as an increase in circuit area and power consumption and a decrease in response speed.

  On the other hand, according to the first embodiment, the effect is obtained that the effect of kT / C noise at the inverting input terminal of the operational amplifier OA1 as well as the sense node Ns can be reduced.

(Second embodiment)
FIG. 8 is a circuit diagram of a capacitance detection circuit 100B according to the second embodiment. The preamplifier 110B includes an operational amplifier OA1, a feedback capacitor Cf, an input capacitor Cs, and switches SW4 to SW6.

  One end of the feedback capacitor Cf is connected to the output terminal of the operational amplifier OA1. The fourth switch SW4 is connected in parallel with the feedback capacitor Cf, and is turned on in the first state φ1. The fifth switch SW5 is provided between the other end of the feedback capacitor Cf and the inverting input terminal of the operational amplifier OA1, and is turned on in the first state φ1. The sixth switch SW6 is provided between the other end of the feedback capacitor Cf and the sense node Ns, and is turned on in the second state φ2 and the third state φ3.

  FIGS. 9A to 9C are equivalent circuit diagrams of the capacitance detection circuit 100B in FIG. 8 in the first to third states φ1 to φ3. In the first state φ1, as in the first embodiment, the reference voltage Vcom is applied to both ends of the feedback capacitor Cf, and the inverting input terminal (−) and the output terminal of the operational amplifier OA1 are short-circuited. In the second state φ2 and the third state φ3, a feedback capacitor Cf is connected between the sense node Ns and the output terminal of the operational amplifier OA1.

  According to the second embodiment, the same effects as in the first embodiment can be obtained. According to those skilled in the art, the first embodiment and the second embodiment are merely examples, and there are various modifications in the topology of a plurality of switches, and such modifications are included in the scope of the present invention. Is understood.

  Next, the signal processing and configuration in the subsequent stage of the capacitance detection circuit 100 will be described. FIG. 10 is a block diagram of the acceleration sensor 2. The read circuit 6C includes a difference amplifier 10, a ΔΣ modulator 12, an integrator 14, and a controller 20 in addition to the capacitance detection circuit 100. The controller 20 controls the state transition of the capacitance detection circuit 100 and, in conjunction therewith, controls the states of the differential amplifier 10, the ΔΣ modulator 12, and the integrator 14 at the subsequent stage.

  The difference amplifier 10 samples the output voltage Vout of the driver 120 in the second state φ2 and the output voltage Vout of the driver in the third state φ3, and generates a voltage Vx according to the difference ΔV between them. The ΔΣ modulator 12 performs ΔΣ modulation on the voltage Vx and converts the voltage Vx into a digital output Dout which is a bit stream. The integrator 14 removes noise included in a high band due to noise shaping by ΔΣ modulation.

FIG. 11 is a circuit diagram of the preamplifier 100C and the difference amplifier 10 of FIG. The difference amplifier 10 includes a fully differential amplifier DA1, a plurality of capacitors C11 to C14, C21, C22, and a plurality of switches. In this embodiment, the difference amplifier 10 converts the single-ended signal Vout into differential signals V _OUTP and V _OUTN .

  In general, the ΔΣ modulator 12 includes a sub D / A converter that converts a digital output Dout into an analog signal, a subtractor that generates a difference between an input signal and an output of the sub D / A converter, and an integrator that integrates an output of the subtractor. , Quantizer to quantize the output of the integrator and generate a digital output Dout. The difference amplifier 10 in FIG. 11 has functions of a subtractor of the ΔΣ modulator 12 and a sub D / A converter.

  In the figure, the switch denoted by φxd is controlled by a signal obtained by adding a small delay to φx. Reference numerals 30 and 32 operate as sub D / A converters, and the L and H switches are turned on complementarily according to the digital output Dout in FIG.

  The present invention extends to various devices, methods, and circuits derived from the above description, and is not limited to any particular configuration. Hereinafter, more specific embodiments and modifications will be described not to narrow the scope of the present invention but to help understand the essence and operation of the present invention and to clarify them.

  Although the input capacitor Cs is provided in the first and second embodiments, the present invention is not limited to this, and the input capacitor Cs may be omitted.

  In FIG. 10, an A / D converter of ΔΣ modulation is used.

  In the embodiments, the acceleration sensor has been described as an application of the capacitance detection circuit 100. However, the present invention is not limited to this, and various capacitances can be detected. For example, the capacitance detection circuit 100 may be applied to a touch sensor or a microphone.

2 Accelerometer 4 MEMS circuit 6 Readout circuit 10 Difference amplifier 12 ΔΣ modulator 14 Integrator 20 Controller Cm1 First sense capacitor Cm2 Second sense capacitor Ns Sense node L1 First line L2 Second line 100 Capacitance detection circuit 110 Preamplifier OA1 Operational amplifier Cs Input capacitor Cf Feedback capacitor 120 Driver SW1 First switch SW2 Second switch SW3 Third switch SW4 Fourth switch SW5 Fifth switch SW6 Sixth switch

Claims (7)

A detection circuit for detecting capacitance of a first sense capacitor and a second sense capacitor connected in series between a first line and a second line,
A preamplifier including an operational amplifier and a feedback capacitor;
A driver for controlling a voltage of the first line, the second line, and a sense node connecting the first sense capacitor and the second sense capacitor;
With
The driver applies a driving voltage of a first polarity between the first line and the second line in a first state and a second state, and in a third state, the first line and the second line. A drive voltage having a second polarity opposite to the first polarity can be applied,
In the preamplifier, the charge of the feedback capacitor is initialized in the first state, and the feedback capacitor is connected between the sense node and an output terminal of the operational amplifier in the second state and the third state. A detection circuit characterized by being configured as described above. A reference voltage is applied to a non-inverting input terminal of the operational amplifier,
The driver is
In the first state and the second state, a first voltage is applied to the first line, a second voltage is applied to the second line, a reference voltage is applied to the sense node,
In the third state, the second voltage is applied to the first line, and the first voltage is applied to the second line.
The preamplifier,
In the first state, the reference voltage is applied across the feedback capacitor, the inverting input terminal and the output terminal of the operational amplifier are short-circuited,
The detection circuit according to claim 1, wherein the feedback capacitor is connected between the sense node and the output terminal of the operational amplifier in the second state and the third state. One end of the feedback capacitor is connected to the sense node,
The preamplifier,
A first switch provided between the inverting input terminal and the output terminal of the operational amplifier and turned on in the first state;
A second switch provided between the other end of the feedback capacitor and the output terminal of the operational amplifier, and turned on in the second state and the third state;
A third switch provided between a reference line to which the reference voltage is applied and the other end of the feedback capacitor, and turned on in the first state;
The detection circuit according to claim 2, further comprising: One end of the feedback capacitor is connected to the output terminal of the operational amplifier,
The preamplifier,
A fourth switch connected in parallel with the feedback capacitor and turned on in the first state;
A fifth switch provided between the other end of the feedback capacitor and the inverting input terminal of the operational amplifier and turned on in the first state;
A sixth switch provided between the other end of the feedback capacitor and the sense node and turned on in the second state and the third state;
The detection circuit according to claim 2, further comprising:   5. The detection circuit according to claim 1, wherein the preamplifier further includes an input capacitor provided between the sense node and an inverting input terminal of the operational amplifier.   The detection circuit according to claim 1, further comprising a difference amplifier that calculates a difference between an output voltage of the preamplifier in the second state and an output voltage of the preamplifier in the third state.   The detection circuit according to claim 6, further comprising a ΔΣ modulator that converts an output of the difference amplifier into a digital signal.

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